19-1207; Rev 0; 3/97 KIT ATION EVALU LE B A IL A AV +3.3V, 622Mbps, SDH/SONET 4:1 Serializer with Clock Synthesis and LVDS Inputs ____________________________Features ♦ Single +3.3V Supply ♦ 155Mbps Parallel to 622Mbps Serial Conversion ♦ 215mW Power ♦ LVDS Parallel Clock and Data Inputs ♦ Differential 3.3V PECL Serial-Data Output The MAX3691 is available in the extended-industrial temperature range (-40°C to +85°C), in a 32-pin TQFP package. ______________Ordering Information ________________________Applications 622Mbps SDH/SONET Transmission Systems PART TEMP. RANGE MAX3691ECJ 622Mbps ATM/SONET Access Nodes -40°C to +85°C PIN-PACKAGE 32 TQFP Pin Configuration appears at end of data sheet. Add/Drop Multiplexers Digital Cross Connects ___________________________________________________Typical Operating Circuit 0.1µF 0.1µF LVDS CRYSTAL REFERENCE VCC = +3.3V PCLKI- PCLKI+ RCLK- RCLK+ VCC GND PD0+ FIL+ PD0OVERHEAD GENERATION PD1+ PD1- 1.5k 24.9k MAX3691 PD2+ PD2PD3+ 100pF FILVCC = +3.3V PD3PCLKO- PCLKO+ SD- SD+ VCC = +3.3V 130Ω 130Ω MAX3667 THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE (Z0 = 50Ω) 82Ω 82Ω ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800 MAX3691 _______________General Description The MAX3691 serializer is ideal for converting 4-bitwide, 155Mbps parallel data to 622Mbps serial data in ATM and SDH/SONET applications. Operating from a single +3.3V supply, this device accepts low-voltage differential-signal (LVDS) clock and data inputs for interfacing with high-speed digital circuitry, and delivers a 3.3V PECL serial-data output. A fully integrated PLL synthesizes an internal 622Mbps serial clock from a 155.52MHz reference clock. MAX3691 +3.3V, 622Mbps, SDH/SONET 4:1 Serializer with Clock Synthesis and LVDS Inputs ABSOLUTE MAXIMUM RATINGS Terminal Voltage (with respect to GND) VCC .........................................................................-0.5V to 5V All Inputs.................................................-0.5V to (VCC + 0.5V) Output Current LVDS Outputs (PCLKO±)................................................10mA PECL Outputs (SD±).......................................................50mA Continuous Power Dissipation (TA = +85°C) TQFP (derate 10.20mW/°C above +85°C) ...................663mW Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-65°C to +160°C Lead Temperature (soldering, 10sec) .............................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, differential LVDS loads = 100Ω ±1%, PECL loads = 50Ω ±1% to (VCC - 2V), TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C.) PARAMETER Supply Current SYMBOL CONDITIONS MIN TYP MAX UNITS ICC PECL outputs unterminated 38 65 100 mA PECL OUTPUTS (SD±) Output High Voltage VOH Output Low Voltage VOL TA = +25°C to +85°C VCC - 1.03 VCC - 0.88 TA = -40°C VCC - 1.08 VCC - 0.88 TA = +25°C to +85°C VCC - 1.81 VCC - 1.62 TA = -40°C VCC - 1.95 VCC - 1.62 V V LVDS INPUTS AND OUTPUTS (PCLKI±, RCLK±, PCLKO±, PD_±) VI Differential input voltage = 100mV 0 2.4 V Differential Input Threshold VIDTH Common-mode voltage = 50mV -100 100 mV Threshold Hysteresis VHYST Input Voltage Range 70 Differential Input Resistance RIN Output High Voltage VOH Output Low Voltage VOL 0.925 Differential Output Voltage VOD 250 Change in Magnitude of Differential Output Voltage for Complementary States Output Offset Voltage Change in Magnitude of Output Offset Voltage for Complementary States Single-Ended Output Resistance Change in Magnitude of Single-Ended Output Resistance for Complementary States 2 85 Ω 1.475 V 400 mV 25 mV 1.275 V 25 mV 70 140 Ω ±1 ±10 % V ∆VOD VOS TA = +25°C 1.125 ∆VOS RO ∆RO 40 mV 115 100 _______________________________________________________________________________________ +3.3V, 622Mbps, SDH/SONET 4:1 Serializer with Clock Synthesis and LVDS Inputs (VCC = +3.0V to +3.6V, differential LVDS load = 100Ω ±1%, PECL loads = 50Ω ±1% to (VCC - 2V) TA = +25°C, unless otherwise noted. Typical values are at VCC = +3.3V.) (Note 1) PARAMETER SYMBOL Serial Clock Rate CONDITIONS MIN TYP fSCLK MAX 622.08 UNITS MHz Parallel Data-Setup Time tSU 200 ps Parallel Data-Hold Time tH 600 ps PCLKO to PCLKI Skew tSKEW -0.7 Φ0 Output Jitter PECL Differential Output Rise/Fall Time TA = -40°C to +85°C (Note 2) tR, tF +3.3 ns 13 psRMS 400 ps Note 1: AC characteristics guaranteed by design and characterization. Note 2: Assumes a 50% duty cycle ±5%. __________________________________________Typical Operating Characteristics (VCC = +3.0V to +3.6V, differential LVDS loads = 100Ω, unless otherwise noted.) PARALLEL DATA-SETUP TIME vs. TEMPERATURE SUPPLY CURRENT (mA) 80 60 40 20 0 -40 -60 -80 -100 -120 -50 -25 0 25 50 TEMPERATURE (°C) 75 100 250 MAX3691-03 MAX3691-02 -20 PARALLEL DATA-SETUP TIME (ps) MAX3691-01 100 PARALLEL DATA-HOLD TIME vs. TEMPERATURE PARALLEL DATA-HOLD TIME (ps) SUPPLY CURRENT vs. TEMPERATURE 230 210 190 170 150 -50 -25 0 25 50 TEMPERATURE (°C) 75 100 -50 -25 0 25 50 75 100 TEMPERATURE (°C) _______________________________________________________________________________________ 3 MAX3691 AC ELECTRICAL CHARACTERISTICS ____________________________Typical Operating Characteristics (continued) (VCC = +3.0V to +3.6V, differential LVDS loads = 100Ω, unless otherwise noted.) SERIAL-DATA OUTPUT EYE DIAGRAM (622Mbps, 27-1 PRBS) 1.21V SERIAL-DATA OUTPUT JITTER MAX3691-05 MAX3691-04 6 908mV MAX3691-06 PCLKO-to-PCLKI SKEW vs. TEMPERATURE PCLKO-TO-PCLKI SKEW (ns) MAX3691 +3.3V, 622Mbps, SDH/SONET 4:1 Serializer with Clock Synthesis and LVDS Inputs 4 OC-12 SONET MASK 10mV/ div 2 62mV/ div 0 fRCLK = 155.52MHz -2 0.59V -4 -50 -25 0 25 50 75 100 808mV 10ps/div 161ps/div Mean 23.88ns RMS∆ 8.418ps PkPk 70.2ps TEMPERATURE (°C) µ±1σ 68.774% µ±2σ 95.534% µ±3σ 99.738% ______________________________________________________________Pin Description PIN NAME FUNCTION 1, 3, 5, 7 PD0+ to PD3+ Noninverting LVDS Parallel Data Inputs. Data is clocked in on the PCLKI signal’s positive transition. 2, 4, 6, 8 PD0- to PD3- 9, 17, 18, 19, 24, 25, 32 GND Inverting LVDS Parallel Data Inputs. Data is clocked in on the PCLKI signal’s positive transition. Ground 10 PCLKO- Inverting LVDS Parallel-Clock Output. Use PCLKO to clock the overhead management circuit. 11 PCLKO+ Noninverting LVDS Parallel-Clock Output. Use PCLKO to clock the overhead management circuit. 12, 13, 16, 20, 21, 28, 29 VCC +3.3V Supply Voltage 14 SD- Inverting PECL Serial-Data Output 15 SD+ Noninverting PECL Serial-Data Output 22 FIL- Filter Capacitor Input. See Typical Operating Circuit for external-component connections. 23 FIL+ Filter Capacitor Input. See Typical Operating Circuit for external-component connections. 26 RCLK+ Noninverting LVDS Reference Clock Input. Connect (AC couple) a crystal reference clock (155.52MHz) to the RCLK inputs. 27 RCLK- Inverting LVDS Reference Clock Input. Connect (AC couple) a crystal reference clock (155.52MHz) to the RCLK inputs. 30 PCLKI+ Noninverting LVDS Parallel Clock Input. Connect the incoming parallel-data-clock signal to the PCLKI inputs. Note that data is updated on the positive transition of the PCLKI signal. 31 PCLKI- Inverting LVDS Parallel Clock Input. Connect the incoming parallel-data-clock signal to the PCLKI inputs. Note that data is updated on the positive transition of the PCLKI signal. 4 _______________________________________________________________________________________ +3.3V, 622Mbps, SDH/SONET 4:1 Serializer with Clock Synthesis and LVDS Inputs The MAX3691 serializer comprises a 4-bit parallel input register, a 4-bit shift register, control and timing logic, a PECL output buffer, LVDS input/output buffers, and a frequency-synthesizing PLL (consisting of a phase/ frequency detector, loop filter/amplifier, and voltagecontrolled oscillator). This device converts 4-bit-wide, 155Mbps data to 622Mbps serial data (Figure 1). The PLL synthesizes an internal 622Mbps reference used to clock the output shift register. This clock is generated by locking onto the external 155.52MHz reference-clock signal (RCLK). The incoming parallel data is clocked into the MAX3691 on the rising transition of the parallel-clockinput signal (PCLKI). The control and timing logic ensure proper operation if the parallel-input register is latched within a window of time that is defined with respect to the parallel-clock-output signal (PCLKO). PCLKO is the synthesized 622Mbps internal serialclock signal divided by four. The allowable PCLKO-toPCLKI skew is -0.7ns to +3.3ns. This defines a timing window at about the PCLKO rising edge, during which a PCLKI rising edge may occur. Figure 2 is the timing diagram. PD3+ PD3- LVDS PD2+ PD2- LVDS MAX3691 4-BIT PARALLEL INPUT REGISTER PD1+ PD1- LVDS PD0+ PD0- LVDS PCLKI+ LVDS PCLKI- SHIFT RCLK+ LVDS RCLK- PHASE/FREQ DETECT VCO CONTROL LATCH 4-BIT SHIFT REGISTER PECL SD+ SD- LVDS FIL+ FIL- PCLKO+ PCLKO- Figure 1. Functional Diagram _______________________________________________________________________________________ 5 MAX3691 _______________Detailed Description MAX3691 +3.3V, 622Mbps, SDH/SONET 4:1 Serializer with Clock Synthesis and LVDS Inputs PCLKO tSKEW PCLKI tSU PD_ tH VALID PARALLEL DATA* SD D3 D2 D1 D0 NOTE: SIGNALS SHOWN ARE DIFFERENTIAL. FOR EXAMPLE, PCLKO = (PCLKO+) - (PCLKO-). *PD3 = D3; PD2 = D2; PD1 = D1; PD0 = D0. Figure 2. Timing Diagram Low-Voltage Differential-Signal (LVDS) Inputs and Outputs The MAX3691 features LVDS inputs and outputs for interfacing with high-speed digital circuitry. The LVDS standard is based on the IEEE 1596.3 LVDS specification. This technology uses 250mV–400mV differential low-voltage swings to achieve fast transition times, minimized power dissipation, and noise immunity. For proper operation, the parallel-clock LVDS outputs (PCLKO+, PCLKO-) require 100Ω differential DC termi- 6 nation between the inverting and noninverting outputs. Do not terminate these outputs to ground. The parallel data and parallel clock LVDS inputs (PD_+, PD_-, PCLKI+, PCLKI-) are internally terminated with 100Ω differential input resistance, and therefore do not require external termination. PECL Outputs The serial-data PECL outputs (SD+, SD-) require 50Ω DC termination to (VCC - 2V). See the Alternative PECLOutput Termination section. _______________________________________________________________________________________ +3.3V, 622Mbps, SDH/SONET 4:1 Serializer with Clock Synthesis and LVDS Inputs __________________Pin Configuration Alternative PECL-Output Termination Layout Techniques GND FIL+ FILVCC VCC GND GND GND GND RCLK+ RCLKVCC VCC PCLKI+ PCLKIGND 25 26 27 28 29 30 31 32 MAX3691 16 15 14 13 12 11 10 9 VCC SD+ SDVCC VCC PCLKO+ PCLKOGND PD0+ PD0PD1+ PD1PD2+ PD2PD3+ PD3- 1 2 3 4 5 6 7 8 For best performance, use good high-frequency layout techniques. Filter voltage supplies and keep ground connections short. Use multiple vias where possible. Also, use controlled-impedance transmission lines to interface with the MAX3691 clock and data inputs and outputs. TOP VIEW 24 23 22 21 20 19 18 17 Figure 3 shows alternative PECL output-termination methods. Use Thevenin-equivalent termination when a (VCC - 2V) termination voltage is not available. If AC coupling is necessary, be sure that the coupling capacitor is placed following the 50Ω or Thevenin-equivalent DC termination. +3.3V 130Ω TQFP 130Ω MAX3691 SD+ Z0 = 50Ω PECL INPUTS ___________________Chip Information TRANSISTOR COUNT: 1633 SD- Z0 = 50Ω 82Ω 82Ω MAX3691 SD+ Z0 = 50Ω SD- Z0 = 50Ω 50Ω HIGHIMPEDENCE INPUTS 50Ω VCC - 2V Figure 3. Alternative PECL-Output Termination _______________________________________________________________________________________ 7 MAX3691 __________Applications Information ________________________________________________________Package Information TQFPPO.EPS MAX3691 +3.3V, 622Mbps, SDH/SONET 4:1 Serializer with Clock Synthesis and LVDS Inputs Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 8 ___________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 © 1997 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.