19-1210; Rev 0; 3/97 KIT ATION EVALU LE B A IL A AV +3.3V, 622Mbps, SDH/SONET 1:8 Deserializer with TTL Outputs ______________________________Features The MAX3680 deserializer is ideal for converting 622Mbps serial data to 8-bit-wide, 77Mbps parallel data in ATM and SDH/SONET applications. Operating from a single +3.3V supply, this device accepts PECL serial-clock and data inputs, and delivers TTL clock and data outputs. It also provides a TTL synchronization input that enables data realignment and reframing. The MAX3680 is available in the extended-industrial temperature range (-40°C to +85°C), in a 28-pin SSOP package. ♦ Single +3.3V Supply ♦ 622Mbps Serial to 77Mbps Parallel Conversion ♦ 165mW Power ♦ Synchronization Input for Data Realignment and Reframing ♦ Differential 3.3V PECL Clock and Data Inputs ♦ TTL Data Outputs and Synchronization Input __________________________Applications 622Mbps SDH/SONET Transmission Systems ________________Ordering Information 622Mbps ATM/SONET Access Nodes PART MAX3680EAI Add/Drop Multiplexers Digital Cross Connects TEMP. RANGE -40°C to +85°C PIN-PACKAGE 28 SSOP Pin Configuration appears at end of data sheet. ___________________________________________________________________Typical Operating Circuit VCC = +3.3V VCC PD7 VCC = +3.3V VCC = +3.3V MAX3680 130Ω PD6 130Ω PD5 SD+ PHOTODIODE MAX3675 SDPD4 82Ω PREAMP 100Ω LIMITING AMP DATA AND CLOCK RECOVERY OVERHEAD TERMINATION 82Ω PD3 VCC = +3.3V MAX3664 PD2 130Ω 130Ω PD1 SCLK+ SCLK- PD0 82Ω 82Ω PCLK SYNC GND THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE Z0 = 50Ω. ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800 MAX3680 _________________General Description MAX3680 +3.3V, 622Mbps, SDH/SONET 1:8 Deserializer with TTL Outputs ABSOLUTE MAXIMUM RATINGS Terminal Voltage (with respect to GND) VCC ...........................................................................-0.5V to 5V PECL Inputs (SD+/-, SCLK+/-) .................-0.5V to (VCC + 0.5V) TTL Input (SYNC) .....................................-0.5V to (VCC + 0.5V) TTL Outputs (PCLK, PD_).........................-0.5V to (VCC + 0.5V) Continuous Power Dissipation (TA = +85°C) SSOP (derate 9.52mW/°C above +85°C) ......................619mW Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-65°C to +160°C Lead Temperature (soldering, 10sec) .............................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C.) PARAMETER Supply Current SYMBOL ICC CONDITIONS TTL outputs = high MIN TYP MAX UNITS 25 50 90 mA PECL INPUTS (SD+/-, SCLK+/-) Input High Voltage VIH VCC - 1.16 VCC - 0.88 V Input Low Voltage VIL VCC - 1.81 VCC - 1.48 V Input High Current IIH VIN = VIH(MAX) -10 10 µA Input Low Current IIL VIN = VIL(MAX) -10 10 µA TTL INPUT AND OUTPUTS (SYNC, PCLK, PD_) Input High Voltage VIH Input Low Voltage VIL Input High Current IIH VIN = VIH(MAX) -10 IIL Input Low Current 2.0 V 0.8 V 10 µA VIN = VIL(MAX) -10 10 µA Output High Voltage VOH Output sourcing = 400µA 2.4 VCC V Output Low Voltage VOL Output sinking = 400µA 0 0.44 V MAX UNITS AC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER Maximum Serial Clock Frequency SYMBOL CONDITIONS MIN TYP fSCLK 622 MHz Serial Data Setup Time tSU 800 ps Serial Data Hold Time tH 50 ps Parallel Clock to Data Output Delay tCLK-Q VCC = 3.3V, CL = 18pF -200 500 Note 1: AC characteristics guaranteed by design and characterization. 2 _______________________________________________________________________________________ 1300 ps +3.3V, 622Mbps, SDH/SONET 1:8 Deserializer with TTL Outputs MAXIMUM SERIAL-CLOCK FREQUENCY vs. TEMPERATURE 1.2 1.1 1.0 0.9 0.8 360 320 280 240 200 -25 0 25 50 75 100 -50 -25 0 25 50 75 TEMPERATURE (°C) TEMPERATURE (°C) SERIAL DATA-HOLD TIME vs. TEMPERATURE SUPPLY CURRENT vs. TEMPERATURE 70 MAX3680-03 400 280 220 VCC = 3.6V 60 SUPPLY CURRENT (mA) 340 100 MAX3680-04 -50 SERIAL DATA-HOLD TIME (ps) MAX3680-02 400 SERIAL DATA-SETUP TIME (ps) MAX3680-01 SERIAL CLOCK FREQUENCY (GHz) 1.3 SERIAL DATA-SETUP TIME vs. TEMPERATURE 50 VCC = 3.3V 40 VCC = 3.0V 30 20 160 10 100 0 -50 -25 0 25 50 TEMPERATURE (°C) 75 100 -50 -25 0 25 50 75 100 TEMPERATURE (°C) _______________________________________________________________________________________ 3 MAX3680 __________________________________________Typical Operating Characteristics (VCC = +3.0V to +3.6V, unless otherwise noted.) MAX3680 +3.3V, 622Mbps, SDH/SONET 1:8 Deserializer with TTL Outputs ______________________________________________________________Pin Description PIN NAME FUNCTION 1, 2, 5, 8, 14, 18, 25 VCC +3.3V Supply Voltage 3 SD+ Noninverting PECL Serial Data Input. Data is clocked on the SCLK signal’s positive transition. 4 SD- Inverting PECL Serial Data Input. Data is clocked on the SCLK signal’s positive transition. 6 SCLK+ Noninverting PECL Serial Clock Input 7 SCLK- Inverting PECL Serial Clock Input 9, 11, 12, 16, 20, 23, 27 GND Ground 10 SYNC TTL Synchronization Pulse Input. Pulse high for at least two SCLK periods to shift the data alignment by dropping one bit in the serial input data stream. 13 PCLK TTL Parallel Clock Output 15, 17, 19, 21, 22, 24, 26, 28 PD0–PD7 TTL Parallel Data Outputs. Data is updated on the falling edge of PCLK. See Figure 2 for the relationship between serial-data-bit position and output-data-bit assignment. _______________Detailed Description The MAX3680 deserializer uses an 8-bit shift register, 8-bit parallel output register, 3-bit counter, PECL input buffers, and TTL input/output buffers to convert 622Mbps serial data to 8-bit-wide, 77Mbps parallel data (Figure 1). The input shift register continuously clocks incoming data on the positive transition of the serial clock (SCLK) input signal. The 3-bit counter generates a parallel output clock (PCLK) by dividing down the serial clock frequency. The PCLK signal is used to clock the parallel output register. During normal operation, the counter divides the SCLK frequency by eight, causing the output register to latch every eight bits of incoming serial data. The synchronization input (SYNC) is used for data realignment and reframing. When the SYNC signal is pulsed high for at least two SCLK cycles, PCLK is delayed by one SCLK cycle, causing the first incoming bit of the serial input data stream to be dropped. This realignment is guaranteed to occur within two PCLK cycles of the SYNC rising edge. See Figure 2 for the functional timing diagrams and Figure 3 for the timing parameters diagram. TTL SD+ SD- 8-BIT SHIFT REGISTER SCLK+ SCLK- TTL PECL TTL PECL TTL 8-BIT PARALLEL OUTPUT REGISTER TTL MAX3680 TTL TTL SYNC TTL 3-BIT COUNTER Figure 1. Functional Diagram 4 TTL _______________________________________________________________________________________ TTL PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PCLK +3.3V, 622Mbps, SDH/SONET 1:8 Deserializer with TTL Outputs MAX3680 SCLK* SD* D1- D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 PCLK PD7 D8- D0 D8 PD6 D7- D1 D9 PD5 D6- D2 D10 PD4 D5- D3 D11 PD3 D4- D4 D12 PD2 D3- D5 D13 PD1 D2- D6 D14 PD0 D1- D7 D15 * SIGNAL SHOWN IS DIFFERENTIAL. FOR EXAMPLE, SCLK = (SCLK+) - (SCLK-). Figure 2a. Functional Timing Diagram—Normal Operation _______________________________________________________________________________________ 5 MAX3680 +3.3V, 622Mbps, SDH/SONET 1:8 Deserializer with TTL Outputs SCLK* SD* D1- D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 SYNC PCLK PD7 D8- D1 D9 PD6 D7- D2 D10 PD5 D6- D3 D11 PD4 D5- D4 D12 PD3 D4- D5 D13 PD2 D3- D6 D14 PD1 D2- D7 D15 PD0 D1- D8 D16 * SIGNAL SHOWN IS DIFFERENTIAL. FOR EXAMPLE, SCLK = (SCLK+) - (SCLK-). Figure 2b. Functional Timing Diagram—SYNC Operation tSCLK = 1 / fSCLK SCLK* tSU tH SD* PCLK tCLK-Q PD0–PD7 * SIGNAL SHOWN IS DIFFERENTIAL. FOR EXAMPLE, SCLK = (SCLK+) - (SCLK-). Figure 3. Timing Parameters 6 _______________________________________________________________________________________ +3.3V, 622Mbps, SDH/SONET 1:8 Deserializer with TTL Outputs __________Applications Information THEVENIN-EQUIVALENT TERMINATION +3.3V 130Ω 130Ω MAX3680 ZO = 50Ω Alternative PECL Input Termination Figure 4 shows alternative PECL input-termination methods. Use Thevenin-equivalent termination when a (VCC - 2V) termination voltage is not available. If AC coupling is necessary, such as when interfacing with an ECL-output device, use the ECL AC-coupling termination. MAX3680 PECL Inputs The serial data and clock PECL inputs (SD+, SD-, SCLK+, SCLK-) require 50Ω termination to (VCC - 2V) when interfacing with a PECL source (see Alternative PECL Input Termination). PECL INPUTS ZO = 50Ω 82Ω 82Ω Layout Techniques For best performance, use good high-frequency layout techniques. Filter voltage supplies and keep ground connections short. Use multiple vias where possible. Also, use controlled impedance transmission lines to interface with the MAX3680 data inputs. ECL AC-COUPLING TERMINATION +3.3V 1.6k 1.6k ZO = 50Ω MAX3680 50Ω __________________Pin Configuration ZO = 50Ω PECL INPUTS -2V TOP VIEW 50Ω 2.7k 28 PD7 VCC 1 VCC 2 27 GND SD+ 3 26 PD6 SD- 4 25 VCC VCC 5 SCLK+ 6 MAX3680 2.7k -2V Figure 4. Alternative PECL Input Termination 24 PD5 23 GND SCLK- 7 22 PD4 VCC 8 21 PD3 GND 9 20 GND SYNC 10 19 PD2 GND 11 18 VCC GND 12 17 PD1 PCLK 13 16 GND VCC 14 15 PD0 ___________________Chip Information TRANSISTOR COUNT: 1346 SSOP _______________________________________________________________________________________ 7 ________________________________________________________Package Information SSOP.EPS MAX3680 +3.3V, 622Mbps, SDH/SONET 1:8 Deserializer with TTL Outputs Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 8 ___________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 © 1997 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.