BF1100; BF1100R Dual-gate MOS-FETs Rev. 02 — 13 November 2007 Product data sheet IMPORTANT NOTICE Dear customer, As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors, which will be used in future data sheets together with new contact details. In data sheets where the previous Philips references remain, please use the new links as shown below. http://www.philips.semiconductors.com use http://www.nxp.com http://www.semiconductors.philips.com use http://www.nxp.com (Internet) [email protected] use [email protected] (email) The copyright notice at the bottom of each page (or elsewhere in the document, depending on the version) - © Koninklijke Philips Electronics N.V. (year). All rights reserved is replaced with: - © NXP B.V. (year). All rights reserved. If you have any questions related to the data sheet, please contact our nearest sales office via e-mail or phone (details via [email protected]). Thank you for your cooperation and understanding, NXP Semiconductors NXP Semiconductors Product specification Dual-gate MOS-FETs BF1100; BF1100R FEATURES • Specially designed for use at 9 to 12 V supply voltage and substrate interconnected and an internal bias circuit to ensure good cross-modulation performance during AGC. • Short channel transistor with high forward transfer admittance to input capacitance ratio CAUTION • Low noise gain controlled amplifier up to 1 GHz • Superior cross-modulation performance during AGC. APPLICATIONS • VHF and UHF applications such as television tuners and professional communications equipment. DESCRIPTION Enhancement type field-effect transistor in a plastic microminiature SOT143 or SOT143R package. The transistor consists of an amplifier MOS-FET with source 4 PIN SYMBOL 1 s, b 2 d drain 3 g2 gate 2 4 g1 gate 1 DESCRIPTION source handbook, halfpage 3 3 1 Top view PINNING d d handbook, halfpage The device is supplied in an antistatic package. The gate-source input must be protected against static discharge during transport or handling. 4 g2 g2 g1 g1 2 2 s,b MAM124 BF1100 marking code: %MY. 1 Top view s,b MAM125 - 1 BF1100R marking code: %MZ. Fig.1 Simplified outline (SOT143) and symbol. Fig.2 Simplified outline (SOT143R) and symbol. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VDS drain-source voltage − − 14 V ID drain current − − 30 mA Ptot total power dissipation − − 200 mW Tj operating junction temperature − − 150 °C yfs forward transfer admittance 24 28 33 mS Cig1-s input capacitance at gate 1 − 2.2 2.6 pF Crs reverse transfer capacitance f = 1 MHz − 25 35 fF F noise figure f = 800 MHz − 2 − dB Rev. 02 - 13 November 2007 2 of 15 NXP Semiconductors Product specification Dual-gate MOS-FETs BF1100; BF1100R LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDS drain-source voltage − 14 V ID drain current − 30 mA IG1 gate 1 current − ±10 mA IG2 gate 2 current − ±10 mA Ptot total power dissipation see Fig.3 BF1100 up to Tamb = 50 °C; note 1 − 200 mW BF1100R up to Tamb = 40 °C; note 1 − 200 mW Tstg storage temperature −65 +150 °C Tj operating junction temperature − +150 °C Note 1. Device mounted on a printed-circuit board. MLD155 250 handbook, halfpage Ptot (mW) 200 MLD156 40 Y fs (mS) 30 150 20 BF1100R BF1100 100 10 50 0 0 0 50 100 50 150 200 Tamb ( oC) Fig.4 Fig.3 Power derating curves. Rev. 02 - 13 November 2007 0 50 100 150 T j ( oC) Forward transfer admittance as a function of junction temperature; typical values. 3 of 15 NXP Semiconductors Product specification Dual-gate MOS-FETs BF1100; BF1100R THERMAL CHARACTERISTICS SYMBOL Rth j-a Rth j-s PARAMETER CONDITIONS VALUE UNIT BF1100 500 K/W BF1100R 550 K/W thermal resistance from junction to ambient note 1 thermal resistance from junction to soldering point note 2 BF1100 Ts = 92 °C 290 K/W BF1100R Ts = 78 °C 360 K/W Notes 1. Device mounted on a printed-circuit board. 2. Ts is the temperature at the soldering point of the source lead. STATIC CHARACTERISTICS Tj = 25 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT V(BR)G1-SS gate 1-source breakdown voltage VG2-S = VDS = 0; IG1-S = 1 mA 13.2 20 V V(BR)G2-SS gate 2-source breakdown voltage VG1-S = VDS = 0; IG2-S = 1 mA 13.2 20 V V(F)S-G1 forward source-gate 1 voltage VG2-S = VDS = 0; IS-G1 = 10 mA 0.5 1.5 V V(F)S-G2 forward source-gate 2 voltage VG1-S = VDS = 0; IS-G2 = 10 mA 0.5 1.5 V VG1-S(th) gate 1-source threshold voltage VG2-S = 4 V; VDS = 9 V; ID = 20 µA 0.3 1 V VG2-S = 4 V; VDS = 12 V; ID = 20 µA 0.3 1 V VG1-S = 4 V; VDS = 9 V; ID = 20 µA 0.3 1.2 V VG1-S = 4 V; VDS = 12 V; ID = 20 µA 0.3 1.2 V VG2-S = 4 V; VDS = 9 V; RG1 = 180 kΩ; note 1 8 13 mA VG2-S = 4 V; VDS = 12 V; RG1 = 250 kΩ; note 2 8 13 mA VG2-S(th) IDSX gate 2-source threshold voltage drain-source current IG1-SS gate 1 cut-off current VG2-S = VDS = 0; VG1-S = 12 V − 50 nA IG2-SS gate 2 cut-off current VG1-S = VDS = 0; VG2-S = 12 V − 50 nA Notes 1. RG1 connects gate 1 to VGG = 9 V; see Fig.27. 2. RG1 connects gate 1 to VGG = 12 V; see Fig.27. Rev. 02 - 13 November 2007 4 of 15 NXP Semiconductors Product specification Dual-gate MOS-FETs BF1100; BF1100R DYNAMIC CHARACTERISTICS Common source; Tamb = 25 °C; VG2-S = 4 V; ID = 10 mA; unless otherwise specified. SYMBOL PARAMETER yfs CONDITIONS forward transfer admittance input capacitance at gate 1 Cig1-s input capacitance at gate 2 Cig2-s drain-source capacitance Cos MIN. TYP. MAX. UNIT pulsed; Tj = 25 °C VDS = 9 V 24 28 33 mS VDS = 12 V 24 28 33 mS VDS = 9 V − 2.2 2.6 pF VDS = 12 V − 2.2 2.6 pF VDS = 9 V − 1.6 − pF VDS = 12 V − 1.4 − pF VDS = 9 V − 1.4 1.8 pF VDS = 12 V − 1.1 1.5 pF VDS = 9 V − 25 35 fF VDS = 12 V − 25 35 fF VDS = 9 V − 2 2.8 dB VDS = 12 V − 2 2.8 dB f = 1 MHz f = 1 MHz f = 1 MHz reverse transfer capacitance f = 1 MHz Crs F f = 800 MHz; GS = GSopt; BS = BSopt noise figure MLD157 0 MLD158 120 handbook, halfpage handbook, gain halfpage Vunw (dBµV) reduction (dB) 10 (1) 110 (2) 20 100 30 90 40 80 50 0 1 2 3 4 0 10 20 30 VAGC (V) 40 50 gain reduction (dB) (1) RG = 250 kΩ to VGG = 12 V (2) RG = 180 kΩ to VGG = 9 V fw = 50 MHz; funw = 60 MHz; Tamb = 25 °C. f = 50 MHz. Tj = 25 °C. Fig.6 Fig.5 Gain reduction as a function of the AGC voltage; typical values. Rev. 02 - 13 November 2007 Unwanted voltage for 1% cross-modulation as a function of gain reduction; typical values; see Fig.27. 5 of 15 NXP Semiconductors Product specification Dual-gate MOS-FETs BF1100; BF1100R MLD159 20 MLD160 20 handbook, halfpage handbook, halfpage ID (mA) 16 ID (mA) 16 V G1 S = 1.4 V 1.3 V 1.2 V 12 V G2 S = 4 V 3 V 2.5 V 2V 12 1.1 V 1.5 V 8 8 1.0 V 0.9 V 4 4 1V 0 0 0 4 8 12 0 16 0.4 0.8 1.2 1.6 2.0 V G1 S (V) V DS (V) VG2-S = 4 V. Tj = 25 °C. VDS = 9 to 12 V. Tj = 25 °C. Fig.7 Output characteristics; typical values. MLD161 250 Fig.8 Transfer characteristics; typical values. MLD162 40 handbook, halfpage handbook, halfpage I G1 (µA) V G2 S = 4 V y fs (mS) 200 3.5 V V G2 S = 4 V 3.5 V 30 3V 150 3V 20 100 2.5 V 10 2V 50 2.5 V 2V 0 0 0 1 2 V G1 S (V) 3 VDS = 9 to 12 V. Tj = 25 °C. Fig.9 0 10 20 I D (mA) 30 VDS = 9 to 12 V. Tj = 25 °C. Gate 1 current as a function of gate 1 voltage; typical values. Fig.10 Forward transfer admittance as a function of drain current; typical values. Rev. 02 - 13 November 2007 6 of 15 NXP Semiconductors Product specification Dual-gate MOS-FETs BF1100; BF1100R MLD164 MLD163 16 20 handbook, halfpage handbook, halfpage ID (mA) R G1 = 100 kΩ ID (mA) 12 147 kΩ 15 180 kΩ 205 kΩ 8 249 kΩ 10 301 kΩ 402 kΩ 511 kΩ 4 5 0 0 0 20 40 60 I G1 (µA) 80 0 4 8 12 V GG = V DS (V) 16 VG2-S = 4 V. RG1 connected to VGG. Tj = 25 °C. VDS = 9 to 12 V. VG2-S = 4 V. Tj = 25 °C. Fig.11 Drain current as a function of gate 1 current; typical values. MLD165 12 handbook, halfpage Fig.12 Drain current as a function of gate 1 supply voltage (= VGG) and drain supply voltage; typical values; see Fig.27. MLD166 12 handbook, halfpage ID (mA) ID (mA) 8 8 4 4 0 0 0 2 4 6 8 10 V GG (V) VDS = 9 V; VG2-S = 4 V. RG1 = 180 kΩ (connected to VGG); Tj = 25 °C. 0 4 8 V GG (V) 12 VDS = 12 V; VG2-S = 4 V. RG1 = 250 kΩ (connected to VGG); Tj = 25 °C. Fig.13 Drain current as a function of gate 1 voltage (= VGG); typical values; see Fig.27. Fig.14 Drain current as a function of gate 1 voltage; (= VGG); typical values; see Fig.27. Rev. 02 - 13 November 2007 7 of 15 NXP Semiconductors Product specification Dual-gate MOS-FETs BF1100; BF1100R MLD167 50 handbook, halfpage MLD168 50 handbook, halfpage I G1 (µA) 40 I G1 (µA) 40 V GG = 9 V V GG = 12 V 11 V 8V 10 V 7V 30 9V 30 8V 6V 7V 5V 20 20 4V 10 10 0 0 0 2 4 V G2 S (V) 6 0 2 4 6 V G2 S (V) VDS = 9 V. RG1 = 180 kΩ (connected to VGG). Tj = 25 °C. VDS = 12 V. RG1 = 250 kΩ (connected to VGG). Tj = 25 °C. Fig.15 Gate 1 current as a function of gate 2 voltage; typical values. Fig.16 Gate 1 current as a function of gate 2 voltage; typical values. MLD169 16 MLD170 16 handbook, halfpage handbook, halfpage ID (mA) ID (mA) V GG = 9 V 12 12 V GG = 12 V 8 11 V 10 V 9V 8V 7V 8V 7V 6V 8 5V 4V 4 4 0 0 0 2 4 V G2 S (V) 6 0 2 VDS = 9 V. VDS = 12 V. RG1 = 180 kΩ (connected to VGG). Tj = 25 °C. RG1 = 250 kΩ (connected to VGG). Tj = 25 °C. Fig.17 Drain current as a function of the gate 2 voltage; typical values; see Fig.27. 4 V G2 S (V) 6 Fig.18 Drain current as a function of the gate 2 voltage; typical values; see Fig.27. Rev. 02 - 13 November 2007 8 of 15 NXP Semiconductors Product specification Dual-gate MOS-FETs BF1100; BF1100R MLD172 10 2 handbook, halfpage MLD173 10 3 10 3 ϕ rs (deg) y rs (µS) y is (mS) 10 2 10 ϕ rs b is 10 2 y rs 10 1 10 g is 10 1 10 102 f (MHz) 1 10 3 10 VDS = 9 V; VG2 = 4 V. ID = 10 mA; Tamb = 25 °C. 102 f (MHz) 10 3 1 VDS = 9 V; VG2 = 4 V. ID = 10 mA; Tamb = 25 °C. Fig.19 Input admittance as a function of frequency; typical values. MLD174 10 2 Fig.20 Reverse transfer admittance and phase as a function of frequency; typical values. 10 2 ϕ fs y fs y fs (mS) MLD175 10 handbook, halfpage yos (mS) bos (deg) 1 ϕ fs 10 10 10 1 gos 1 1 10 102 f (MHz) 10 3 VDS = 9 V; VG2 = 4 V. ID = 10 mA; Tamb = 25 °C. 10 2 10 102 f (MHz) 10 3 VDS = 9 V; VG2 = 4 V. ID =10 mA; Tamb = 25 °C. Fig.21 Forward transfer admittance and phase as a function of frequency; typical values. Fig.22 Output admittance as a function of frequency; typical values. Rev. 02 - 13 November 2007 9 of 15 NXP Semiconductors Product specification Dual-gate MOS-FETs BF1100; BF1100R MLD176 10 2 handbook, halfpage MLD177 10 3 10 3 ϕ rs (deg) y rs (µS) y is (mS) 10 2 10 ϕ rs b is 10 2 y rs 10 1 10 g is 10 1 10 102 f (MHz) 1 1 10 3 10 VDS = 12 V; VG2 = 4 V. ID = 10 mA; Tamb = 25 °C. 102 f (MHz) 10 3 VDS = 12 V; VG2 = 4 V. ID = 10 mA; Tamb = 25 °C. Fig.23 Input admittance as a function of frequency; typical values. MLD178 10 2 y fs 10 2 ϕ fs y fs (mS) Fig.24 Reverse transfer admittance and phase as a function of frequency; typical values. MLD179 10 handbook, halfpage yos (mS) (deg) bos 1 ϕ fs 10 10 10 1 gos 1 1 10 102 f (MHz) 10 3 VDS = 12 V; VG2 = 4 V. ID = 10 mA; Tamb = 25 °C. 10 2 10 102 f (MHz) 10 3 VDS = 12 V; VG2 = 4 V. ID = 10 mA; Tamb = 25 °C. Fig.25 Forward transfer admittance and phase as a function of frequency; typical values. Fig.26 Output admittance as a function of frequency; typical values. Rev. 02 - 13 November 2007 10 of 15 NXP Semiconductors Product specification Dual-gate MOS-FETs BF1100; BF1100R VAGC handbook, full pagewidth R1 10 k Ω C1 4.7 nF C2 R GEN 50 Ω R2 50 Ω C3 DUT 4.7 nF 12 pF L1 ≈ 450 nH RL 50 Ω C4 RG 4.7 nF VI VGG V DS MGC420 For VGG = VDS = 9 V, RG = 180 kΩ. For VGG = VDS = 12 V, RG = 250 kΩ. Fig.27 Cross-modulation test set-up. Rev. 02 - 13 November 2007 11 of 15 NXP Semiconductors Product specification Dual-gate MOS-FETs Table 1 f (MHz) BF1100; BF1100R Scattering parameters: VDS = 9 V; VG2-S = 4 V; ID = 10 mA s11 s21 s12 s22 MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) 50 0.986 −3.6 2.528 174.4 0.001 63.7 1.000 −2.0 100 0.983 −7.4 2.531 169.8 0.001 80.7 1.000 −4.2 200 0.974 −14.7 2.490 159.5 0.002 81.0 0.996 −8.1 300 0.960 −21.8 2.446 149.8 0.002 80.3 0.994 −11.9 400 0.953 −28.7 2.412 139.8 0.003 76.3 0.992 −15.7 500 0.933 −35.4 2.341 130.1 0.003 76.5 0.987 −19.4 600 0.915 −42.0 2.283 120.4 0.004 79.0 0.984 −23.0 700 0.895 −47.9 2.205 111.6 0.003 81.5 0.981 −26.7 800 0.880 −53.5 2.146 102.9 0.003 90.8 0.978 −30.3 900 0.864 −59.6 2.087 93.4 0.003 106.6 0.974 −33.9 1000 0.839 −65.0 1.998 84.4 0.003 135.4 0.971 −37.6 Table 2 Table 3 f (MHz) Noise data: VDS = 9 V; VG2-S = 4 V; ID = 10 mA Γopt f (MHz) Fmin (dB) (ratio) (deg) 800 2.00 0.67 43.9 rn 0.89 Scattering parameters: VDS = 12 V; VG2-S = 4 V; ID = 10 mA s21 s11 s12 s22 MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) MAGNITUDE (ratio) ANGLE (deg) 50 0.986 −3.7 2.478 174.7 0.001 72.2 1.000 −1.6 100 0.984 −7.4 2.480 170.3 0.001 80.9 1.000 −3.5 200 0.974 −14.6 2.440 160.6 0.002 82.7 0.997 −6.6 300 0.960 −21.8 2.400 151.4 0.002 79.9 0.996 −9.7 400 0.953 −28.7 2.371 141.9 0.003 77.7 0.994 −12.8 500 0.933 −35.3 2.306 132.7 0.003 77.1 0.991 −15.8 600 0.915 −41.9 2.255 123.6 0.004 77.1 0.989 −18.7 700 0.894 −47.8 2.183 115.3 0.004 79.3 0.986 −21.7 800 0.879 −53.5 2.131 107.2 0.003 83.9 0.984 −24.6 900 0.863 −59.5 2.080 98.2 0.003 95.1 0.982 −27.5 1000 0.838 −65.0 1.999 89.7 0.003 115.8 0.980 −30.4 Table 4 Noise data: VDS = 12 V; VG2-S = 4 V; ID = 10 mA Γopt f (MHz) Fmin (dB) (ratio) (deg) 800 2.00 0.66 43.3 Rev. 02 - 13 November 2007 rn 0.97 12 of 15 NXP Semiconductors Product specification Dual-gate MOS-FETs BF1100; BF1100R PACKAGE OUTLINES handbook, full pagewidth 0.75 0.60 3.0 2.8 0.150 0.090 B 1.9 4 3 0.1 max o 10 max 0.2 M A B A 2.5 max 1.4 1.2 o 10 max 2 1 1.1 max o 30 max 0.88 0 0.1 0.48 0 0.1 0.1 M A B MBC845 1.7 TOP VIEW Dimensions in mm. Fig.28 SOT143. 3.0 2.8 handbook, full pagewidth 0.150 0.090 0.40 0.25 B 1.9 3 4 0.1 max o 10 max 0.2 M A A 1.4 1.2 o 2.5 max 10 max 2 1.1 max o 30 max 1 0.48 0.38 0.88 0.78 MBC844 1.7 0.1 M B TOP VIEW Dimensions in mm. Fig.29 SOT143R. Rev. 02 - 13 November 2007 13 of 15 BF1100; BF1100R NXP Semiconductors Dual-gate MOS-FETs Legal information Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. 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Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: [email protected] Rev. 02 - 13 November 2007 14 of 15 BF1100; BF1100R NXP Semiconductors Dual-gate MOS-FETs Revision history Revision history Document ID Release date Data sheet status Change notice Supersedes BF1100_N_2 20071113 Product data sheet - BF1100_1 Modifications: BF1100_1 • Fig. 1 and 2 on page 2; Figure note changed 19950425 Product specification - - Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 13 November 2007 Document identifier: BF1100_N_2