CY7C199D 256 K (32 K × 8) Static RAM 256 K (32 K × 8) Static RAM Features Functional Description ■ Temperature ranges ❐ –40 °C to 85 °C ■ Pin and function compatible with CY7C199C ■ High speed ❐ tAA ■ = 10 ns Low active power ❐ ICC ■ The CY7C199D is a high performance CMOS static RAM organized as 32,768 words by 8-bits. Easy memory expansion is provided by an active LOW chip enable (CE), an active LOW output enable (OE) and tri-state drivers. This device has an automatic power-down feature, reducing the power consumption when deselected. The input and output pins (I/O0 through I/O7) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW and WE LOW). = 80 mA at 10 ns Low CMOS standby power ❐ ISB2 Write to the device by taking chip enable (CE) and write enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A14). = 3 mA ■ 2.0 V data retention ■ Automatic power-down when deselected ■ Complementary metal oxide semiconductor (CMOS) for optimum speed/power ■ Transistor-transistor logic (TTL) compatible inputs and outputs ■ Easy memory expansion with CE and OE features ■ Available in Pb-free 28-pin 300-Mil-wide molded small outline J-lead package (SOJ) and 28-pin thin small outline package (TSOP) I packages Read from the device by taking chip enable (CE) and output enable (OE) LOW while forcing write enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appears on the I/O pins. Logic Block Diagram I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 Cypress Semiconductor Corporation Document Number: 38-05471 Rev. *I • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised June 2, 2011 [+] Feedback CY7C199D Contents Pin Configuration ............................................................. 3 Selection Guide ................................................................ 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 AC Test Loads and Waveforms ....................................... 5 Switching Characteristics ................................................ 6 Data Retention Characteristics ....................................... 7 Data Retention Waveform ................................................ 7 Switching Waveforms ...................................................... 7 Truth Table ........................................................................ 9 Document Number: 38-05471 Rev. *I Ordering Information ........................................................ 9 Ordering Code Definitions ........................................... 9 Package Diagrams .......................................................... 10 Acronyms ........................................................................ 12 Document Conventions ................................................. 12 Units of Measure ....................................................... 12 Document History Page ................................................. 13 Sales, Solutions, and Legal Information ...................... 14 Worldwide Sales and Design Support ....................... 14 Products .................................................................... 14 PSoC Solutions ......................................................... 14 Page 2 of 14 [+] Feedback CY7C199D Pin Configuration Figure 1. 28-pin SOJ (Top View) A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A4 A3 A2 A1 OE A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 Figure 2. 28-pin TSOP I (Top View) OE A1 A2 A3 A4 WE VCC A5 A6 A7 A8 A9 A10 A11 22 23 24 25 26 27 28 1 2 3 4 5 6 7 TSOP I Top View (not to scale) 21 20 19 18 17 16 15 14 13 12 11 10 9 8 A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A14 A13 A12 Selection Guide -10 (Industrial) Unit Maximum access time Description 10 ns Maximum operating current 80 mA Maximum CMOS standby current 3 mA Document Number: 38-05471 Rev. *I Page 3 of 14 [+] Feedback CY7C199D DC input voltage [1] ............................. –0.5 V to VCC + 0.5 V Maximum Ratings Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage temperature ................................ –65 C to +150 C Output current into outputs (LOW) ............................. 20 mA Static discharge voltage ........................................ > 2,001 V (per MIL-STD-883, method 3015) Latch-up current ................................................... > 140 mA Ambient temperature with power applied .......................................... –55 C to +125 C Operating Range Supply voltage on VCC to relative GND [1] ................................–0.5 V to +6.0 V Range DC voltage applied to outputs in high Z State [1] ................................ –0.5 V to VCC + 0.5 V Industrial Ambient Temperature VCC Speed –40 C to +85 C 5 V 0.5 V 10 ns Electrical Characteristics Over the operating range Parameter Description CY7C199D-10 Test Conditions Unit Min Max 2.4 – V – 0.4 V 2.2 VCC + 0.5 V –0.5 0.8 V VOH Output HIGH voltage IOH = –4.0 mA VOL Output LOW voltage IOL = 8.0 mA VIH Input HIGH voltage [1] VIL Input LOW voltage [1] IIX Input leakage current GND < VI < VCC –1 +1 µA IOZ Output leakage current GND < VO < VCC, output disabled –1 +1 µA ICC VCC operating supply current VCC = VCC(max), IOUT = 0 mA, f = fmax = 1/tRC 100 MHz – 80 mA 83 MHz – 72 mA 66 MHz – 58 mA 40 MHz – 37 mA ISB1 Automatic CE power-down current— TTL Inputs VCC = VCC(max), CE > VIH, VIN > VIH or VIN < VIL, f = fmax – 10 mA ISB2 Automatic CE power-down current— CMOS Inputs VCC = VCC(max), CE > VCC – 0.3 V, VIN > VCC – 0.3 V or VIN < 0.3 V, f = 0 – 3 mA Note 1. VIL(min) = –2.0 V and VIH(max) = VCC + 1 V for pulse durations of less than 5 ns. Document Number: 38-05471 Rev. *I Page 4 of 14 [+] Feedback CY7C199D Capacitance Parameter [2] Description CIN Input capacitance COUT Output capacitance Test Conditions Max TA = 25 C, f = 1 MHz, VCC = 5.0 V Unit 8 pF 8 pF Thermal Resistance Parameter [2] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) Test Conditions 28-pin SOJ Still air, soldered on a 3 × 4.5 inch, four-layer printed circuit board 28-pin TSOP I Unit 59.16 54.65 C/W 40.84 21.49 C/W AC Test Loads and Waveforms Figure 3. AC Test Loads and Waveforms [3] Z = 50 ALL INPUT PULSES OUTPUT 3.0 V 50 * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT 30pF* GND 10% 90% 10% 90% 1.5 V Rise Time: 3 ns (a) High Z characteristics: (b) Fall Time: 3 ns R1 480 5V OUTPUT R2 255 5 pF INCLUDING JIG AND SCOPE (c) Notes 2. Tested initially and after any design or process changes that may affect these parameters. 3. AC characteristics (except high Z) are tested using the load conditions shown in Figure 3 (a). High Z characteristics are tested for all speeds using the test load shown in Figure 3 (c). Document Number: 38-05471 Rev. *I Page 5 of 14 [+] Feedback CY7C199D Switching Characteristics Over the operating range Parameter [4] Description CY7C199D-10 Min Max Unit Read Cycle tpower [5] VCC(typical) to the first access 100 – s tRC Read cycle time 10 – ns tAA Address to data valid – 10 ns tOHA Data hold from address change 3 – ns tACE CE LOW to data valid – 10 ns OE LOW to data valid – 5 ns OE LOW to low Z 0 – ns tDOE [6] tLZOE tHZOE [6, 7] OE HIGH to high Z – 5 ns tLZCE [6] CE LOW to low Z 3 – ns tHZCE [6, 7] CE HIGH to high Z – 5 ns CE LOW to power-up 0 – ns CE HIGH to power-down – 10 ns tPU [8] tPD [8] Write Cycle [9, 10] tWC Write cycle time 10 – ns tSCE CE LOW to write end 7 – ns tAW Address setup to write end 7 – ns tHA Address hold from write end 0 – ns tSA Address setup to write start 0 – ns tPWE WE pulse width 7 – ns tSD Data setup to write end 6 – ns Data hold from write end 0 – ns tHZWE [6] WE LOW to high Z – 5 ns tLZWE [6, 7] WE HIGH to low Z 3 – ns tHD Notes 4. Test conditions assume signal transition time of 3 ns or less for all speeds, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 5. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of Figure 3 on page 5. Transition is measured 200 mV from steady-state voltage. 8. This parameter is guaranteed by design and is not tested. 9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write. 10. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document Number: 38-05471 Rev. *I Page 6 of 14 [+] Feedback CY7C199D Data Retention Characteristics Over the operating range Parameter Description Conditions Min Max Unit 2.0 – V – 3 mA VDR VCC for data retention ICCDR Data retention current tCDR [11] Chip deselect to data retention time 0 – ns Operation recovery time 15 – ns tR [12] VCC = VDR = 2.0 V, CE > VCC – 0.3 V, VIN > VCC – 0.3 V or VIN < 0.3 V Data Retention Waveform DATA RETENTION MODE VCC 4.5 V 4.5 V VDR > 2 V tR tCDR CE Switching Waveforms Figure 4. Read Cycle No. 1: Address Transition Controlled [13, 14] tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Figure 5. Read Cycle No. 2 OE Controlled [14, 15] tRC CE tACE OE tHZOE tHZCE tDOE DATA OUT tLZOE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT HIGH IMPEDANCE tPD tPU ICC 50% 50% ISB Notes 11. Tested initially and after any design or process changes that may affect these parameters. 12. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 µs or stable at VCC(min) > 50 µs. 13. Device is continuously selected. OE, CE = VIL. 14. WE is HIGH for read cycle. 15. Address valid prior to or coincident with CE transition LOW. Document Number: 38-05471 Rev. *I Page 7 of 14 [+] Feedback CY7C199D Switching Waveforms (continued) Figure 6. Write Cycle No. 1: CE Controlled [16, 17, 18] tWC ADDRESS tSCE CE tSA tAW tHA WE tSD DATA I/O tHD DATA IN VALID Figure 7. Write Cycle No. 3 WE Controlled, OE LOW [18, 19] tWC ADDRESS CE tAW tHA tSA WE tSD DATA IO NOTE 20 tHD DATAIN VALID tHZWE tLZWE Notes 16. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write. 17. Data I/O is high impedance if OE = VIH. 18. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 19. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 20. During this period the I/Os are in the output state and input signals should not be applied. Document Number: 38-05471 Rev. *I Page 8 of 14 [+] Feedback CY7C199D Truth Table CE WE OE Inputs/Outputs Mode Power H X X High Z Deselect/power-down Standby (ISB) L H L Data out Read Active (ICC) L L X Data in Write Active (ICC) L H H High Z Deselect, output disabled Active (ICC) Ordering Information Cypress offers other versions of this type of product in many different configurations and features. The following table contains only the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at http://www.cypress.com and refer to the product summary page at http://www.cypress.com/products or contact your local sales representative. Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office closest to you, visit us at http://www.cypress.com/go/datasheet/offices. Speed (ns) Ordering Code 10 Package Diagram Package Type CY7C199D-10VXI 51-85031 28-pin (300-Mil) Molded SOJ (Pb-free) CY7C199D-10ZXI 51-85071 28-pin TSOP Type I (Pb-free) Operating Range Industrial Please contact your local Cypress sales representative for availability of these parts. Ordering Code Definitions CY 7 C 1 9 9 D - XX X X I Temperature Grade: I I = Industrial Pb-free Package Type: V or Z V = 28 pin (300-Mil) Molded SOJ Z = 28 pin TSOP Type 1 Speed Grade: 10 ns Process Technology: 90 nm Bus Width = × 8 Density = 256 K Fast SRAM Family Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 38-05471 Rev. *I Page 9 of 14 [+] Feedback CY7C199D Package Diagrams Figure 8. 28-pin SOJ 300-Mils V28.3 (Molded SOJ V21) 51-85031 *D Document Number: 38-05471 Rev. *I Page 10 of 14 [+] Feedback CY7C199D Package Diagrams (continued) Figure 9. 28-pin TSOP Type 1 (8 × 13.4 × 1.2 mm) Z28 (Standard) 51-85071 *I Document Number: 38-05471 Rev. *I Page 11 of 14 [+] Feedback CY7C199D Acronyms Acronym Document Conventions Description Units of Measure CE chip enable CMOS complementary metal oxide semiconductor °C degree Celsius I/O input/output µA micro Amperes OE output enable µs micro seconds SOJ small outline J-lead mA milli Amperes SRAM static random access memory mm milli meter TSOP thin small outline package ns nano seconds TTL transistor-transistor logic pF pico Farad WE write enable V Volts W Watts Document Number: 38-05471 Rev. *I Symbol Unit of Measure Page 12 of 14 [+] Feedback CY7C199D Document History Page Document Title: CY7C199D, 256 K (32 K × 8) Static RAM Document Number: 38-05471 Revision ECN Orig. of Change Submission Date Description of Change ** 201560 SWI See ECN Advance Information datasheet for C9 IPP *A 233728 RKF See ECN DC parameters modified as per EROS (Spec # 01-02165) Pb-free Offering in Ordering Information *B 262950 RKF See ECN Removed 28-LCC Pinout and Package Diagrams Added Data Retention Characteristics table Added Tpower Spec in Switching Characteristics table Shaded Ordering Information *C 307594 RKF See ECN Reduced Speed bins to -10, -12 and -15 ns *D 820660 VKN See ECN Converted from Preliminary to Final Removed 12 ns and 15 ns speed bin Removed Commercial Operating range Removed “L” part Removed 28-pin PDIP and 28-pin SOIC package Changed Overshoot spec from VCC+2V to VCC+1V in footnote #2 Changed ICC spec from 60 mA to 80 mA for 100 MHz speed bin Added ICC specs for 83 MHz, 66 MHz and 40 MHz speed bins Updated Thermal Resistance table Updated Ordering Information Table *E 2745093 VKN See ECN Included 28-Pin SOIC package Changed VIH level from 2.0V to 2.2V For Industrial grade, changed tSD from 5 ns to 6 ns, and tHZWE from 6 ns to 5 ns Included Automotive-E information *F 2897087 AJU 03/22/10 Removed obsolete parts from ordering information table Updated package diagrams *G 3023234 RAME 09/06/2010 *H 3130763 PRAS 01/07/11 *I 3271782 PRAS 06/02/2011 Document Number: 38-05471 Rev. *I Added Auto-E SOIC package related info Changed TDOE spec from 10 ns to 11 ns in CY7C199D-25. Added Ordering Code Definitions. Added Acronyms and Document Conventions. Dislodged Automotive information to a new datasheet (001-65530) Updated Functional Description (Removed “For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.”). Updated Package Diagrams. Updated in new template. Page 13 of 14 [+] Feedback CY7C199D Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive Clocks & Buffers cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory cypress.com/go/memory Optical & Image Sensing cypress.com/go/image PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/touch USB Controllers Wireless/RF cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2004-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-05471 Rev. *I Revised June 2, 2011 Page 14 of 14 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback