CY2410 MPEG Clock Generator with VCXO MPEG Clock Generator with VCXO Features Benefits ■ Integrated phase-locked loop (PLL) ■ Highest-performance PLL tailored for multimedia applications ■ Low-jitter, high-accuracy outputs ■ Meets critical timing requirements in complex system designs ■ VCXO with analog adjust ■ Large ±150-ppm range, better linearity ■ 3.3 V operation ■ Application compatibility for a wide variety of designs ■ Compatible with MK3727 (–1, –5) ■ Enables design compatibility ■ Advanced Features ■ Matches nonlinear MK3727A VCXO control curve (-5) ■ Digital VCXO control ■ Electromagnetic interference (EMI) reduction for standards compliance ■ Second source for existing designs Part Number Outputs Output Frequencies Input Frequency Range VCXO Control Curve Other Features CY2410-1 1 13.5-MHz pullable crystal input per Cypress specification 1 copy of 27 MHz linear Compatible with MK3727 CY2410-5 1 13.5-MHz pullable crystal input per Cypress specification 1 copy of 27 MHz nonlinear Matches MK3727A nonlinear VCXO Control Curve CY2410-1, -5 Logic Block Diagram 13.5 XIN XOUT OSC Q OUTPUT DIVIDERS VCO 27 MHz P VCXO PLL VDD Cypress Semiconductor Corporation Document #: 38-07317 Rev. *G • 198 Champion Court VSS • San Jose, CA 95134-1709 • 408-943-2600 Revised July 16, 2011 [+] Feedback CY2410 CY2410-3 Logic Block Diagram 13.5 XIN OSC Q OUTPUT DIVIDERS XOUT VCO 27 MHz P PLL SCLK SDAT Digital VCXO Serial Programming Interface Document #: 38-07317 Rev. *G VDD VSS Page 2 of 13 [+] Feedback CY2410 Contents Pin Configuration ............................................................. 4 Pin Definitions for CY2410-1, CY2410-5 ......................... 4 Pullable Crystal Specifications ....................................... 5 Absolute Maximum Conditions ....................................... 7 Recommended Operating Conditions ............................ 7 DC Electrical Specifications ............................................ 7 AC Electrical Specifications (VDD = 3.3 V) ..................... 7 Ordering Information ........................................................ 9 Ordering Code Definitions ........................................... 9 Document #: 38-07317 Rev. *G Package Diagram ............................................................ 10 Acronyms ........................................................................ 11 Document Conventions ................................................. 11 Units of Measure ....................................................... 11 Document History Page ................................................. 12 Sales, Solutions, and Legal Information ...................... 13 Worldwide Sales and Design Support ....................... 13 Products .................................................................... 13 PSoC Solutions ......................................................... 13 Page 3 of 13 [+] Feedback CY2410 Pin Configuration Figure 1. CY2410-1, CY2410-5 8-pin SOIC XIN 1 8 XOUT VDD VCXO 2 7 NC or VSS 3 6 NC or VDD VSS 4 5 27 MHz Pin Definitions for CY2410-1, CY2410-5 Name Pin Number Description XIN 1 VDD 2 Voltage supply VCXO 3 Input analog control for VCXO Reference crystal input VSS 4 Ground 27 MHz 5 27-MHz clock output NC/VDD 6 No Connect or voltage supply NC/VSS 7 No Connect or ground XOUT[1] 8 Reference crystal output Note 1. Float XOUT if XIN is externally driven. Document #: 38-07317 Rev. *G Page 4 of 13 [+] Feedback CY2410 Pullable Crystal Specifications Parameter [2] Description Min Typ Max Unit – 13.5 – MHz – 14 – pF – – 25 Ratio of third overtone mode ESR Ratio used because typical R1 values to fundamental mode ESR are much less than the maximum spec. 3 – – DL Crystal drive level No external series resistor assumed – 0.5 2.0 mW F3SEPHI Third overtone separation from 3 × FNOM High side 300 – – ppm F3SEPLO Third overtone separation from 3 × FNOM Low side – – –150 ppm C0 Crystal shunt capacitance – – 7 pF C0/C1 Ratio of shunt to motional capacitance 180 – 250 C1 Crystal motional capacitance 14.4 18 21.6 FNOM Nominal crystal frequency CLNOM Nominal load capacitance R1 Equivalent series resistance (ESR) R3/R1 Condition Parallel resonance, fundamental mode, AT cut Fundamental mode pF Note 2. Crystals that meet this specification includes: Ecliptek ECX-5788-13.500M, Siward XTL001050A-13.5-14-400, Raltron A-13.500-14-CL, PDI HA13500XFSA14XC. Document #: 38-07317 Rev. *G Page 5 of 13 [+] Feedback CY2410 Figure 2. Data Valid and Data Transition Periods Data Valid Transition to next bit SDAT tDH SCLK tSU CLKHIGH VIH CLKLOW VIL Figure 3. Start and Stop Frame SDAT SCLK Transition to next bit START STOP Figure 4. Duty Cycle Definition; DC = t2/t1 t1 t2 CLK 50% 50% Figure 5. Rise and Fall Time Definitions: ER = 0.6 × VDD / t3, EF = 0.6 × VDD / t4 t4 t3 80% CLK Document #: 38-07317 Rev. *G 20% Page 6 of 13 [+] Feedback CY2410 Absolute Maximum Conditions Parameter VDD Description Supply Voltage TS Storage Temperature TJ Junction Temperature [3] Min Max Unit –0.5 7.0 V –65 125 °C – 125 °C Digital Inputs VSS – 0.3 VDD + 0.3 V Digital Outputs referred to VDD VSS – 0.3 VDD + 0.3 V 2000 – V Min Typ Max Unit Electrostatic Discharge Recommended Operating Conditions Parameter Description VDD Operating Voltage 3.135 3.3 3.465 V TA Ambient Temperature 0 – 70 °C CLOAD Max. Load Capacitance – – 15 pF fREF Reference Frequency – 13.5 – MHz tPU Power up time for VDD to reach minimum specified voltage (power ramp must be monotonic) 0.05 – 500 ms DC Electrical Specifications Min Typ Max Unit IOH Parameter Output HIGH Current: -1, -5 Name VOH = VDD – 0.5, VDD = 3.3 V Description 12 24 – mA IOL Output LOW Current: -1, -5 VOL = 0.5, VDD = 3.3 V 12 24 – mA CIN Input Capacitance – – 7 pF IIZ Input Leakage Current – 5 – A fXO VCXO pullability range: -1, -5 +150 – – ppm VVCXO VCXO input range 0 – VDD V IVDD Supply Current – 30 35 mA AC Electrical Specifications (VDD = 3.3 V) Parameter[4] Description Min Typ Max Unit DC Output Duty Cycle Name Duty Cycle is defined in Figure 4 on page 6, 50% of VDD 45 50 55 % EROR Rising Edge Rate: -1, -5 Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF. See Figure 5 on page 6. 0.8 1.4 – V/ns EROF Falling Edge Rate: -1, -5 Output Clock Edge Rate, Measured from 80% to 20% of VDD, CLOAD = 15 pF. See Figure 5 on page 6. 0.8 1.4 – V/ns t9 Clock Jitter: -1, -5 Peak-to-peak period jitter – 140 – ps t10 PLL Lock Time – – 3 ms Notes 3. Rated for ten years. 4. Not 100% tested. Document #: 38-07317 Rev. *G Page 7 of 13 [+] Feedback CY2410 Figure 6. Test and Measurement Setup VDD CLK out 0.1 F OUTPUTS CLOAD GND Document #: 38-07317 Rev. *G Page 8 of 13 [+] Feedback CY2410 Ordering Information Ordering Code Package Type Operating Range Operating Voltage Features Pb-free CY2410KSXC–5 8-pin SOIC Commercial 3.3 V Matches nonlinear MK3727A VCXO control curve CY2410KSXC–5T 8-pin SOIC - Tape and Reel Commercial 3.3 V Matches nonlinear MK3727A VCXO control curve Ordering Code Definitions CY2410K S X C - 5 T Tape and Reel Configuration Type Temperature Range: C = Commercial Pb-free Package Type: S = 8-pin SOIC Base Part Number Document #: 38-07317 Rev. *G Page 9 of 13 [+] Feedback CY2410 Package Diagram Figure 7. 8-pin SOIC (150 Mils), 51-85066 51-85066 *E Document #: 38-07317 Rev. *G Page 10 of 13 [+] Feedback CY2410 Acronyms Acronym Document Conventions Description Units of Measure PLL phase-locked loop EMI electromagnetic interference C degree Celsius ESD electrostatic discharge MHz Mega Hertz ESR equivalent series resistance F micro Farad PLL phase locked loop mA milli Amperes SOIC small outline integrated circuit ms milli seconds VCXO voltage controlled crystal oscillator mW milli Watts ohms Document #: 38-07317 Rev. *G Symbol Unit of Measure ppm parts per million % percent pF pico Farad ps pico seconds V Volts Page 11 of 13 [+] Feedback CY2410 Document History Page Document Title: CY2410, MPEG Clock Generator with VCXO Document Number: 38-07317 REV. ECN NO. Submission Date Orig. of Change ** 111553 02/12/02 CKN Description of Change New Data Sheet *A 114937 09/24/02 CKN Added -6 to data sheet, Advance Information to Final *B 121418 12/06/02 CKN Updated the Pullable Crystal Specifications table on page 2 *C 126905 06/17/03 RGL Added -7 part to data sheet Added new parameter on the Pullable Crystal table Power up requirements added to the operating conditions *D 131100 01/20/03 RGL Added VCXO -7 pullability range in the DC Specs with min. value of ±115 ppm *E 2440886 See ECN AESA Updated template. Added Note “Not recommended for new designs.” Added part number CY2410SXC-1, CY2410SXC-1T, CY2410SXC-5, CY2410SXC-5T, CY2410KSXC-5, and CY2410KSXC-5T in ordering information table. Removed all part numbers for non-Pb-free packages (part numbers beginning CY2410SC). Removed details specific to the -3, -4, -6 and -7 versions. *F 2897373 03/22/10 CXQ Updated ordering information table. Removed part numbers CY2410SXC-1, CY2410SXC-1T, CY2410SXC-5T, and CY2410SXC-5 Updated package diagram. Updated copyright section. *G 3317009 07/16/2011 BASH Added Ordering Code Definitions. Updated Package Diagram. Updated Acronyms and Units of Measure. Updated in new template. Document #: 38-07317 Rev. *G Page 12 of 13 [+] Feedback CY2410 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2009-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-07317 Rev. *G Revised July 16, 2011 Page 13 of 13 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback