CY2410 MPEG Clock Generator with VCXO Features • Application compatibility for a wide variety of designs • Enables design compatibility • Integrated phase-locked loop (PLL) • Advanced Features • Low-jitter, high-accuracy outputs • Serial programming interface (CY2410-3 only) • VCXO with analog adjust • Lower drive strength settings (CY2410-4, -6) • 3.3V operation • Matches nonlinear MK3727A VCXO control curve (-5, -6) • Compatible with MK3727 (–1, –4, –5, –6, –7) • Matches nonlinear MK3727C VCXO control curve (-7) Benefits Benefits • Highest-performance PLL tailored for multimedia applications • Digital VCXO control • Meets critical timing requirements in complex system designs • Electromagnetic interference (EMI) reduction for standards compliance • Large ±150-ppm range, better linearity • Second source for existing designs Part Number Outputs Output Frequencies CY2410–1 1 13.5-MHz pullable crystal input per 1 copy of 27 MHz linear Cypress specification Compatible with MK3727 CY2410–3 1 13.5-MHz pullable crystal input per 1 copy of 27 MHz linear Cypress specification Serial programming interface CY2410–4 1 13.5-MHz pullable crystal input per 1 copy of 27 MHz linear Cypress specification Same as CY2410–1 except lower drive strength settings CY2410–5 1 13.5-MHz pullable crystal input per 1 copy of 27 MHz nonlinear Cypress specification Matches MK3727A nonlinear VCXO Control Curve CY2410–6 1 13.5-MHz pullable crystal input per 1 copy of 27 MHz nonlinear Cypress specification Same as CY2410–5 except lower drive strength CY2410–7 1 13.5-MHz pullable crystal input per 1 copy of 27 MHz nonlinear Cypress specification Matches MK3727C nonlinear VCXO control curve Input Frequency Range CY2410–1,–4,–5,–6,–7 Logic Block Diagram VCXO Control Curve CY2410–3 Logic Block Diagram 13.5 XIN OSC Q XOUT OSC Q OUTPUT DIVIDERS Φ VCO VCO 27 MHz 27 MHz P PLL P VCXO OUTPUT DIVIDERS Φ XOUT 13.5 XIN Other Features PLL SCLK VDD VSS SDAT Digital VCXO Serial Programming Interface VDD VSS Pin Configurations CY2410–3 CY2410–1,–4,–5,–6,–7 8-pin SOIC XIN 1 8 XOUT VDD VCXO 2 7 NC or VSS 3 6 NC or VDD VSS 4 5 27 MHz Cypress Semiconductor Corporation Document #: 38-07317 Rev. *D • 3901 North First Street 8-pin SOIC XIN 1 8 XOUT VDD SDAT 2 7 3 6 NC or VSS 27 MHz VSS 4 5 SCLK • San Jose, CA 95134 • 408-943-2600 Revised December 11, 2003 CY2410 Pin Descriptions for CY2410–1, –4, –5, –6, –7 Name Pin Number Description XIN 1 Reference crystal input VDD 2 Voltage supply VCXO 3 Input analog control for VCXO VSS 4 Ground 27 MHz 5 27-MHz clock output NC/VDD 6 No Connect or voltage supply NC/VSS 7 No Connect or ground XOUT[1] 8 Reference crystal output Pin Description for CY2410–3 Name Pin Number Description XIN 1 Reference crystal input VDD 2 Voltage supply SDAT 3 Serial data input for DCXO control VSS 4 Ground SCLK 5 Serial clock input for DCXO control 27 MHz 6 27-MHz clock output NC/VSS 7 No Connect or ground [1] 8 Reference crystal output XOUT Pullable Crystal Specifications[2] Parameter Description Condition Parallel resonance, fundamental mode, AT cut Min. Typ. Max. Unit – 13.5 – MHz – 14 – pF – – 25 Ω 3 – – 0.5 2.0 mW – – ppm – –150 ppm pF FNOM Nominal crystal frequency CLNOM Nominal load capacitance R1 Equivalent series resistance (ESR) R3/R1 Ratio of third overtone mode ESR to fundamen- Ratio used because typical tal mode ESR R1 values are much less than the maximum spec. DL Crystal drive level No external series resistor assumed – F3SEPHI Third overtone separation from 3*FNOM High side 300 F3SEPLO Third overtone separation from 3*FNOM Low side – Fundamental mode C0 Crystal shunt capacitance – – 7 C0/C1 Ratio of shunt to motional capacitance 180 – 250 C1 Crystal motional capacitance 14.4 18 21.6 pF Notes: 1. Float XOUT if XIN is externally driven. 2. Crystals that meet this specification includes: Ecliptek ECX-5788-13.500M,Siward XTL001050A-13.5-14-400, Raltron A-13.500-14-CL,PDI HA13500XFSA14XC. Document #: 38-07317 Rev. *D Page 2 of 7 CY2410 Serial Programmable Interface Protocol The CY2410-3 utilizes a two-wire-interface SDAT and SCLK that operates up to 400 kbits/sec in Read or Write mode. The basic Write serial format is as follows: start bit; 7-bit device address (DA); R/W bit; slave clock acknowledge (ACK); 8-bit memory address (MA); ACK; 8-bit data; ACK; 8-bit data in MA+1 if desired; ACK; 8-bit data in MA+2; ACK; etc. until stop bit, as illustrated in Figure 1. 1-bit 1-bit Slave R/W = 0 ACK SDA Write 7-bit Device Address 1-bit Slave ACK 1-bit Slave ACK 8-bit 8-bit Register Register Data Address Start Signal Data Valid SDAT tDH SCLK tSU CLKHIGH VIH CLKLOW VIL Stop Signal Transition to next bit Figure 2. Data Valid and Data Transition Periods Figure 1. Data Frame Architecture Data Valid Data is valid when the clock is HIGH, and may only be transitioned when the clock is low as illustrated in Figure 2. SDAT SCLK Data Frame Every new data frame is indicated by a start and stop sequence, as illustrated in Figure 3. Start Sequence A start frame is indicated by SDAT going LOW when SCLK is HIGH. Every time a start signal is given, the next 8-bit data must be the device address (7 bits) and a R/W bit (0 for Write), followed by register address (8 bits) and register data (8 bits). See Figure 3. Transition to next bit START Figure 3. Start and Stop Frame t1 t2 CLK 50% 50% Stop Sequence A stop frame is indicated by SDAT going HIGH when SCLK is HIGH. A stop frame frees the bus for writing to another part on the same bus or writing to another random register address. See Figure 3. Figure 4. Duty Cycle Definition; DC = t2/t1 Device Address t4 t3 Acknowledge Pulse During Write mode, the CY2410-3 will respond with an ACK pulse after every 8 bits. This is accomplished by pulling the SDAT line LOW during the next clock cycle after the eighth bit is shifted in. STOP 80% CLK 20% Figure 5. Rise and Fall Time Definitions: ER = 0.6 x VDD / t3, EF = 0.6 x VDD / t4 The 7-bit device address is 1101001. Register Address The 8-bit address for the VCXO register is 00010011. Register Data The register data can be any value between 00H–FFH. As you increase the value, the capacitance on the XIN and XOUT pins will increase, thereby decreasing the xtal frequency. Document #: 38-07317 Rev. *D Page 3 of 7 CY2410 Absolute Maximum Conditions Parameter Description Min. Max. Unit VDD Supply Voltage –0.5 7.0 V TS Storage Temperature[3] –65 125 °C TJ Junction Temperature – 125 °C Digital Inputs VSS – 0.3 VDD + 0.3 V Digital Outputs referred to VDD VSS – 0.3 VDD + 0.3 V Electrostatic Discharge 2000 V Recommended Operating Conditions Parameter Description Min. Typ. Max. Unit 3.135 3.3 3.465 V 0 – 70 °C VDD Operating Voltage TA Ambient Temperature CLOAD Max. Load Capacitance – – 15 pF fREF Reference Frequency – 13.5 – MHz tPU Power up time for VDD to reach minimum specified voltage (power ramp must be monotonic) 0.05 – 500 ms DC Electrical Specifications Parameter Name Description Min. Typ. Max. Unit IOH Output HIGH Current –1,3,5,7 VOH = VDD – 0.5, VDD = 3.3V 12 24 – mA IOL Output LOW Current –1,3,5,7 VOL = 0.5, VDD = 3.3V 12 24 – mA IOH Output HIGH Current –4,6 VOH = VDD – 0.5, VDD = 3.3V 6 18 – mA IOL Output LOW Current –4,6 VOL = 0.5, VDD = 3.3V 6 18 – mA CIN Input Capacitance – – 7 pF IIZ Input Leakage Current – 5 – µA f∆XO VCXO pullability range:–1,–3,–4,–5,–6 +150 – – ppm VCXO pullability range:–7 +115 – – ppm VVCXO VCXO input range 0 – VDD V IVDD Supply Current – 30 35 mA AC Electrical Specifications (VDD = 3.3V)[4] Parameter[4] Min. Typ. Max. Unit DC Output Duty Cycle Name Duty Cycle is defined in Figure 4, 50% of VDD Description 45 50 55 % EROR Rising Edge Rate –1, –3, –5, –7 Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF See Figure 5. 0.8 1.4 – V/ns EROF Falling Edge Rate –1, –3, –5, –7 Output Clock Edge Rate, Measured from 80% to 20% of VDD, CLOAD = 15 pF See Figure 5. 0.8 1.4 – V/ns EROR Rising Edge Rate –4, –6 Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF See Figure 5. 0.7 1.1 – V/ns EROF Falling Edge Rate –4, –6 Output Clock Edge Rate, Measured from 80% to 20% of VDD, CLOAD = 15 pF See Figure 5. 0.7 1.1 – V/ns t9 Clock Jitter –1, –3, –5, –7 Peak-to-peak period jitter – 140 – ps t9 Clock Jitter –4, –6 Peak-to-peak period jitter – 150 – ps t10 PLL Lock Time – – 3 ms Notes: 3. Rated for ten years. 4. Not 100% tested. Document #: 38-07317 Rev. *D Page 4 of 7 CY2410 Serial Programming Interface Timing Specifications Parameter fSCL Description Min. Frequency of SCLK Max. Unit 400 kHz Start mode time from SDAT LOW to SCLK LOW 0.6 µS CLKLOW SCLK LOW period 1.3 µS CLKHIGH SCLK HIGH period 0.6 µS tSU Data transition to SCLK HIGH 100 ns tDH Data hold (SCLK LOW to data transition) 0 ns Rise time of SCLK and SDAT 300 ns Fall time of SCLK and SDAT 300 ns Stop mode time from SCLK HIGH to SDA HIGH 0.6 µs Stop mode to start mode 1.3 µs Test and Measurement Set-up VDD CLK out 0.1 µF OUTPUTS CLOAD GND Ordering Information Ordering Code Package Type Operating Range Operating Voltage Features CY2410SC–1 8-pin SOIC Commercial 3.3V Linear VCXO control curve CY2410SC–1T 8-pin SOIC - Tape and Reel Commercial 3.3V Linear VCXO control curve CY2410SC–3 8-pin SOIC Commercial 3.3V Digital VCXO control CY2410SC–3T 8-pin SOIC - Tape and Reel Commercial 3.3V Digital VCXO control CY2410SC–4 8-pin SOIC Commercial 3.3V Lower drive strength (reduced EMI) CY2410SC–4T 8-pin SOIC - Tape and Reel Commercial 3.3V Lower drive strength (reduced EMI) CY2410SC–5 8-pin SOIC Commercial 3.3V Matches nonlinear MK3727A VCXO control curve CY2410SC–5T 8-pin SOIC - Tape and Reel Commercial 3.3V Matches nonlinear MK3727A VCXO control curve CY2410SC–6 8-pin SOIC Commercial 3.3V Lower drive strength version of CY2410–5 CY2410SC–6T 8-pin SOIC - Tape and Reel Commercial 3.3V Lower drive strength version of CY2410–5 CY2410SC–7 8-pin SOIC Commercial 3.3V Matches MK3727C nonlinear VCXO control curve CY2410SC–7T 8-pin SOIC - Tape and Reel Commercial 3.3V Matches MK3727C nonlinear VCXO control curve Document #: 38-07317 Rev. *D Page 5 of 7 CY2410 Package Drawing and Dimensions 8-lead (150-Mil) SOIC S8 8 Lead (150 Mil) SOIC - S08 PIN 1 ID 4 1 1. DIMENSIONS IN INCHES[MM] MIN. MAX. 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 0.150[3.810] 0.157[3.987] 3. REFERENCE JEDEC MS-012 0.230[5.842] 0.244[6.197] 4. PACKAGE WEIGHT 0.07gms PART # S08.15 STANDARD PKG. 5 SZ08.15 LEAD FREE PKG. 8 0.189[4.800] 0.196[4.978] 0.010[0.254] 0.016[0.406] SEATING PLANE X 45° 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.004[0.102] 0.0098[0.249] 0°~8° 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 51-85066-*C All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07317 Rev. *D Page 6 of 7 © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY2410 Document History Page Document Title: CY2410 MPEG Clock Generator with VCXO Document Number: 38-07317 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 111553 02/12/02 CKN New Data Sheet *A 114937 09/24/02 CKN Added -6 to data sheet, Advance Information to Final *B 121418 12/06/02 CKN Updated the Pullable Crystal Specifications table on page 2 *C 126905 06/17/03 RGL Added -7 part to data sheet Added new parameter on the Pullable Crystal table Power-up requirements added to the operating conditions *D 131100 01/20/03 RGL Added VCXO –7 pullability range in the DC Specs with min. value of ±115ppm Document #: 38-07317 Rev. *D Page 7 of 7