MAXIM MAX1816ETM

19-2569; Rev 0; 10/02
Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers
♦ +2V to +28V Battery Input Range
♦ Differential Remote Sense (BUCK1)
♦ Linear-Regulator Controller
♦ 200/300/550/1000kHz Switching Frequency
♦ 2.2mA (typ) ICC Supply Current
♦ 20µA (max) Shutdown Supply Current
♦ Independent Power-Good Outputs
(PGOOD, LINGOOD)
Ordering Information
PART
MAX1816ETM
MAX1994ETM
TEMP RANGE
-40°C to +100°C
-40°C to +100°C
Quick-PWM is a trademark of Maxim Integrated Products, Inc.
PIN-PACKAGE
48 Thin QFN
48 Thin QFN
BST2
V+
38
37
39
DL2
DH2
LX2
40
41
42
43
44
DH1
PERF
DL1
PGND
VDD
46
45
BST1
LX1
47
TOP VIEW
48
Pin Configuration
ILIM1
1
36
ILIM2
CC
CS1+
CS1-
2
35
CS2
3
34
4
33
OUT2
FB2
FBS
GDS
5
32
REF
6
31
VCC
AGND
LINBSE
MAX1816
MAX1994
30
9
28
10
27
SUS
11
26
DPSLP
12
25
24
23
22
LINGOOD
LINFB
TIME
OVPSET
LIN/SDN
PGOOD
TON
21
20
29
SKP1/SDN
SKP2/SDN
19
8
18
7
17
GAIN
OFS0
OFS1
OFS2
D0
Small Notebook Computers
♦ Voltage-Positioning Gain and Offset Control
16
3- to 4-Cell Li+ Battery to CPU Core Supply
♦ +0.70V to +2.00V Output Adjust Range (MAX1994)
15
Memory I/O and VID Supplies
♦ +0.60V to +1.75V Output Adjust Range (MAX1816)
14
Mobile CPU Core and Video Processors
♦ 5-Bit On-Board D/A Converter
13
Applications
♦ ±1% VOUT Accuracy
D1
D2
D3
D4
S0
S1
BUCK1, BUCK2, and the linear regulator feature overvoltage protection (OVP). The detection threshold for BUCK1
is adjusted with an external resistive voltage-divider, while
the OVP thresholds for BUCK2 and the linear regulator
are fixed. Connecting the OVPSET pin to VCC disables
OVP for BUCK1 and BUCK2, but not the linear regulator.
The MAX1816 features an output-voltage adjustment
range from 0.6V to 1.75V. Similarly, the MAX1994 is
adjustable from 0.925V to 2.0V, using an alternate VID
code set. While in suspend mode, the adjustment range
is 0.7V to 1.075V for both the MAX1816 and MAX1994.
Both parts are available in 48-pin thin QFN packages.
Features
♦ Dual Quick-PWM Architecture
THIN QFN 7mm × 7mm
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX1816/MAX1994
General Description
The MAX1816/MAX1994 are dual step-down controllers
for notebook computer applications. BUCK1 is a CPU
core regulator with dynamically adjustable output, ultrafast transient response, high DC accuracy, and high efficiency. BUCK2 is an adjustable step-down regulator for
I/O and memory supplies. Both regulators employ Maxim’s
proprietary Quick-PWM™ control architecture. This fastresponse, constant-on-time PWM control scheme handles
wide input/output voltage ratios with ease and provides
100ns “instant” on-response to load transients, while maintaining a relatively constant switching frequency. The
MAX1816/MAX1994 also have a linear-regulator controller
for low-voltage auxiliary power supplies.
The CPU regulator supports “active voltage positioning”
to reduce output bulk capacitance and lower power dissipation. A programmable gain amplifier allows the use
of lower value sense resistors. Four fixed-gain settings
are available (0, 1.5, 2, and 4). A differential remotesense amplifier is also included to more accurately control the voltage at the load. Accuracy is further
enhanced with an internal integrator.
The MAX1816/MAX1994 include a specialized digital
interface that makes them suitable for mobile CPU and
video processor applications. The power-good
(PGOOD) output for the core regulator is forced high
during VID transitions, and the LINGOOD output for the
linear regulator includes a 1ms (min) turn-on delay.
MAX1816/MAX1994
Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers
ABSOLUTE MAXIMUM RATINGS
V+ to AGND............................................................-0.3V to +30V
VCC, VDD to AGND...................................................-0.3V to +6V
PGND, GDS to AGND .........................................................±0.3V
SKP1/SDN, SKP2/SDN, LIN/SDN to AGND............-0.3V to +16V
LINBSE, SUS, PERF, DPSLP, PGOOD,
LINGOOD, CS1+, CS1-, FBS, D0–D4,
OUT2 to AGND.....................................................-0.3V to +6V
OFS0, OFS1, OFS2, ILIM1, ILIM2,
FB2, REF, TON, TIME, OVPSET, S0, S1,
GAIN, CC, LINFB to AGND ....................-0.3V to (VCC + 0.3V)
DL1, DL2 to PGND .....................................-0.3V to (VDD + 0.3V)
DH1 to LX1 ..............................................-0.3V to (VBST1 + 0.3V)
DH2 to LX2 ..............................................-0.3V to (VBST2 + 0.3V)
BST1 to LX1..............................................................-0.3V to +6V
BST2 to LX2..............................................................-0.3V to +6V
LX1, LX2, CS2 to AGND ............................................-2V to +30V
REF Short Circuit to AGND.........................................Continuous
LINBSE Short Circuit to +6V.......................................Continuous
Continuous Power Dissipation (TA = +70°C)
48-Pin Thin QFN (derate 26.3mW/°C above +70°C) .2105mW
Operating Temperature Range .........................-40°C to +100°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, V+ = 15V, VOUT1 = 1.20V, VOUT2 = 2.50V, VCC = VDD = 5.0V, VSKP1/SDN = VSKP2/SDN = VLIN/SDN = 5.0V,
TA = 0°C to +85°C. Typical values are at TA = +25°C, unless otherwise noted.)
PARAMETER
Input Voltage Range
CONDITIONS
Battery voltage V+
TON = REF, open, or VCC
TON = GND
VCC, VDD
BUCK1 DC Output Voltage
Accuracy
BUCK2 Error Comparator Threshold
(DC Output Voltage Accuracy)
(Note 1)
V+ = 4.5V to 28V,
includes load
regulation errors,
OFS_ = GDS = AGND,
CS1+ = CS1- = FBS
V+ = 4.5V to 28V
MIN
UNITS
28
2
16
4.5
5.5
-1
+1
V
%
DAC codes from 0.700V to
2.000V (MAX1994)
FB2 = GND
2.475
2.500
2.525
FB2 = VCC
1.782
1.800
1.818
FB2 = OUT2
0.990
1.000
1.010
1.0
FB2 GND Level
Voltage level to enable internal feedback for BUCK2
with VOUT2 = 2.5V
FB2 External Feedback Level
Voltage level to enable external feedback for BUCK2
with FB2 regulated to 1.0V nominal
0.15
FB2 VCC Level
Voltage level to enable internal feedback for BUCK2
with VOUT2 = 1.8V
2.10
GAIN = GND
2
MAX
DAC codes from 0.600V to
1.750V (MAX1816)
OUT2 Adjust Range
Voltage-Positioning Gain
TYP
2
V
5.5
V
0.05
V
1.90
V
V
0
GAIN = REF
1.425
1.500
1.575
GAIN = open
1.900
2.000
2.100
GAIN = VCC
3.800
4.000
4.200
_______________________________________________________________________________________
V/V
Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers
(Circuit of Figure 1, V+ = 15V, VOUT1 = 1.20V, VOUT2 = 2.50V, VCC = VDD = 5.0V, VSKP1/SDN = VSKP2/SDN = VLIN/SDN = 5.0V,
TA = 0°C to +85°C. Typical values are at TA = +25°C, unless otherwise noted.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Current-Sense Differential Input
Range (CS1+, CS1-)
200
mV
Remote-Sense Differential Input
Range (CS1+, FBS)
300
mV
Remote-Sense Differential Input
Range (GDS, AGND)
200
mV
µA
CS1+, FBS Input Bias Current
-300mV < VCS1+ - VFBS < +300mV
-60
+60
CS1- Input Bias Current
-100mV < VCS1+ - VCS1- < +100mV, VCS1- = VFBS
-60
+60
µA
GDS Input Bias Current
-3
+3
µA
FB2 Input Bias Current
-0.2
+0.2
OUT2 Input Resistance
70
TIME Frequency Accuracy
BUCK1 On-Time (Note 2)
252kHz nominal, RTIME = 143kΩ
-8
+8
53kHz nominal to 530kHz nominal,
RTIME = 680kΩ to 68kΩ
-12
+12
V+ = 5V, CS1- = 1.2V
TON = GND (1000kHz)
230
260
290
TON = REF (550kHz)
165
190
215
TON = open (300kHz)
320
355
390
TON = VCC (200kHz)
465
515
565
TON = GND (715kHz)
630
720
810
TON = REF (390kHz)
495
550
605
TON = open (390kHz)
495
550
605
TON = VCC (260kHz)
740
V+ = 12V, CS1- = 1.2V
V+ = 5V, OUT2 = 2.5V
BUCK2 On-Time (Note 2)
V+ = 12V, OUT2 = 2.5V
µA
kΩ
%
ns
ns
825
910
TON = open, TON = VCC (Note 2)
425
500
TON = GND, TON = REF (Note 2)
325
375
Quiescent Supply Current (VCC)
Measured at VCC, with FBS, OUT2, FB2, and LINFB
forced above the no-load regulation point
2200
3800
µA
Partial Shutdown Supply Current
(Linear Regulator On Only)
VSKP1/SDN = 0V, VSKP2/SDN = 0V, VLIN/SDN = 5V;
measured at VCC, with FBS and LINFB forced above
the no-load regulation point
425
650
µA
Partial Shutdown Supply Current
(BUCK1 and Linear Regulator)
VSKP1/SDN = 5V, VSKP2/SDN = 0V, VLIN/SDN = 5V;
measured at VCC, with FBS and LINFB forced above
the no-load regulation point
1825
3000
µA
Partial Shutdown Supply Current
(BUCK2 Only)
VSKP1/SDN = 0V, VSKP2/SDN = 5V, VLIN/SDN = 0V;
measured at VCC, with OUT2 and FB2 forced above
the regulation point
600
1100
µA
Quiescent Supply Current (VDD)
Measured at VDD, with FBS, OUT2, and FB2 forced
above the no-load regulation point
<1
5
µA
Minimum Off-Time
ns
_______________________________________________________________________________________
3
MAX1816/MAX1994
ELECTRICAL CHARACTERISTICS (continued)
MAX1816/MAX1994
Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = 15V, VOUT1 = 1.20V, VOUT2 = 2.50V, VCC = VDD = 5.0V, VSKP1/SDN = VSKP2/SDN = VLIN/SDN = 5.0V,
TA = 0°C to +85°C. Typical values are at TA = +25°C, unless otherwise noted.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Quiescent Battery Current
Measured at V+
25
40
µA
Shutdown Supply Current (VCC)
VSKP1/SDN = 0V, VSKP2/SDN = 0V, and VLIN/SDN = 0V
4
10
µA
Shutdown Supply Current (VDD)
VSKP1/SDN = 0V, VSKP2/SDN = 0V, and VLIN/SDN = 0V
<1
5
µA
Shutdown Battery Current
VSKP1/SDN = VSKP2/SDN = 0V, measured at V+, with
VCC = VDD = 0V or 5V
<1
5
µA
Reference Voltage
VCC = 4.5V to 5.5V, IREF = 50µA sourcing
2.00
2.02
V
1.98
IREF = 0 to 50µA
0
7
IREF = 50µA to 100µA
0
7
Reference Sink Current
REF in regulation
10
OVPSET Disable Mode Threshold
Voltage at OVPSET above which the OVP functions
are disabled for BUCK1 and BUCK2
VCC 1.5
VCC 0.5
V
OVPSET Default Mode Threshold
for BUCK1
Voltage at OVPSET below which the OVP thresholds
are set to their default values
0.4
0.6
V
Overvoltage Trip Threshold for
BUCK1 (Fixed OVP Threshold)
OVPSET = GND,
measured at FBS
MAX1816
1.95
2.00
2.05
MAX1994
2.20
2.25
2.30
VOVPSET = 1.0V,
measured at FBS
MAX1816
0.95
1.00
1.05
MAX1994
1.075
1.125
1.175
MAX1816
1.95
2.00
2.05
MAX1994
2.20
2.25
2.30
115
117
%
+100
nA
Reference Load Regulation
Overvoltage Trip Threshold for
BUCK1 (Adjustable Threshold)
VOVPSET = 2.0V,
measured at FBS
mV
µA
V
V
Overvoltage Trip Threshold for
BUCK2
Measured at OUT2 (or FB2 if external feedback is
used)
113
OVPSET Bias Current
0V < VOVPSET < VCC
-100
Overvoltage Fault Propagation
Delay
FBS, OUT2, FB2, and LINFB forced 2% above the
no-load trip threshold
Output Undervoltage Protection
Threshold
With respect to unloaded output voltage, FBS, and
OUT2 (FB2 in external feedback)
Output Undervoltage Fault
Propagation Delay
FBS, OUT2, FB2, and LINFB forced 2% below trip
threshold
10
µs
Output Undervoltage Protection
Blanking Time for FBS
From SKP1/SDN signal going high; clock speed set
by RTIME (Note 3)
256
Clks
Output Undervoltage Protection
Blanking Time for OUT2
From SKP2/SHDN signal going high; clock speed set
by RTIME (Note 3)
4096
Clks
Linear Regulator (LINFB)
Undervoltage Protection Blanking
Time
Linear regulator; from LIN/SDN signal going high;
clock speed set by RTIME (Note 3)
512
Clks
4
10
65
70
_______________________________________________________________________________________
µs
75
%
Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers
(Circuit of Figure 1, V+ = 15V, VOUT1 = 1.20V, VOUT2 = 2.50V, VCC = VDD = 5.0V, VSKP1/SDN = VSKP2/SDN = VLIN/SDN = 5.0V,
TA = 0°C to +85°C. Typical values are at TA = +25°C, unless otherwise noted.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VCC 1.5
VCC 1.0
VCC 0.5
V
CS1+ - CS1-; VILIM1 = VCC
40
50
60
mV
CS1+ - CS1-; VILIM1 = 0.5V
40
50
60
CS1+ - CS1-; VILIM1 = 2.0V
160
200
240
BUCK1 Negative Current-Limit
Threshold (Fixed)
CS1+ - CS1-; VILIM1 = VCC
-90
-72
-55
mV
ILIM1 Input Bias Current
0 to 2V
-100
+100
nA
CS2 Input Bias Current
0 to 28V
-1
+1
µA
ILIM1 Default Threshold
BUCK1 Current-Limit Threshold
(Fixed)
BUCK1 Current-Limit Threshold
(Adjustable)
mV
VCC 1.5
VCC 1.0
VCC 0.5
V
AGND - CS2; VILIM2 = VCC
40
50
60
mV
AGND - CS2; VILIM2 = 0.5V
40
50
60
AGND - CS2; VILIM2 = 2.0V
160
200
240
BUCK2 Negative Current-Limit
Threshold (Fixed)
AGND - CS2; VILIM2 = VCC
-90
-72
-55
mV
ILIM2 Input Bias Current
0 to 2V
-100
+100
nA
Thermal-Shutdown Threshold
15°C hysteresis
VCC Undervoltage Lockout
Threshold
Rising edge, hysteresis = 20mV
DH1 Gate-Driver On-Resistance
BST1–LX1 forced to 5V (Note 4)
ILIM2 Default Threshold
BUCK2 Current-Limit Threshold
(Fixed)
BUCK2 Current-Limit Threshold
(Adjustable)
mV
4.10
C
4.45
V
1
4.5
Ω
1
4.5
DL1 low state (pulldown) (Note 4)
0.35
2
DH1 Gate-Driver Source/Sink
Current
DH1 forced to 2.5V, BST–LX forced to 5V
1.5
A
DL1 Gate-Driver Sink Current
DL1 forced to 2.5V
5
A
DL1 Gate-Driver Source Current
DL1 forced to 2.5V
1.5
A
DL1 rising
35
DH1 rising
26
BST2–LX2 forced to 5V (Note 4)
2
8
2
8
0.7
3
DL1 Gate-Driver On-Resistance
Dead Time
DH2 Gate-Driver On-Resistance
DL2 Gate-Driver On-Resistance
DL1 high state (pullup) (Note 4)
o
160
DL2 high state (pullup) (Note 4)
DL2 low state (pulldown) (Note 4)
Ω
ns
Ω
Ω
_______________________________________________________________________________________
5
MAX1816/MAX1994
ELECTRICAL CHARACTERISTICS (continued)
MAX1816/MAX1994
Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = 15V, VOUT1 = 1.20V, VOUT2 = 2.50V, VCC = VDD = 5.0V, VSKP1/SDN = VSKP2/SDN = VLIN/SDN = 5.0V,
TA = 0°C to +85°C. Typical values are at TA = +25°C, unless otherwise noted.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DH2 Gate-Driver Source/Sink Current DH2 forced to 2.5V, BST2–LX2 forced to 5V
0.75
A
DL2 Gate-Driver Sink Current
DL2 forced to 2.5V
2.5
A
DL2 Gate-Driver Source Current
DL2 forced to 2.5V
0.75
A
Dead Time
LINFB Input Bias Current
LINBSE Drive Current
DL2 rising
35
DH2 rising
26
VLINFB = 1.035V
-100
+100
VLINFB = 1.05V, VLINBSE = 5V
VLINFB = 0.965V, VLINBSE = 0.5V
ns
0.4
20
mA
LINFB Regulation Voltage
VLINBSE = 5V, ILINBSE = 4mA (sink)
0.988
1.000
LINFB Load Regulation
VLINBSE = 5V, ILINBSE = 2mA to 10mA (sink)
-2.2
-1.2
Logic Input High Voltage
D0–D4, SUS, PERF, LIN/SDN
2.4
Logic Input Low Voltage
D0–D4, SUS, PERF, LIN/SDN
Logic Input High Voltage
DPSLP
Logic Input Low Voltage
DPSLP
Logic Input Current
D0–D4, SUS, PERF, LIN/SDN, DPSLP = 0V or 5V
Four-Level Logic VCC Level
TON, S0, S1, GAIN logic input high level
VCC 0.4
Four-Level Logic Float Level
TON, S0, S1, GAIN logic input upper midlevel
3.15
3.85
V
Four-Level Logic REF Level
TON, S0, S1. GAIN logic input lower midlevel
1.65
2.35
V
Four-Level Logic GND Level
TON, S0, S1, GAIN logic input low level
0.5
V
+3
µA
V
0.8
SKP1/SDN, SKP2/SDN Skip Level
SKP1/SDN, SKP2/SDN logic input high level
2.8
SKP1/SDN, SKP2/SDN PWM Level
SKP1/SDN, SKP2/SDN logic input float level
1.4
SKP1/SDN, SKP2/SDN Shutdown
Level
SKP1/SDN, SKP2/SDN logic input low level
SKP1/SDN Test Mode Input Voltage
Range
To enable no-fault mode, 4.5V < VCC < 5.5V
10.8
PGOOD Lower Trip Threshold
Measured at FBS, OUT2, and FB2 with respect to
unloaded output voltage, falling edge, typical
hysteresis = 1%
-12.0
LINGOOD Lower Trip Threshold
and LINFB Undervoltage Protection
Threshold
Measured at LINFB with respect to unloaded output
voltage, falling edge (Note 5)
PGOOD Upper Trip Threshold
Measured at FBS, OUT_, FB2 with respect to
unloaded output voltage, rising edge, typical
hysteresis = 1%
V
V
-1
-3
V
%
0.8
SKP1/SDN, SKP2/SDN, S0, S1,
SKP1/SDN, SKP2/SDN, TON, S0, S1, GAIN forced to
GAIN, and TON Logic-Input Current GND or VCC
6
1.017
nA
0.4
V
+1
µA
V
V
2.2
V
0.4
V
13.2
V
-10.0
-8.0
%
-12.0
-10.0
-8.0
%
8.0
10.0
12.0
%
_______________________________________________________________________________________
Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers
(Circuit of Figure 1, V+ = 15V, VOUT1 = 1.20V, VOUT2 = 2.50V, VCC = VDD = 5.0V, VSKP1/SDN = VSKP2/SDN = VLIN/SDN = 5.0V,
TA = 0°C to +85°C. Typical values are at TA = +25°C, unless otherwise noted.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
8.0
10.0
12.0
%
LINGOOD Upper Trip Threshold
and LINFB Overvoltage Trip
Threshold
Measured at LINFB with respect to unloaded output
voltage, rising edge (Note 5)
PGOOD Propagation Delay
OUT_, FB2 forced 2% above or below PGOOD trip
threshold
LINGOOD Turn-On Delay
LINFB forced 2% above LINGOOD lower trip
threshold
LINGOOD Turn-Off Delay
LINFB forced 2% below LINGOOD lower trip
threshold
10
µs
PGOOD Transition Delay
After the output-voltage transition on BUCK1 is
complete (PGOOD blanking is enabled for N + 4
clocks, blanking is excluded in startup and
shutdown)
4
Clk
After the output-voltage transition on BUCK1 is
Forced-PWM Mode Transition Delay complete (forced-PWM mode persists for N + 32
clocks for all transitions)
32
Clk
Open-Drain Output Low Voltage
(PGOOD, LINGOOD)
ISINK = 3mA
Open-Drain Leakage Current
(PGOOD, LINGOOD)
High state, forced to 5.5V
Input Current
OFS0–OFS2
OFS Positive Offset when
Programmed to Zero
Deviation in the output voltage when tested with
OFS_ connected to REF
OFS Gain
10
µs
1
ms
-0.1
0.4
V
1
µA
+0.1
µA
2
mV
∆VOUT / ∆VOFS, ∆VOFS = (0.8V - 0V)
0.119
0.125
0.131
∆VOUT / ∆VOFS, ∆VOFS = (2.0V - 1.2V)
0.119
0.125
0.131
V/V
_______________________________________________________________________________________
7
MAX1816/MAX1994
ELECTRICAL CHARACTERISTICS (continued)
MAX1816/MAX1994
Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, V+ = 15V, VOUT1 = 1.20V, VOUT2 = 2.50V, VCC = VDD = 5.0V, VSKP1/SDN = VSKP2/SDN = VLIN/SDN = 5.0V,
TA = -40°C to +100°C, unless otherwise noted.) (Note 6)
PARAMETER
Input Voltage Range
CONDITIONS
Battery voltage V+
V+ = 4.5V to 28V, includes
load regulation errors,
OFS_ = GDS = AGND,
CS1+ = CS1- = FBS
BUCK2 Error Comparator
Threshold (DC Output-Voltage
Accuracy) (Note 1)
V+ = 4.5V to 28V
MAX
TON = REF, open, or VCC
2
2
16
4.5
5.5
-1.5
+1.5
FB2 = GND
2.463
2.538
FB2 = VCC
1.773
1.827
FB2 = OUT2
0.985
1.015
DAC codes from 0.600V to
1.750V (MAX1816)
UNITS
28
V
%
DAC codes from 0.700V to
2.000V (MAX1994)
OUT2 Adjust Range
Voltage-Positioning Gain
TYP
TON = GND
VCC, VDD
BUCK1 DC Output-Voltage
Accuracy
MIN
1.0
5.5
GAIN = REF
1.425
1.575
GAIN = open
1.900
2.100
GAIN = VCC
3.800
4.200
V
V
V/V
Current-Sense Differential Input
Range (CS1+, CS1-)
200
mV
Remote-Sense Differential Input
Range (CS1+, FBS)
300
mV
Remote-Sense Differential Input
Range (GDS, AGND)
200
mV
CS1+, FBS Input Bias Current
-300mV < VCS1+ - VFBS < +300mV
-60
+60
µA
CS1- Input Bias Current
-100mV < VCS1+ - VCS1- < +100mV, VCS1- = VFBS
-60
+60
µA
252kHz nominal; RTIME =143kΩ
-8
+8
53kHz nominal to 530kHz nominal; RTIME = 680kΩ to 68kΩ
-12
+12
V+ = 5V, CS1- = 1.2V
TIME Frequency Accuracy
BUCK1 On-Time (Note 2)
BUCK2 On-Time (Note 2)
Minimum Off-Time
Quiescent Supply Current (VCC)
8
TON = GND (1000kHz)
230
290
TON = REF (550kHz)
165
215
V+ = 12V, CS1- = 1.2V
TON = open (300kHz)
320
390
TON = VCC (200kHz)
465
565
V+ = 5V, OUT2 = 2.5V
TON = GND (715kHz)
630
810
TON = REF (390kHz)
495
605
TON = open (390kHz)
495
605
TON = VCC (260kHz)
740
910
V+ = 12V, OUT2 = 2.5V
TON = open, TON = VCC (Note 2)
500
TON = GND, TON = REF (Note 2)
375
Measured at VCC, with FBS, OUT2, FB2, and LINFB
forced above the no-load regulation point
4500
_______________________________________________________________________________________
%
ns
ns
ns
µA
Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers
(Circuit of Figure 1, V+ = 15V, VOUT1 = 1.20V, VOUT2 = 2.50V, VCC = VDD = 5.0V, VSKP1/SDN = VSKP2/SDN = VLIN/SDN = 5.0V,
TA = -40°C to +100°C, unless otherwise noted.) (Note 6)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Partial Shutdown Supply Current
(Linear Regulator On Only)
VSKP1/SDN = 0V, VSKP2/SDN = 0V, VLIN/SDN = 5V;
measured at VCC, with FBS and LINFB forced above the
no-load regulation point
750
µA
Partial Shutdown Supply Current
(BUCK1 and Linear Regulator)
VSKP1/SDN = 5V, VSKP2/SDN = 0V, VLIN/SDN = 5V;
measured at VCC, with FBS and LINFB forced above the
no-load regulation point
3400
µA
Partial Shutdown Supply Current
(BUCK2 Only)
VSKP1/SDN = 0V, VSKP2/SDN = 5V, VLIN/SDN = 0V;
measured at VCC, with OUT2 and FB2 forced above the
regulation point
1400
µA
Quiescent Supply Current (VDD)
Measured at VDD, with FBS, OUT2, and FB2 forced above
the no-load regulation point, TA = -40°C to +85°C
5
µA
Quiescent Battery Current
Measured at V+
40
µA
Shutdown Supply Current (VCC)
VSKP1/SDN = 0V, VSKP2/SDN = 0V, and VLIN/SDN = 0V,
TA = -40°C to +85°C
10
µA
Shutdown Supply Current (VDD)
VSKP1/SDN = 0V, VSKP2/SDN = 0V, and VLIN/SDN = 0V,
TA = -40°C to +85°C
5
µA
Shutdown Battery Current
VSKP1/SDN = VSKP2/SDN = 0V, measured at V+, with
VCC = VDD = 0V or 5V, TA = -40°C to +85°C
5
µA
Reference Voltage
VCC = 4.5V to 5.5V, IREF = 50µA sourcing
1.98
2.02
V
IREF = 0 to 50µA
0
7
IREF = 50µA to 100µA
0
7
Reference Sink Current
REF in regulation
10
OVPSET Disable Mode Threshold
Voltage at OVPSET above which the OVP functions are
disabled for BUCK1 and BUCK2
VCC 1.5
VCC 0.5
V
OVPSET Default Mode Threshold
for BUCK1
Voltage at OVPSET below which the OVP thresholds are
set to their default values
0.4
0.6
V
Overvoltage Trip Threshold for
BUCK1 (Fixed OVP Threshold)
OVPSET = GND,
measured at FBS
MAX1816
1.95
2.05
MAX1994
2.20
2.30
VOVPSET = 1.0V,
measured at FBS
MAX1816
0.95
1.05
MAX1994
1.075
1.175
VOVPSET = 2.0V,
measured at FBS
MAX1816
1.95
2.05
MAX1994
2.20
2.30
Reference Load Regulation
Overvoltage Trip Threshold for
BUCK1 (Adjustable Threshold)
mV
µA
V
V
Overvoltage Trip Threshold for
BUCK2
Measured at OUT2 (or FB2 if external feedback is used)
113
117
%
Output Undervoltage Protection
Threshold
With respect to unloaded output voltage FBS and OUT2
(FB2 in external feedback)
65
75
%
_______________________________________________________________________________________
9
MAX1816/MAX1994
ELECTRICAL CHARACTERISTICS (continued)
MAX1816/MAX1994
Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = 15V, VOUT1 = 1.20V, VOUT2 = 2.50V, VCC = VDD = 5.0V, VSKP1/SDN = VSKP2/SDN = VLIN/SDN = 5.0V,
TA = -40°C to +100°C, unless otherwise noted.) (Note 6)
PARAMETER
CONDITIONS
ILIM1 Default Threshold
BUCK1 Current-Limit Threshold
(Fixed)
BUCK1 Current-Limit Threshold
(Adjustable)
BUCK1 Negative Current-Limit
Threshold (Fixed)
CS1+ - CS1-; VILIM1 = VCC
TYP
MAX
UNITS
VCC 1.5
VCC 0.5
V
40
60
mV
CS1+ - CS1-; VILIM1 = 0.5V
40
60
CS1+ - CS1-; VILIM1 = 2.0V
160
240
CS1+ - CS1-; VILIM1 = VCC
-90
-55
mV
VCC 1.5
VCC 0.5
V
40
60
mV
ILIM2 Default Threshold
BUCK2 Current-Limit Threshold
(Fixed)
MIN
AGND - CS2; VILIM2 = VCC
mV
AGND - CS2; VILIM2 = 0.5V
40
60
AGND - CS2; VILIM2 = 2.0V
160
240
BUCK2 Negative Current-Limit
Threshold (Fixed)
AGND - CS2; VILIM2 = VCC
-90
-55
mV
VCC Undervoltage Lockout
Threshold
Rising edge, hysteresis = 20mV
4.10
4.45
V
DH1 Gate-Driver On-Resistance
BST1–LX1 forced to 5V (Note 4)
4.5
Ω
DL1 high state (pullup) (Note 4)
4.5
BUCK2 Current-Limit Threshold
(Adjustable)
DL1 Gate-Driver On-Resistance
DH2 Gate-Driver On-Resistance
DL2 Gate-Driver On-Resistance
LINBSE Drive Current
DL1 low state (pulldown) (Note 4)
2
BST2–LX1 forced to 5V (Note 4)
8
DL2 high state (pullup) (Note 4)
8
DL2 low state (pulldown) (Note 4)
3
VLINFB = 1.05V, VLINBSE = 5V
VLINFB = 0.965V, VLINBSE = 0.5V
0.4
20
LINFB Regulation Voltage
VLINBSE = 5V, ILINBSE = 4mA (sink)
LINFB Load Regulation
VLINBSE = 5V, ILINBSE = 2mA to 10mA (sink)
0.988
-2.2
Logic Input High Voltage
D0–D4, SUS, PERF, LIN/SDN
2.4
Logic Input Low Voltage
D0–D4, SUS, PERF, LIN/SDN
Logic Input High Voltage
DPSLP
Logic Input Low Voltage
DPSLP
1.017
mV
Ω
Ω
Ω
mA
V
%
V
0.8
0.8
V
V
0.4
V
Four-Level Logic VCC Level
TON, S0, S1, GAIN logic input high level
VCC 0.4
Four-Level Logic Float Level
TON, S0, S1, GAIN logic input upper midlevel
3.15
3.85
V
Four-Level Logic REF Level
TON, S0, S1, GAIN logic input lower midlevel
1.65
2.35
V
Four-Level Logic GND Level
TON, S0, S1, GAIN logic input low level
0.5
V
10
______________________________________________________________________________________
V
Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers
(Circuit of Figure 1, V+ = 15V, VOUT1 = 1.20V, VOUT2 = 2.50V, VCC = VDD = 5.0V, VSKP1/SDN = VSKP2/SDN = VLIN/SDN = 5.0V,
TA = -40°C to +100°C, unless otherwise noted.) (Note 6)
PARAMETER
CONDITIONS
MIN
SKP1/SDN, SKP2/SDN Skip
Level
SKP1/SDN, SKP2/SDN logic input high level
2.8
SKP1/SDN, SKP2/SDN PWM
Level
SKP1/SDN, SKP2/SDN logic input float level
1.4
SKP1/SDN, SKP2/SDN Shutdown
Level
SKP1/SDN, SKP2/SDN logic input low level
PGOOD Lower Trip Threshold
Measured at FBS, OUT2, and FB2 with respect to unloaded
output voltage, falling edge, typical hysteresis = 1%
LINGOOD Lower Trip Threshold
and LINFB Undervoltage
Protection Threshold
Measured at LINFB with respect to unloaded output
voltage, falling edge (Note 5)
PGOOD Upper Trip Threshold
TYP
MAX
UNITS
V
2.2
V
0.4
V
-12.5
-7.5
%
-12.5
-7.5
%
Measured at FBS, OUT_, FB2 with respect to unloaded
output voltage, rising edge, typical hysteresis = 1%
7.5
12.5
%
LINGOOD Upper Trip Threshold
and LINFB Overvoltage Trip
Threshold
Measured at LINFB with respect to unloaded output
voltage, rising edge (Note 5)
7.5
12.5
%
LINGOOD Turn-On Delay
LINFB forced 2% above LINGOOD lower trip threshold
Open-Drain Output Low Voltage
(PGOOD, LINGOOD)
ISINK = 3mA
OFS Positive Offset when
Programmed to Zero
Deviation in the output voltage when tested with OFS_
connected to REF
OFS Gain
1
ms
0.4
V
2
mV
∆VOUT / ∆VOFS, ∆VOFS = (0.8V - 0V)
0.119
0.131
∆VOUT / ∆VOFS, ∆VOFS = (2.0V - 1.2V)
0.119
0.131
V/V
Note 1: DC output accuracy specifications for BUCK2 refer to the trip level of the error amp. The output voltage has a DC regulation
higher than the trip level by 50% of the ripple. In SKIP mode, the output rises by approximately 1.5% when transitioning from
continuous conduction to no load.
Note 2: On-time and minimum off-time specifications for both BUCK1 and BUCK2 are measured from 50% to 50% at the DH_ pin
with LX_ forced to zero, BST_ forced to 5V, and a 500pF capacitor from DH_ to LX_ to simulate external MOSFET gate
capacitance. Actual in-circuit times can be different due to MOSFET switching speeds.
Note 3: This does not include the time for REF to start up if required.
Note 4: Production testing limitations due to package handling require relaxed maximum on-resistance specifications for the thin
QFN package.
Note 5: The LINGOOD signal is latched low under a fault condition of LINFB dropping below 90% or rising above 110% of the nominal set point. The LINGOOD signal does not go high again until the fault latch is reset.
Note 6: Specifications from -40°C to +100°C are guaranteed by design, not production tested.
______________________________________________________________________________________
11
MAX1816/MAX1994
ELECTRICAL CHARACTERISTICS (continued)
VOUT1
0.6V TO 1.75V
(MAX1816)
0.7V TO 2.0V
(MAX1994)
REF
R15
196kΩ
1%
R16
3.48kΩ
1%
R18
4.99kΩ
1%
C10
22nF
R19
2Ω
R17
196kΩ
1%
C11
0.047µF
PC BOARD TRACE
RESISTANCE
COUT1
3 × 330µF
R14
2kΩ
1%
R13
196kΩ
1%
R20
2Ω
R4
49.9kΩ
1%
R3
280kΩ
1%
C12
0.047µF
D1
C4
47pF
CONTROL
INPUTS
FLOAT
(GAIN = 2)
Q2
CS1FBS
GDS
4
5
6
OFS1
9
MAX1816
MAX1994
0Ω
SUSPEND
INPUTS
PGND
BST1 48
13 D0
DAC INPUTS
LX1 47
14 D1
12 DPSLP
11 SUS
10 OFS2
OFS0
8
GAIN
CS1+
3
7
CC
ILIM1
2
1
C2
0.1µF
DH1 46
15 D2
Q1
PERF 45
16 D3
CREMOTE
L1
0.6µH
DL1 44
17 D4
PC BOARD TRACE
RESISTANCE
AGND
VDD 42
19 S1
C1
2.2µF
DL2 41
20 SKP1/SDN
D4
DH2 40
21 SKP2/SDN
CIN1
3 × 10µF
LX2 39
22 LIN/SDN
R1
0.001Ω
1%
BST2 38
INPUT VOLTAGE
7V TO 24V
VDD, 5V BIAS SUPPLY
PGND 43
18 S0
OVPSET 25
TIME 26
LINFB 27
LINGOOD 28
LINBSE 29
AGND 30
VCC 31
REF 32
FB2 33
OUT2 34
CS2 35
ILIM2 36
V+ 37
FLOAT
24 TON
12
23 PGOOD
C6
R10
143kΩ
C7
1µF
0.22µF
C5
1000pF
REF
R5
100Ω
R2
0.005Ω
1%
Q4
Q3
D1: CMSH5-40
D2: EC31QS03L
D3, D4: CMPSH-3
C3
0.1µF
D3
L2
1.2µH
R11
100kΩ
R6
10Ω
D2
CIN2
10µF
R9
100kΩ
R12
1%
100kΩ
R8
20kΩ
1%
R7
220Ω
VDD
PGOOD
LINGOOD
C9
10µF
VLIN
1.20V
C8
4.7µF
3.3V
BIAS SUPPLY
VOUT2
2.5V
Q5 FZT749
COUT2
330µF
MAX1816/MAX1994
Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers
Figure 1. Standard Application Circuit
______________________________________________________________________________________
Figure 2. High-Current Master-Slave Application Circuit
______________________________________________________________________________________
13
VOUT1
0.6V TO 1.75V
(MAX1816)
0.7V TO 2.0V
(MAX1994)
PC BOARD TRACE
RESISTANCE
COUT1
6 × 330µF
REF
C10
22nF
R19
2Ω
R27
2Ω
C16
22nF
R24
0.001Ω
1%
R20
2Ω
R28
2Ω
R16
3.48kΩ
1%
R18
4.99kΩ
1%
L3
0.6µH
R14
2kΩ
1%
Q7
Q6
R13
196kΩ
1%
D6
CIN3
3 × 10µF
R15
196kΩ
1%
Q2
R17
196kΩ
1%
C18
0.047µF
C17
0.047µF
D1
R3
280kΩ
47pF
CONTROL
INPUTS
FLOAT
(GAIN = 2)
C4
R4 1%
49.9kΩ
1%
CS1FBS
GDS
4
5
6
OFS1
9
C13
1µF
C19
100pF
C14
0.22µF
D5
12 DPSLP
11 SUS
10 OFS2
OFS0
8
GAIN
CS1+
3
7
CC
ILIM1
2
1
REF
C12
0.1µF
VDD
VCC
DD
DH
LX
DAC INPUTS
BST1 48
13 D0
CREMOTE
C2
0.1µF
LX1 47
14 D1
Q1
DH1 46
15 D2
PC BOARD TRACE
RESISTANCE
DL1 44
PERF 45
16 D3
D4
C1
2.2µF
MAX1816
MAX1994
SUSPEND
INPUTS
MAX1980
R21
34.8kΩ
R26
20Ω
CS+
CS-
TON
CM-
CM+
LINBSE 29
AGND 30
VCC 31
REF 32
FB2 33
OUT2 34
CS2 35
ILIM2 36
C15
270pF
FLOAT
FLOAT
C3
0.1µF
D3
R23
49.9kΩ
1%
OVPSET 25
TIME 26
LINFB 27
LINGOOD 28
R22
280kΩ
1%
LX2 39
22 LIN/SDN
CIN1
3 × 10µF
L1
0.6µH
PGND 43
18 S0
V+
PGND
BST2 38
23 PGOOD
R1
0.001Ω
1%
GND
17 D4
BST
DL
VDD 42
19 S1
LIMIT
DL2 41
20 SKP1/SDN
ILIM
POL
DH2 40
21 SKP2/SDN
TRIG
COMP
V+ 37
24 TON
REF
C6
R9
100kΩ
1%
0Ω
0Ω
VLIN
1.2V
AGND
(SLAVE)
PGOOD
C9
10µF
FZT749
C8
4.7µF
3.3V
BIAS SUPPLY
COUT2
VOUT2
2 × 270µF 2.5V
D1, D6: CMSH5-40
D2: EC31QS03L
D3, D4, D5: CMPSH-3
AGND
(MASTER)
Q5
VDD
R8
.20kΩ
1%
R7
220Ω
R12
100kΩ
R6
10Ω
D2
L2
1.2µH
CIN2
10µF
PGND
R10
143kΩ
C7
1µF
0.22µF
C5
1000pF
REF
R5
100Ω
R2
0.005Ω
1%
Q4
Q3
MAX1816/MAX1994
INPUT VOLTAGE
7V TO 24V
VDD, 5V BIAS SUPPLY
Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers
Typical Operating Characteristics
(Circuit of Figure 1, V+ = 12V, VDD = VCC = VSKP1/SDN = VSKP2/SDN = VLIN/SDN = 5V; VIN(LDO) = 3.3V, VOUT(BUCK1) = 1.25V,
VOUT(BUCK2) = 2.5V; TA = +25°C, unless otherwise noted.)
SKIP MODE
80
70
60
SKIP MODE
90
EFFICIENCY (%)
1.25
1.24
FORCED PWM
1.23
MAX1816 toc03
SKIP MODE
OUTPUT VOLTAGE (V)
VIN = 12V
VIN = 20V
100
MAX1816 toc02
VIN = 7V
80
VIN = 7V
VIN = 12V
VIN = 20V
70
1.22
60
1.21
FORCED PWM
FORCED PWM
0.1
0.01
1
10
0
100
5
10
15
20
25
0.1
0.01
30
1
10
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
OUTPUT VOLTAGE vs. LOAD CURRENT
(BUCK2)
FREQUENCY vs. LOAD CURRENT
(BUCK1 AND BUCK2)
FREQUENCY vs. INPUT VOLTAGE
(BUCK1 AND BUCK2)
BUCK2 PWM MODE
BUCK2 SKIP MODE
BUCK2 IOUT2 = 8A
SKIP MODE
2.54
FORCED PWM
2.52
FREQUENCY (kHz)
300
FREQUENCY (kHz)
2.56
400
MAX1816 toc05
400
MAX1816 toc04
2.58
OUTPUT VOLTAGE (V)
50
1.20
50
MAX1816 toc06
EFFICIENCY (%)
1.26
MAX1816 toc01
100
90
EFFICIENCY vs. LOAD CURRENT
(BUCK2 VOUT2 = 2.5V)
OUTPUT VOLTAGE vs. LOAD CURRENT
(BUCK1)
EFFICIENCY vs. LOAD CURRENT
(BUCK1 VOUT1 = 1.25V)
BUCK1 PWM MODE
BUCK1 SKIP MODE
200
350
BUCK2 IOUT2 = 1A
BUCK1 IOUT1 = 20A
300
100
BUCK1 IOUT1 = 3A
2.50
0
0
2
4
6
10
8
5
10
20
15
10
15
20
INPUT VOLTAGE (V)
FREQUENCY vs. TEMPERATURE
(BUCK1 AND BUCK2)
OUTPUT CURRENT AT CURRENT LIMIT
vs. TEMPERATURE
NO-LOAD SUPPLY CURRENT
vs. INPUT VOLTAGE (SKIP MODE)
BUCK1 IOUT1 = 20A
300
20
BUCK2
10
-20
0
20
40
60
TEMPERATURE (°C)
80
100
ICC + IDD
2700
25
MAX1816 toc09
MAX1816 toc08
BUCK1
30
2400
2100
1800
1500
1200
900
600
300
0
250
3000
SUPPLY CURRENT (µA)
350
40
OUTPUT CURRENT AT CURRENT LIMIT (A)
MAX1816 toc07
BUCK2 IOUT2 = 8A
-40
5
LOAD CURRENT (A)
400
14
250
0
LOAD CURRENT (A)
450
FREQUENCY (kHz)
MAX1816/MAX1994
Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers
I+
0
-40
-20
0
20
40
60
TEMPERATURE (°C)
80
100
5
10
15
INPUT VOLTAGE (V)
______________________________________________________________________________________
20
25
Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers
NO-LOAD SUPPLY CURRENT
vs. INPUT VOLTAGE (PWM MODE)
BUCK1 LOAD TRANSIENT RESPONSE
(SKIP MODE)
MAX1816 toc10
MAX1816 toc11
50
ICC + IDD
SUPPLY CURRENT (mA)
40
20A
A
0
I+
1.35V
30
B
1.25V
20
1.15V
10
20A
C
0
0
5
10
15
25
20
20µs/div
A: LOAD CURRENT, 20A/div
B: OUTPUT VOLTAGE, 100mV/div, AC-COUPLED
C: INDUCTOR CURRENT, 20A/div
INPUT VOLTAGE (V)
BUCK1 LOAD TRANSIENT RESPONSE
(PWM MODE)
BUCK2 LOAD TRANSIENT RESPONSE
(SKIP MODE)
MAX1816 toc12
MAX1816 toc13
20A
A
0
2.6V
A
2.5V
1.35V
2.4V
1.25V
B
1.15V
10A
B
C
20µs/div
A: LOAD CURRENT, 20A/div
B: OUTPUT VOLTAGE, 100mV/div, AC-COUPLED
C: INDUCTOR CURRENT, 20A/div
20A
5A
0
0
20µs/div
A: OUTPUT VOLTAGE, 100mV/div, AC-COUPLED
B: INDUCTOR CURRENT, 5A/div
______________________________________________________________________________________
15
MAX1816/MAX1994
Typical Operating Characteristics (continued)
(Circuit of Figure 1, V+ = 12V, VDD = VCC = VSKP1/SDN = VSKP2/SDN = VLIN/SDN = 5V; VIN(LDO) = 3.3V, VOUT(BUCK1) = 1.25V,
VOUT(BUCK2) = 2.5V; TA = +25°C, unless otherwise noted.)
MAX1816/MAX1994
Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers
Typical Operating Characteristics (continued)
(Circuit of Figure 1, V+ = 12V, VDD = VCC = VSKP1/SDN = VSKP2/SDN = VLIN/SDN = 5V; VIN(LDO) = 3.3V, VOUT(BUCK1) = 1.25V,
VOUT(BUCK2) = 2.5V; TA = +25°C, unless otherwise noted.)
BUCK1 STARTUP WAVEFORM
(PWM MODE, NO LOAD)
BUCK2 LOAD TRANSIENT RESPONSE
(PWM MODE)
MAX1816 toc15
MAX1816 toc14
2.6V
A
2V
1V
A
2.5V
0
2.4V
10A
B
0
10A
B
5A
0
2V
C
0
100µs/div
A: OUTPUT VOLTAGE, 1V/div
B: INDUCTOR CURRENT, 10A/div
C: SKP1/SDN SIGNAL, 2V/div
20µs/div
A: OUTPUT VOLTAGE, 100mV/div, AC-COUPLED
B: INDUCTOR CURRENT, 5A/div
BUCK1 STARTUP WAVEFORM
(PWM MODE, IOUT1 = 20A)
MAX1816 toc16
BUCK2 STARTUP WAVEFORM
(PWM MODE, NO LOAD)
1V
A
MAX1816 toc17
2V
4V
2V
A
0
0
20A
10A
B
10A
B
0
0
2V
C
2V
C
0
100µs/div
A: OUTPUT VOLTAGE, 1V/div
B: INDUCTOR CURRENT, 10A/div
C: SKP1/SDN SIGNAL, 2V/div
16
0
40µs/div
A: OUTPUT VOLTAGE, 2V/div
B: INDUCTOR CURRENT, 10A/div
C: SKP2/SDN SIGNAL, 2V/div
______________________________________________________________________________________
Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers
BUCK2 STARTUP WAVEFORM
(PWM MODE, IOUT2 = 8A)
MAX1816 toc18
BUCK1 DYNAMIC OUTPUT-VOLTAGE TRANSITION
(PWM MODE)
MAX1816 toc19
4V
2V
A
0
1.5V
A
1V
10A
10A
B
0
B
0
5V
C
0
2V
C
5V
D
0
0
40µs/div
A: OUTPUT VOLTAGE, 2V/div
B: INDUCTOR CURRENT, 10A/div
C: SKP2/SDN SIGNAL, 2V/div
100µs/div
VOUT1 = 1.40V TO 1.00V TO 1.40V
IOUT1 = 3A, RTIME = 143kΩ
A: OUTPUT VOLTAGE, 500mV/div
B: INDUCTOR CURRENT, 10A/div
C: PGOOD SIGNAL, 5V/div
D: VID BIT, 5V/div
BUCK1 DYNAMIC OUTPUT-VOLTAGE TRANSITION
(SKIP MODE)
MAX1816 toc20
BUCK1 DYNAMIC OUTPUT-VOLTAGE TRANSITION
(SKIP MODE)
MAX1816 toc21
1.5V
A
1V
1V
A
0.5V
10A
B
0
5V
C
10A
B
0
5V
C
0
0
5V
D
5V
D
0
100µs/div
VOUT1 = 1.40V TO 1.00V TO 1.40V
IOUT1 = 1A, RTIME = 143kΩ
A: OUTPUT VOLTAGE, 500mV/div
B: INDUCTOR CURRENT, 10A/div
C: PGOOD SIGNAL, 5V/div
D: VID BIT, 5V/div
0
100µs/div
VOUT1 = 1.00V TO 0.60V TO 1.00V
IOUT1 = 1A, RTIME = 143kΩ
A: OUTPUT VOLTAGE, 500mV/div
B: INDUCTOR CURRENT, 10A/div
C: PGOOD SIGNAL, 5V/div
D: SUS SIGNAL, 5V/div
______________________________________________________________________________________
17
MAX1816/MAX1994
Typical Operating Characteristics (continued)
(Circuit of Figure 1, V+ = 12V, VDD = VCC = VSKP1/SDN = VSKP2/SDN = VLIN/SDN = 5V; VIN(LDO) = 3.3V, VOUT(BUCK1) = 1.25V,
VOUT(BUCK2) = 2.5V; TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(Circuit of Figure 1, V+ = 12V, VDD = VCC = VSKP1/SDN = VSKP2/SDN = VLIN/SDN = 5V; VIN(LDO) = 3.3V, VOUT(BUCK1) = 1.25V,
VOUT(BUCK2) = 2.5V; TA = +25°C, unless otherwise noted.)
BUCK1 SHUTDOWN WAVEFORM
(SKIP MODE, NO LOAD)
MAX1816 toc22
BUCK1 SHUTDOWN WAVEFORM
(PWM MODE, IOUT2 = 20A)
MAX1816 toc23
2V
1V
A
2V
1V
A
0
0
20A
B
10A
10A
0
0
B
-10A
5V
5V
C
C
0
0
100µs/div
A: OUTPUT VOLTAGE, 1V/div
B: INDUCTOR CURRENT, 10A/div
C: SKP1/SDN SIGNAL, 5V/div
100µs/div
A: OUTPUT VOLTAGE, 1V/div
B: INDUCTOR CURRENT, 10A/div
C: SKP1/SDN SIGNAL, 5V/div
OUTPUT OFFSET
vs. OFS INPUT VOLTAGE
BUCK1 OUTPUT-VOLTAGE DISTRIBUTION
(VOUT1 = 1.25V, SAMPLE SIZE = 55)
SAMPLE PERCENTAGE (%)
100
0
-100
MAX1816 toc25
30
MAX1816 toc24
200
OUTPUT OFFSET (mV)
MAX1816/MAX1994
Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers
20
10
UNDEFINED
REGION
-200
0
0
0.5
1.0
VOFS (V)
18
1.5
2.0
1.248
1.249
1.250
1.251
1.252
BUCK1 OUTPUT VOLTAGE (V)
______________________________________________________________________________________
Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers
1.208
1.206
1.204
1.202
1.999
2.000
2.001
2.002
1.20
1.19
1.18
1.17
1.16
1.200
0
1.21
OUTPUT VOLTAGE (V)
10
1.22
MAX1816 toc27
MAX1816 toc26
20
LINEAR REGULATOR LINE REGULATION
LINEAR REGULATOR LOAD REGULATION
1.210
OUTPUT VOLTAGE (V)
SAMPLE PERCENTAGE (%)
30
MAX1816 toc28
REFERENCE VOLTAGE DISTRIBUTION
(VREF = 2.0V, SAMPLE SIZE = 55)
1
0.1
10
100
0
1000
LINEAR REGULATOR LOAD
TRANSIENT RESPONSE
4
6
8
10
12
LINEAR REGULATOR STARTUP WAVEFORM
MAX1816 toc30
MAX1816 toc29
400mA
A
2
INPUT VOLTAGE (V)
LOAD CURRENT (mA)
REFERENCE VOLTAGE (V)
5V
A
200mA
0
0
2V
1V
B
0
1.2V
B
1.19V
400mA
C
200mA
0
20µs/div
A: LOAD CURRENT, 200mA/div
B: OUTPUT VOLTAGE, 10mV/div, AC-COUPLED
20µs/div
A: VLIN/SDN, 5V/div
B: VLIN = 1.2V, 1V/div
C: ILIN = 300mA, 200mA/div
______________________________________________________________________________________
19
MAX1816/MAX1994
Typical Operating Characteristics (continued)
(Circuit of Figure 1, V+ = 12V, VDD = VCC = VSKP1/SDN = VSKP2/SDN = VLIN/SDN = 5V; VIN(LDO) = 3.3V, VOUT(BUCK1) = 1.25V,
VOUT(BUCK2) = 2.5V; TA = +25°C, unless otherwise noted.)
Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers
MAX1816/MAX1994
Pin Description
PIN
FUNCTION
1
ILIM1
BUCK1 Current-Limit Adjustment. The CS1+ - CS1- current-limit threshold defaults to 50mV if ILIM1 is
connected to VCC. In adjustable mode, the current-limit threshold voltage is precisely 1/10th of the voltage
at ILIM1. The logic threshold for switchover to the default value is approximately VCC - 1V.
2
CC
Integrator Time Constant Control Input. This pin allows the integrator to be compensated independent of
the voltage-positioning sense feedback path. Connect a 47pF to 1000pF capacitor from this pin to ground
to control the integration time constant.
CS1+
Positive Voltage-Positioning and Current-Sense Input for BUCK1. The current-limit sense voltage for
CS1+ - CS1- is 1/10th of the voltage at the ILIM1 input. The CS1+ and CS1- inputs are also used for active
voltage positioning, with the voltage-positioning gain set with the GAIN pin. Connecting the GAIN pin to
ground disables voltage positioning. Positive and negative current limits are always active.
4
CS1-
Negative Voltage-Positioning and Current-Sense Input for BUCK1. CS1- is also the output sense input for
calculating TON. The current-limit sense voltage for CS1+ - CS1- is 1/10th of the voltage at the ILIM1 input.
The CS1+ and CS1- inputs are also used for active voltage positioning, with the voltage-positioning gain
set with the GAIN pin. Connecting the GAIN pin to ground disables voltage positioning. Positive and
negative current limits are always active.
5
FBS
Output Feedback Remote-Sense Input for BUCK1. Connect FBS directly to the load. FBS internally
connects to an amplifier that fine-tunes the output voltage, compensating for voltage drops from the
regulator output to the load.
6
GDS
Ground Remote-Sense Input for BUCK1. Connect GDS directly to the load. GDS internally connects to an
amplifier that fine-tunes the output voltage, compensating for voltage drops from the regulator ground to
the load ground.
GAIN
Voltage-Positioning Gain Control. GAIN is a four-level logic input that selects the voltage-positioning gain
(see CS1+, CS1- pins). The gain setting does not affect current-limit functions. Connecting GAIN to GND
disables the voltage positioning by setting the gain to zero. Connecting GAIN to REF sets the gain to 1.5.
Leaving GAIN open sets the gain to 2. Connecting GAIN to VCC sets the gain to 4.
GND = 0; REF = 1.5; open = 2; VCC = 4.
OFS0
Voltage-Divider Input for Voltage-Positioning Offset Control. OFS0–OFS2 are selected based on the SUS,
PERF, and DPSLP signals. For 0V < OFS_ < 0.8V, 0.125 times the voltage at OFS_ is subtracted from the
output. For 1.2V < OFS_ < 2.0V, 0.125 times the difference between REF and OFS_ is added to the output.
Voltages in the range of 0.8V < OFS_ < 1.2V are not permitted (see Table 7).
OFS1
Voltage-Divider Input for Voltage-Positioning Offset Control. OFS0–OFS2 are selected based on the SUS,
PERF, and DPSLP signals. For 0V < OFS_ < 0.8V, 0.125 times the voltage at OFS_ is subtracted from the
output. For 1.2V < OFS_ < 2.0V, 0.125 times the difference between REF and OFS_ is added to the output.
Voltages in the range of 0.8V < OFS_ < 1.2V are not permitted (see Table 7).
OFS2
Voltage-Divider Input for Voltage-Positioning Offset Control. OFS0–OFS2 are selected based on the SUS,
PERF, and DPSLP signals. For 0V < OFS_ < 0.8V, 0.125 times the voltage at OFS_ is subtracted from the
output. For 1.2V < OFS_ < 2.0V, 0.125 times the difference between REF and OFS_ is added to the output.
Voltages in the range of 0.8V < OFS_ < 1.2V are not permitted (see Table 7).
11
SUS
Suspend Mode Control Input. The SUS signal causes the S0 and S1 inputs to take precedence over the
VID code setting and OFS inputs. When SUS is high, the state of the S0 and S1 inputs are decoded to
select the appropriate DAC code and the offset is forced to zero (see the DAC Inputs and Internal
Multiplexer section).
12
DPSLP
Deep Sleep Control Input. This logic control input goes to the offset selection multiplexer that determines
which, if any, offset control inputs are read (OFS0–OFS2). This input is compatible with 1.5V logic (see
Table 7).
13
D0
3
7
8
9
10
20
NAME
VID Code Input. D0 is the least significant bit (LSB).
______________________________________________________________________________________
Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers
PIN
NAME
14
D1
VID Code Input
15
D2
VID Code Input
16
D3
VID Code Input
17
D4
VID Code Input. D4 is the most significant bit (MSB).
18
S0
Suspend Mode Voltage-Select Input. S0 and S1 are four-level logic inputs that select the suspend mode
VID code for the suspend mode multiplexer inputs. If SUS is high, the suspend mode VID code is delivered
to the DAC overriding any other voltage setting (see the DAC Inputs and Internal Multiplexer section).
19
S1
Suspend Mode Voltage-Select Input. S0 and S1 are four-level logic inputs that select the suspend mode
VID code for the suspend mode multiplexer inputs. If SUS is high, the suspend mode VID code is delivered
to the DAC overriding any other voltage setting (see the DAC Inputs and Internal Multiplexer section).
SKP1/SDN
Combined Shutdown and Skip-Mode Control Input for BUCK1. Always start BUCK2 before starting BUCK1.
Connect SKP1/SDN to VCC or drive the pin above 2.8V with external 3.3V-powered CMOS logic for normal
PFM/PWM operation. Connect SKP1/SDN to GND or drive the pin below 0.5V to shut down BUCK1. In
shutdown mode, DL1 is forced to VDD in order to enforce overvoltage protection when the regulator is
powered down. Leave SKP1/SDN floating for the low-noise forced PWM operation. Low-noise forced-PWM
mode causes the inductor current to reverse at light loads and suppresses pulse-skipping operation.
SKP1/SDN can also be used to disable both over- and undervoltage protection circuits and clear the fault
latch. This test mode is enabled by forcing the pin to 10.8V < VSKP1/SDN < 13.2V. While in the test mode,
the regulator performs the normal PFM/PWM operation. SKP1/SDN cannot withstand the battery voltage.
SKP2/SDN
Combined Shutdown and Skip-Mode Control Input for BUCK2. Always start BUCK2 before starting BUCK1.
Connect SKP2/SDN to VCC or drive the pin above 2.8V with external 3.3V-powered CMOS logic for normal
PFM/PWM operation. Connect SKP2/SDN to GND or drive the pin below 0.5V to shut down BUCK2. In
shutdown mode, DL2 is forced to VDD if the overvoltage protection is enabled. This is done in order to
enforce overvoltage protection even when the regulator is powered down. Leave SKP2/SDN floating for the
low-noise forced PWM operation. Low-noise forced-PWM mode causes the inductor current to recirculate
at light loads and suppresses pulse-skipping operation. If OVPSET = VCC, then DL2 is forced LOW in
shutdown mode. SKP2/SDN cannot withstand the battery voltage.
LIN/SDN
Linear Regulator Shutdown Control Input. Connect LIN/SDN to VCC or drive the pin above 2.4V to turn on
the linear regulator. Connect LIN/SDN to GND or drive the pin below 0.8V to shut down the linear regulator.
In shutdown mode, LINBSE is forced to a high-impedance state preventing sufficient drive to the external
PNP power transistor in the regulator. LIN/SDN cannot withstand the battery voltage.
PGOOD
Open-Drain Power-Good Output. PGOOD is forced low during power-up and power-down transitions on
BUCK1. In normal operation, if FBS and OUT2 (FB2) are in regulation, then PGOOD is high. PGOOD is
forced low when SKP1/SDN is low. If SKP2/SDN is low, OUT2 (FB2) does not affect PGOOD. Normally,
PGOOD is forced high for all VID transitions, and stays high for 4 TIME clock periods after the D/A count is
equalized. If OUT2 is enabled during these conditions and a fault occurs on BUCK2, then PGOOD goes
low. A pullup resistor on PGOOD causes additional finite shutdown current.
TON
On-Time Selection Control Input. This four-level input sets the K factor that determines the DH on-time. The
TON times for BUCK2 are shifted to minimize beating between the two regulators. GND = 1000kHz
(BUCK1) and 715kHz (BUCK2), REF = 550kHz (BUCK1) and 390kHz (BUCK2), open = 300kHz (BUCK1)
and 390kHz (BUCK2), VCC = 200kHz (BUCK1) and 260kHz (BUCK2).
20
21
22
23
24
FUNCTION
______________________________________________________________________________________
21
MAX1816/MAX1994
Pin Description (continued)
Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers
MAX1816/MAX1994
Pin Description (continued)
PIN
22
NAME
FUNCTION
25
OVPSET
Overvoltage Protection Control Input. This pin controls the OVP functions for BUCK1 and BUCK2. LINFB is
not affected by OVPSET. Connect OVPSET to VCC to disable overvoltage protection for both BUCK1 and
BUCK2. Connect OVPSET to GND for default overvoltage threshold of 2.0V (MAX1816) or 2.25V (MAX1994)
for BUCK1, measured at FBS. The OVP threshold for BUCK2 is always at 115% of the nominal output
voltage. The OVP threshold for BUCK1 can be adjusted by connecting OVPSET between 1.0V and 2.0V. An
overvoltage condition occurs if VFBS > VOVPSET (MAX1816) or VFBS > 1.125 × VOVPSET (MAX1994).
Undervoltage protection thresholds are always enabled and are not affected by this pin.
26
TIME
Slew Rate Adjustment Input. Connect a resistor from TIME to GND to set the internal slew-rate clock. A
680kΩ to 68kΩ resistor to GND sets the clock from 53kHz to 530kHz, fSLEW = 252kHz × (143kΩ / RTIME).
27
LINFB
Linear Regulator Feedback Input. The linear regulator’s feedback set point is 1.0V. Connect a resistive
voltage-divider from the collector of the external PNP pass transistor to LINFB. The DC bias current in the
voltage-divider should be greater than 10µA. The linear regulator is active whenever LIN/SDN is high.
Open-Drain Power-Good Output for the Linear Regulator. As soon as LINFB is in regulation, LINGOOD
goes high after a 1ms minimum delay. When the output goes out of regulation or LIN/SDN goes low,
LINGOOD is forced low within approximately 10µs. A pullup resistor on LINGOOD causes additional
shutdown current.
28
LINGOOD
29
LINBSE
Linear Regulator Base Drive. Connect LINBSE to the base of an external PNP power transistor. Add a 220Ω
pullup resistor between the base and the emitter.
30
AGND
Analog Ground. Connect the MAX1816/MAX1994s’ exposed backside pad and low-current ground
terminations to AGND. The current-limit comparator’s ground sense for BUCK2 also connects to AGND.
31
VCC
Analog Supply Voltage Input for BUCK1, BUCK2, and the Linear Regulator. This pin supplies all power to
the device except for the MOSFET drivers. The range for VCC is 4.5V to 5.5V. Bypass VCC to GND with a
minimum capacitance of 1µF. The maximum resistance between VCC and VDD should be 10Ω.
32
REF
2.0V Reference Output. Bypass REF to GND with a minimum capacitance of 0.22µF. The reference is
trimmed with a nominal 50µA load, and can source a total of 100µA for external loads. Loading REF greater
or less than 50µA decreases output-voltage accuracy according to the limits defined in the Electrical
Characteristics table.
33
FB2
Adjustable Feedback Input for BUCK2. In adjustable mode, FB2 regulates to 1.00V. It also selects default
voltage. Connect FB2 to GND for 2.5V output, or connect FB2 to VCC for 1.8V output.
34
OUT2
35
CS2
Output Voltage Connection for BUCK2. Connect directly to the junction of the output filter capacitors. OUT2
senses the output voltage to determine the on-time and also serve as the feedback input in fixed-output
modes.
Current-Sense Input for BUCK2. For accurate current limit, connect CS2 to a sense resistor between the
source of the low-side MOSFET and ground. Alternatively, CS2 can be connected to LX2 for lossless
current sensing across the low-side MOSFET. The current-limit sense voltage for CS2 is set at the ILIM2
36
ILIM2
BUCK2 Current-Limit Adjustment Input. The current-limit threshold measured between AGND and CS2
defaults to 50mV when ILIM2 is connected to VCC. In adjustable mode, the current-limit threshold voltage is
precisely 1/10th of the voltage at ILIM2. The logic threshold for switchover to the default value is
approximately VCC - 1V.
37
V+
Battery Voltage Sense Input. V+ is used only for PWM one-shot timing. DH1 and DH2 on-times are inversely
proportional to input voltage over a 2V to 28V range.
38
BST2
BUCK2 Boost Flying Capacitor Connection. An optional resistor in series with BST2 allows the DH1 pullup
current to be adjusted.
______________________________________________________________________________________
Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers
PIN
NAME
FUNCTION
39
LX2
40
DH2
BUCK2 Inductor Connection. LX2 is the internal lower supply rail for the DH2 high-side gate driver.
BUCK2 High-Side Gate-Driver Output. DH2 swings from LX2 to BST2.
41
DL2
BUCK2 Low-Side Gate-Driver Output. DL2 swings from PGND to VDD. DL2 is forced high when
MAX1816/MAX1994 detect an overvoltage fault. When the regulator powers down, DL2 is forced high if
OVP is enabled, and is forced low if OVP is disabled.
42
VDD
Supply Voltage Input for DL1 and DL2 Gate Drivers. Connect VDD to the system supply voltage (4.5V to
5.5V). Bypass VDD to PGND with a 2.2µF or greater ceramic capacitor.
43
PGND
44
DL1
45
PERF
46
DH1
BUCK1 High-Side Gate-Driver Output. DH1 swings from LX1 to BST1.
47
LX1
BUCK1 Inductor Connection. LX1 is the internal lower supply rail for the DH1 high-side gate driver.
48
BST1
Power Ground. Ground connection for low-side gate drivers DL1 and DL2.
BUCK1 Low-Side Gate-Driver Output. DL1 swings from PGND to VDD. DL1 is forced high when
MAX1816/MAX1994 detect an overvoltage fault. When the regulator powers down, DL1 is forced high.
Performance Mode Control Input. This logic-control input goes to the offset selection mux that determines
which, if any, offset control inputs are read (OFS0–OFS2). This input is compatible with 3.3V logic (see
Table 7).
BUCK1 Boost Flying Capacitor Connection. An optional resistor in series with BST1 allows the DH1 pullup
current to be adjusted.
Detailed Description
The MAX1816/MAX1994 are dual step-down controllers
for notebook computer applications. The controllers
include a CPU regulator (BUCK1) that features a
dynamically adjustable output with offset control and a
programmable suspend mode voltage. This regulator is
capable of delivering very large currents at the high
efficiencies needed for leading-edge CPU core applications. A second step-down regulator (BUCK2) is
included to generate I/O or memory supplies. Both regulators employ Maxim’s proprietary Quick-PWM control
architecture. A linear-regulator controller is also included for low-voltage auxiliary power supplies. All of the
regulators have independent shutdown control inputs.
The linear regulator includes a power-good output that
is independent of the combined power-good output for
BUCK1 and BUCK2.
5V Bias Supply (VCC and VDD)
The MAX1816/MAX1994 require an external 5V bias
supply in addition to the battery. Typically, this 5V bias
supply is the notebook computer’s 5V system supply.
Keeping the bias supply external to the IC improves efficiency and eliminates the cost associated with the 5V
linear regulator that would otherwise be needed to supply the PWM controllers and gate drivers of BUCK1 and
BUCK2. If stand-alone capability is needed, the 5V supply can be generated with an external linear regulator.
The 5V bias supply must provide VCC for the PWM controller’s internal reference, bias, and logic; and VDD for
the gate drivers. The maximum bias supply current is:
IBIAS = ICC + f (QG1 + QG2 + QG3 + QG4)
= 20mA to 80mA (typ)
where ICC is 2.2mA (typ), f is the switching frequency,
and QG1, QG2, QG3, and QG4 are the total gate charge
specifications at VGS = 5V in the MOSFET data sheets.
V+ and VDD can be connected if the input power source
is a fixed 4.5V to 5.5V supply. If the 5V bias supply is
powered up prior to the battery supply, the enable signals
(SKP_/SDN) must be delayed until the battery voltage is
present to ensure startup.
______________________________________________________________________________________
23
MAX1816/MAX1994
Pin Description (continued)
MAX1816/MAX1994
Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers
Table 1. Component Selection for Standard Applications
BUCK1 (CIRCUITS OF
FIGURES 1 AND 2)
COMPONENT
BUCK2 (CIRCUITS OF
FIGURES 1 AND 2)
SLAVE (CIRCUIT OF FIGURE 2)
Input Voltage Range
7V to 24V
7V to 24V
7V to 24V
Output Voltage
0.6V to 1.75V (MAX1816),
0.7V to 2.0V (MAX1994)
2.5V
0.6V to 1.75V (MAX1816),
0.7V to 2.0V (MAX1994)
Output Current
20A
7A
20A
Frequency
300kHz
300kHz
300kHz
High-Side MOSFET
(2) N-channel
International Rectifier IRF7811W
N-channel
International Rectifier IRF7811W
(2) N-channel
International Rectifier IRF7811W
Low-Side MOSFET
(2) N-channel
International Rectifier IRF7822
Fairchild FDS7764A
N-channel
International Rectifier IRF7822
Fairchild FDS7764A
(2) N-channel
International Rectifier IRF7822
Fairchild FDS7764A
Input Capacitor
(3) 10µF, 25V X5R ceramic
Taiyo Yuden TMK432BJ106KM
TDK C4532X5R1E106M
10µF, 25V X5R ceramic
Taiyo Yuden TMK432BJ106KM
TDK C4532X5R1E106M
(3) 10µF, 25V X5R ceramic
Taiyo Yuden TMK432BJ106KM
TDK C4532X5R1E106M
Output Capacitor
(3) 330µF, 2.5V, 10mΩ SP
Panasonic EEFUE0E331XR
(1) 330µF, 2.5V, 10mΩ SP
Panasonic EEFUE0E331XR
(3) 330µF, 2.5V, 10mΩ SP
Panasonic EEFUE0E331XR
Inductor
0.6µH
Panasonic ETQP6F0R6BFA
Toko EH125C-R60N
Sumida CDEP134H-0R6
1.2µH
Toko EH125C-1R2N
Sumida CDEP134H-1R2
Panasonic ETQP6F1R2BFA
0.6µH
Panasonic ETQP6F0R6BFA
Toko EH125C-R60N
Sumida CDEP134H-0R6
Current-Sense Resistor
1mΩ ±1%, 1W
Panasonic ERJM1WTJ1M0U
5mΩ ±1%, 1W
Panasonic ERJM1WSF5M0U
1mΩ ±1%, 1W
Panasonic ERJM1WTJ1M0U
Table 2. Component Suppliers
SUPPLIER
PHONE
WEBSITE
CAPACITORS
Panasonic
847-468-5624
Sanyo
619-661-6835
www.panasonic.com
www.sanyovideo.com
Taiyo Yuden
408-573-4150
www.t-yuden.com
TDK
847-803-6100
www. tdk.com
Panasonic
847-468-5624
www.panasonic.com
Sumida
408-982-9660
www.sumida.com
Fairchild Semiconductor
888-522-5372
www.fairchildsemi.com
International Rectifier
310-322-3331
www.irf.com
Siliconix
203-268-6261
www.vishay.com
INDUCTORS
MOSFETs
24
______________________________________________________________________________________
Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers
Both BUCK1 and BUCK2 employ Maxim’s proprietary
Quick-PWM control architecture. The control scheme is
a pseudo fixed-frequency, constant-on-time currentmode type with voltage feed forward (Figures 3, 4, and
5). It relies on the output ripple voltage to provide the
PWM ramp signal. This signal can come from the output filter capacitor’s ESR or a dedicated sense resistor.
The control algorithm is simple: the high-side switch ontime is determined solely by a one-shot whose period is
inversely proportional to input voltage and directly proportional to output voltage. Another one-shot sets a
minimum off-time (425ns, typ). The on-time one-shot is
triggered if the error comparator is low, the low-side
switch current is below the current-limit threshold, and
the minimum off-time one-shot has timed out.
On-Time One-Shot (TON)
The heart of the PWM core is the one-shot that sets the
high-side switch on-time (Figures 4 and 5). This fast,
low-jitter, adjustable one-shot includes circuitry that
varies the on-time in response to battery and output
voltages. The high-side switch on-time is inversely proportional to the battery voltage as measured by the V+
input, and proportional to the output voltage. This algorithm results in a nearly constant switching frequency
despite the lack of a fixed-frequency clock generator.
The benefits of a constant switching frequency are
twofold: first, the frequency can be selected to avoid
noise-sensitive regions such as the 455kHz IF band;
second, the inductor ripple-current operating point
remains relatively constant, resulting in easy design
methodology and predictable output-voltage ripple:
On-Time = K (VOUT + 0.075V) / VIN
The on-times for BUCK1 have nominal frequency settings of 200kHz, 300kHz, 550kHz, or 1000kHz, while the
on-times for BUCK2 are shifted to minimize beating
between the two regulators. The corresponding frequency settings for BUCK2 are 260kHz, 390kHz,
390kHz, and 715kHz. The BUCK2 on-times for TON =
open and TON = VCC are shifted down to improve the
efficiency. The BUCK2 on-times for TON = GND and
TON = REF are shifted up to avoid beating, yet maintain
the efficiency. The latter settings were not shifted down
because the resulting frequencies would be too high.
The on-time one-shot has good accuracy at the operating points specified in the Electrical Characteristics
(±10% at 200kHz and 300kHz, ±12.5% at 550kHz and
1000kHz for BUCK1). On-times at operating points far
removed from the conditions specified in the Electrical
Characteristics can vary over a wider range.
For example, the 1000kHz setting typically runs about
10% slower with inputs much greater than 5V due to the
very short on-times required.
On-times translate only roughly to switching frequencies.
The on-times guaranteed in the Electrical Characteristics
are influenced by switching delays in the external highside MOSFETs. Resistive losses, including the inductor,
both MOSFETs, output capacitor ESR, and PC board
copper losses tend to raise the switching frequency at
higher output currents. Also, the dead-time effect
increases the effective on-time, reducing the switching
frequency. It occurs only in PWM mode (SKP_/SDN =
open) and during dynamic output-voltage transitions
(BUCK1) when the inductor current reverses at light or
negative load currents. With reversed inductor current,
the inductor’s EMF causes LX to go high earlier than
normal, extending the on-time by a period equal to the
DH_ low-to-high dead time.
where K is set by the TON pin-strap connection and
0.075V is an approximation to accommodate for the
expected drop across the low-side MOSFET switch
(Table 3).
Table 3. Approximate K-Factor Errors
TON
BUCK1
K-FACTOR
(µs)
BUCK1
FREQUENCY
(kHz)
BUCK1
K-FACTOR ERROR
(%)
BUCK2
K-FACTOR
(µs)
BUCK2
FREQUENCY
(kHz)
BUCK2
K-FACTOR
ERROR (%)
±12.5
GND
1.0
1000
±12.5
1.4
715
Open
1.8
550
±12.5
2.56
390
±10
REF
3.3
300
±10
2.56
390
±10
VCC
5.0
200
±10
3.84
260
±10
______________________________________________________________________________________
25
MAX1816/MAX1994
Free-Running, Constant On-Time PWM
Controller with Input Feed-Forward
MAX1816/MAX1994
Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers
INPUT
7V TO 24V
5V BIAS
SUPPLY
V+
VDD
VCC
REF
REF
2V REF
SKP1/SDN
AGND
MAX1816
MAX1994
SKP2/SDN
LIN/SDN
LIN/SDN
BST1
BUCK1
DH1
VOUT1
DH1
V+
DAC
BITS
VOUT2
2.5V
LX2
VDD
REF
DL1
DH2
DH2
I_OFFSET
DAC
BITS
LX1
DL1
BST2
BUCK2
V+
I_OFFSET
REF
DL2
REF
DL2
PGND
TON1
TON1
GAIN
OVPEN
CS1-
FBS
GDS
FBS
GDS
ILIM1
CC
ILIM1
CS2
CS2
TON2
GAIN
CS1+
CS1+
CS1-
REF
TON2
OVPEN
OVPEN
SKP1/SDN
CC
PGOOD1
SKP2/SDN
OUT2
FB2
PGOOD2
ILIM2
OUT2
FB2
REF
ILIM2
P GOOD
DAC BITS
ON-TIME
SELECTOR
TON
N.C.
DAC
INPUTS
SUSPEND
INPUTS
TON1
TON1
TON2
TON2
S0-S1
2
5
PGOOD
5
VID MUX
D0–D4
MUX
OUT
D0-D4
5
FOUR-LEVEL
DECODE
REGISTER
PRESENT-STATE
DAC BITS
REGISTER
5
VID ROM
5
BITS
IN
BITS
OUT
X
5
VID0–VID4
X=Y
OSCILLATOR
Y
RTIME
DIGITAL
COMPARATOR
TIME
OSC OUT
SUS
CLOCK
UP/DOWN
COUNTER
SUS
PERF
CONTROL
INPUTS
DPSLP
SUS
X>Y
DOWN
OFS
PERF CONTROL
STATE
DPSLP MACHINE
X<Y
UP
DAC
BITS OUT
DAC BITS
LINGOOD
LINGOOD
OFS_SEL
3.3V
BIAS SUPPLY
OFFSET CONTROL
INPUT
OFFSET
CONTROL
FAULTLR
SEL
3
OFS0–OFS2
I_OFFSET
I_OFFSET
FAULT
THRESHOLD
CONTROL
LINBSE
LIN/SDN
0Ω
OVPSET
PGND
AGND
LINEAR
REG
LINFB
OVPSET
OVPEN
Figure 3. Functional Diagram
26
______________________________________________________________________________________
VLIN
Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers
MAX1816/MAX1994
V+
TO DH1 DRIVER
INPUT
OUT1
Q
ON-TIME
COMPUTE
TON1
TRIG
TOFF
Q ONE-SHOT
S
TON ONE-SHOT
TRIG
TO DL1 DRIVER
INPUT
Q
S
Q
R
Q
R
ZERO CROSSING
∑
ILIM1
8.6R1
ERROR
AMPLIFIER
∑
REF
0.4R1
70kΩ
CC
R1
10kΩ
GM
I_OFFSET
FBS
10kΩ
DAC
AMPLIFIER
10kΩ/AVPS
CS1+
CS110kΩ/AVPS
REF - 10%
10kΩ
GAINSTATE
DECODER
REF + 10%
R-2R
DAC
PGOOD1
I_GDS
OVP/UVP
DETECTOR
SKP1/SDN
ON/OFF
CONTROL
TIMER
OVPEN
GAIN
GND
GM
GDS
RESET
OUT
OVPEN
FBS
DAC BITS
Figure 4. BUCK1 PWM Control Diagram
For loads above the critical conduction point, where the
dead-time effect is no longer a factor, the actual switching frequency is:
f=
VOUT + VDROP1
t ON (VIN + VDROP2 )
where VDROP1 is the sum of the parasitic voltage drops
in the inductor discharge path, including synchronous
rectifier, inductor, and PC board resistances; VDROP2 is
the sum of the parasitic voltage drops in the inductor
charge path, including high-side switch, inductor, and
PC board resistances; and tON is the on-time calculated by the MAX1816/MAX1994.
______________________________________________________________________________________
27
MAX1816/MAX1994
Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers
V+
TO DH2 DRIVER
INPUT
OUT2
Q
TRIG
TOFF
Q ONE-SHOT
ON-TIME
COMPUTE
TON2
S
TON ONE-SHOT
TRIG
TO DL2 DRIVER
INPUT
Q
S
Q
R
Q
R
ZERO CROSSING
CS2
GND
ILIM2
∑
ERROR
AMPLIFIER
REF
OUT2
DUAL-MODE FEEDBACK MUX
FIXED 1.5V
REF - 10%
FIXED 1.8V
R
REF + 10%
R
FB2
PGOOD2
OVP/UVP
DETECTOR
SKP2/SDN
ON/OFF
CONTROL
TIMER
RESET
OUT
OVPEN
OVPEN
1V
2V
Figure 5. BUCK2 PWM Control Diagram
BUCK1 Integrator
BUCK1 includes a transconductance integrator (Figure
4) that provides a fine adjustment to the output regulation point. The integrator forces the DC average of the
feedback voltage to equal the VID DAC setting. The circuit has the ability to lower the output voltage by 3%
and raise it by 3%.
28
The differential input voltage range for the amplifier is at
least ±60mV total, including DC offset and AC ripple.
The integration time constant can be easily set with a
capacitor at the CC pin. Use a capacitance of 47pF to
1000pF (47pF typ). The transconductance of the amplifier is 80µS (typ).
______________________________________________________________________________________
Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers
The MAX1816/MAX1994 include differential remotesense inputs to eliminate the effect of voltage drops
down the PC board traces and through the processor’s
power leads. The FBS and GDS inputs enable true differential remote sense of the load voltage. The two inputs
measure the voltage directly across the load to provide a
signal that is summed with the feedback signals that set
the voltage-positioned output. Connect the feedback
sense input (FBS) directly to the positive load terminal
and connect the ground sense input (GDS) directly to
the negative load terminal. Modern microprocessors now
include dedicated V CC and ground-sense pins to
facilitate the measurement of the chip’s supply voltage.
BUCK1 Voltage-Positioning and
Current-Sense Inputs (CS1+, CS1-)
The CS1+ and CS1- pins are differential inputs that
measure the voltage drop across the sense resistor of
BUCK1 for current-limiting, zero-crossing detection and
active voltage positioning (Figure 4). The current-limit
threshold is adjusted with an external resistive voltagedivider at ILIM1. A 10µA (min) divider current is recommended. The current-limit threshold adjustment range
is from 25mV to 250mV. In adjustable mode, the current-limit threshold is precisely 1/10th of the voltage at
ILIM1. The default current limit is 50mV when ILIM1 is
connected to VCC. The logic threshold for switchover to
the default value is approximately VCC - 1V.The default
current limit accommodates the low voltage drop
expected across the sense resistor.
The current-limit circuit of BUCK1 employs a unique
“valley” current-sensing algorithm (Figure 6). If the
magnitude of the current-sense voltage between CS1+
and CS1- is above the current-limit threshold, the PWM
IPEAK
is not allowed to initiate a new cycle. The actual peak
current is greater than the current-limit threshold by an
amount equal to the inductor ripple current. Therefore,
the exact current-limit characteristic and maximum load
capability are a function of the sense resistance, inductor value, and battery voltage.
There is also a negative current limit that prevents
excessive reverse inductor currents when V OUT1 is
sinking current in PWM mode.
The negative current-limit threshold is set to approximately 140% of the positive current limit and therefore
tracks the positive current limit when ILIM1 is adjusted.
The GAIN pin controls the voltage-positioning gain. The
slope of the output voltage as a function of load current
is set by measuring the output current with a sense
resistor (RSENSE) in series with the inductor. An amplified version of this signal is fed back into the loop to
decrease the output voltage. The required offset is
added through the OFS0–OFS2 inputs (see the BUCK1
Output-Voltage Offset Control section). The exact relationship for the output of BUCK1 can be described with
the following equation:
VOUT1 = VSET - AVPS × (VCS1+ - VCS1-) + VOS × SF
where VSET is the programmed output voltage (see
Tables 5 and 6), VOS is the offset voltage generated
from the selected OFS_ pin, SF is a scale factor (0.125)
for the offset voltage, and AVPS is the differential voltage-positioning gain set with the GAIN pin.
Since VCS1+ - VCS1- = ILOAD × RSENSE, substituting the
differential sense voltage yields:
VOUT1 = VSET - AVPS × ILOAD × RSENSE + VOS × SF
The GAIN pin is a four-level logic input. When GAIN is
set to GND, REF, open, and VCC, the differential voltage gains are 0, 1.5, 2, and 4, respectively. Grounding
GAIN disables the voltage-positioning function but
does not disable the current limit.
BUCK2 Current-Sense Input (CS2)
INDUCTOR CURRENT
ILOAD
ILIMIT
0
TIME
BUCK2 uses the voltage at the CS2 pin to estimate the
inductor current and determine the zero crossing for
controlling pulse-skipping operation (Figure 5).
Connect CS2 to the current-sense resistor (Figure 1) for
the best possible current-limit accuracy. However, the
improved accuracy is achieved at the expense of the
additional power loss in the sense resistor. CS2 can be
connected to LX2 for lossless current sensing. In this
case, the trade-off is that the current limit becomes
dependent on the low-side MOSFET’s RDS(ON) with its
inherent inaccuracies and thermal drift.
Figure 6. “Valley” Current-Limit Threshold Point
______________________________________________________________________________________________________
29
MAX1816/MAX1994
BUCK1 Differential Remote-Sense
Amplifier (FBS, GDS)
MAX1816/MAX1994
Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers
Like BUCK1, the current-limit circuit of BUCK2 also
employs “valley” current sensing (Figure 6). If the magnitude of the current-sense voltage at CS2 is above the
current-limit threshold, the PWM is not allowed to initiate a
new cycle. The actual peak current is greater than the
current-limit threshold by an amount equal to the inductor
ripple current. Therefore, the exact current-limit characteristic and maximum load capability are a function of the
sense resistance, inductor value, and battery voltage.
There is also a negative current limit that prevents
excessive reverse inductor currents when V OUT2 is
sinking current in PWM mode. The negative currentlimit threshold is set to approximately 140% of the positive current limit and therefore tracks the positive
current limit when ILIM2 is adjusted.
The current-limit threshold is adjusted with an external
resistive voltage-divider at ILIM2. A 10µA (min) divider
current is recommended. The current-limit threshold
adjustment range is from 25mV to 250mV. In adjustable
mode, the current-limit threshold voltage is precisely
1/10th of the voltage at ILIM2. The threshold defaults to
50mV when ILIM2 is connected to V CC . The logic
threshold for switchover to the 50mV default value is
approximately V CC - 1V. The default current limit
accommodates the low voltage drop expected across
the sense resistor.
Carefully observe the PC board layout guidelines to
ensure that noise and DC errors do not corrupt the current-sense signal seen by CS2. Because CS2 is not a
real differential current-sense input, minimize the return
impedance from the sense resistor to the power ground
to reduce voltage errors when measuring the current.
In Figure 1, the Schottky diode (D2) provides a current
path parallel to the Q4/R2 current path. Accurate current sensing demands D2 to be off while Q4 conducts.
Avoid large current-sense voltages. The combined voltage across Q4 and R2 can cause D2 to conduct. If very
large sense voltages are used, connect D2 directly
from Q4’s source to drain.
Forced-PWM Mode
BUCK1 and BUCK2 operate in forced-PWM mode
when SKP1/SDN and SKP2/SDN are unconnected. The
low-noise forced-PWM mode disables the zero-crossing comparator, allowing the inductor current to reverse
at light loads. This causes the low-side gate-drive
waveform to become the complement of the high-side
gate-drive waveform. This in turn causes the inductor
current to reverse at light loads while DH_ maintains a
duty factor of VOUT_/VIN. The benefit of forced-PWM
mode is to keep the switching frequency fairly constant,
but it comes at a cost: the no-load 5V bias supply cur30
rent can be 20mA to 80mA total for both BUCK1 and
BUCK2, depending on the external MOSFETs and
switching frequency.
Forced-PWM mode is most useful for reducing audiofrequency noise, improving load-transient response,
providing sink-current capability for dynamic-output
voltage adjustment, and improving the cross-regulation
of multiple-output applications that use a flyback transformer or coupled inductor. BUCK1 uses PWM mode
during all output transitions, while the slew-rate controller is active and for 32 clock cycles thereafter.
Automatic Pulse-Skipping Mode
In skip mode (SKP_/SDN = high), an inherent automatic
switchover to PFM takes place at light loads. This
switchover is affected by a comparator that truncates
the low-side switch on-time at the inductor current’s
zero crossing. This mechanism causes the threshold
between pulse-skipping PFM and nonskipping PWM
operation to coincide with the boundary between continuous and discontinuous inductor-current operation
(also known as the “critical conduction” point).
In low duty-cycle applications, this threshold is relatively constant, with only a minor dependence on battery
voltage.
ILOAD _(SKIP) =
KVOUT _
2L _
×
VIN − VOUT _
VIN
where K is the on-time scale factor (Table 3). The load
current level at which PFM/PWM crossover occurs,
ILOAD(SKIP), is equal to 1/2 the peak-to-peak ripple current, which is a function of the inductor value (Figure 7).
For example, in the standard application circuit with K
= 3.3µs (Table 3), VOUT1 = 1.25V, VIN = 12V, and L1 =
0.68µH, switchover to pulse-skipping operation occurs
at ILOAD1 = 2.7A. The crossover point occurs at an
even lower value if a swinging (soft-saturation) inductor
is used.
The switching waveforms can appear noisy and asynchronous when light loading causes pulse-skipping
operation, but this is a normal operating condition that
results in high light-load efficiency. Trade-offs in PFM
noise vs. light-load efficiency are made by varying the
inductor value. Generally, low inductor values produce
a broader efficiency vs. load curve, while higher values
result in higher full-load efficiency (assuming that the
coil resistance remains fixed) and less output voltage
ripple. Penalties for using higher inductor values
include larger physical size and degraded load-transient response, especially at low-input-voltage levels.
______________________________________________________________________________________
Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers
The 1ms (min) LINGOOD delay is necessary to allow
the PLLs in the CPU to power up and stabilize before
turning on the main regulator. The delay time is computed based on 1024 RTIME clock cycles. As such, the
delay varies based on the RTIME period.
INDUCTOR CURRENT
IPEAK
MOSFET Gate Drivers (DH_, DL_)
ILOAD = IPEAK/2
0
ON-TIME
TIME
Figure 7. Pulse-Skipping/Discontinuous Crossover Point
DC output accuracy specifications for BUCK2 refer to
the threshold of the error comparator. When the inductor is in continuous conduction, BUCK2 output voltage
has a DC regulation level higher than the trip level by
50% of the ripple. In discontinuous conduction
(SKP2/SDN = high, light-loaded), BUCK2 output voltage has a DC regulation level higher than the errorcomparator threshold by approximately 1.5% due to
slope compensation.
Note that BUCK1 automatically enters forced-PWM
mode during all output voltage transitions and stays in
forced-PWM mode until the transition is completed and
for 32 clock cycles thereafter. The reason for that is the
forced-PWM operation provides current sinking capability required during output-voltage transitions.
Linear-Regulator Controller
The linear-regulator controller of the MAX1816/MAX1994
is an analog gain block with an open-drain N-channel
output. It drives an external PNP pass transistor with a
220Ω base-to-emitter resistor (Figure 1). The controller
is guaranteed to provide at least 20mA sink current. The
linear regulator is typically used to provide a
1.2V/500mA VID logic supply. The controller is designed
to be stable with an output capacitor of 10µF or more.
The output voltage can be adjusted with a resistive voltage-divider between the linear regulator output and
analog ground with the center tap connected to LINFB.
The set point of LINFB is 1.0V. The regulator is enabled
when LIN/SDN is high. As soon as LINFB is in regulation, the open-drain power-good output LINGOOD goes
high after a 1ms (min) delay. When the output goes out
of regulation or LIN/SDN goes low, LINGOOD is forced
low within approximately 10µs.
The DH_ and DL_ drivers are optimized for driving moderate-sized high-side and larger low-side power
MOSFETs. This is consistent with the low duty factor
seen in the notebook CPU environment, where a large
VIN - VOUT_ differential exists. Two adaptive dead-time
circuits monitor the DH_ and DL_ outputs and prevent
the opposite side FET from turning on until DL_ or DH_ is
fully off. There must be a low-resistance, low-inductance
path from the DL_ and DH_ drivers to the MOSFET gates
for the adaptive dead-time circuits to work properly.
Otherwise, the sense circuitry in the MAX1816/MAX1994
interprets the MOSFET gate as “off” while there is actually still charge left on the gate. Use very short, wide traces
measuring 10 to 20 squares (50 mils to 100 mils wide if
the MOSFET is 1in from the MAX1816/MAX1994).
The internal pulldown transistor that drives DL_ low is
robust, with a very low pulldown resistance. For DL1,
this resistance is 0.35Ω (typ), while the resistance for
DL2 is slightly higher at 0.7Ω (typ). This helps prevent
DL_ from being pulled up during the fast rise-time of
the inductor node, due to capacitive coupling from the
drain to the gate of the low-side synchronous-rectifier
MOSFET. However, for high-current applications, some
combinations of high- and low-side FETs can cause
excessive gate-drain coupling, which can lead to efficiency-killing, EMI-producing shoot-through currents.
This is often remedied by adding a resistor in series
with BST_, which increases the turn-on time of the highside FET without degrading the turn-off time (Figure 8).
+5V
VBATT
LX_
5Ω TYP
DH_
BST_
MAX1816
MAX1994
Figure 8. Reducing the Switching-Node Rise Time
______________________________________________________________________________________
31
MAX1816/MAX1994
∆i
VBATT - VOUT
=
∆t
L
MAX1816/MAX1994
Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers
Shutdown Control (SKP1/SDN,
SKP2/SDN, and LIN/SDN)
If BUCK2 is used, always start BUCK2 before starting
BUCK1. When SKP1/SDN goes below 0.5V, BUCK1
enters low-power shutdown mode. PGOOD goes low
immediately. The output voltage ramps down to zero in
25mV steps at the clock rate set by RTIME. Thirty-two
clocks after the DAC reaches the zero setting, DL1 is
forced to VDD, and DH1 is forced low. When SKP1/SDN
goes above 1.4V or floats, the DAC target is evaluated
and switching begins. The slew-rate controller ramps
up from zero in 25mV steps to the selected DAC code
value. There is no traditional soft-start (variable currentlimit) circuitry, so full output current is available immediately. Floating SKP1/SDN causes BUCK1 to operate in
low-noise forced-PWM mode. Forcing SKP1/SDN
above 2.8V enables skip mode operation.
When SKP2/SDN goes below 0.5V, BUCK2 enters shutdown mode. In shutdown mode, DL2 is forced to VDD if
overvoltage protection is enabled. If OVPSET is connected to VCC, overvoltage protection is disabled and
DL2 is forced low in shutdown mode.
When LIN/SDN goes below 0.8V, the linear regulator of
the MAX1816/MAX1994 enters shutdown mode. In
shutdown mode, LINBSE is forced to a high-impedance
state preventing sufficient drive to the external PNP
pass transistor in the regulator. LINGOOD is forced low
within 10µs (typ) when LIN/SDN goes low. Forcing
LIN/SDN above 2.4V turns on the linear regulator.
Power-On Reset
Power-on reset (POR) occurs when VCC rises above
approximately 2V, resetting the fault latch and preparing
the MAX1816/MAX1994 for operation. VCC undervoltage
lockout (UVLO) circuitry inhibits switching, forces
PGOOD low, and forces the DL1 gate driver high (to
enforce output overvoltage protection). The DL2 gate
driver is also forced high if OVP is enabled. When VCC
rises above 4.25V, the DAC inputs are sampled and the
output voltage begins to slew to the DAC setting. For
automatic startup, the battery voltage should be present
before VCC. If the MAX1816/MAX1994 attempt to bring
the output into regulation without the battery voltage
present, the fault latch will trip. Toggling any of the shutdown control pins resets the fault latch.
Power Valid Outputs
(PGOOD and LINGOOD)
PGOOD is an open-drain power-good output. Table 4
describes the behavior of PGOOD with respect to the
logic inputs. Window comparators on FBS and OUT2
(FB2) control the PGOOD output. If BUCK1 and BUCK2
are in regulation then PGOOD is high, except during
power-up and power-down.
32
The PGOOD output goes low if FBS or OUT2 (FB2) is
outside a window of ±10% about the nominal set point
(see the DAC Inputs and Internal Multiplexers and
Adjusting BUCK2 Output Voltage sections).
PGOOD is forced low when SKP1/SDN is low. If
SKP2/SDN is low, then OUT2 (FB2) does not affect
PGOOD. Normally, PGOOD is forced high during all
VID transitions, and stays high for 4 clock periods after
the DAC count is equalized. If BUCK2 goes out of regulation during these conditions, then PGOOD goes low
as a consequence. A pullup resistor on PGOOD causes additional finite shutdown current.
The following conditions must all be met for PGOOD to
go high:
• VCC must be above UVLO.
•
SKP1/SDN must be greater than 1.4V or unconnected.
•
The output of BUCK1 must be within a window of
±10% about the nominal set point.
•
PGOOD is forced high during DAC code transitions
of BUCK1. The “blanking” period persists for N+4
RTIME clock cycles. Blanking does not occur during
power-up and power-down.
•
If SKP2/SDN is not low, then OUT2 (FB2) must be
within a window of ±10% about the nominal set point.
•
When enabled, a fault on OUT2 overrides the blanking on BUCK1.
LINGOOD is an open-drain power-good output for the
linear regulator. LINGOOD goes high at least 1ms after
the internal comparator signals that the output is in regulation. In normal operation, if the internal comparator
signals that the circuit is out of regulation, LINGOOD
goes low within approximately 10µs (typ). If LIN/SDN
goes low, LINGOOD is immediately forced low.
Note that all three regulators are forced off when a fault is
detected. DL_ are forced high, DH_ are forced low, and
the linear regulator is turned off. (See the Output
Overvoltage Protection, Output Undervoltage Protection,
UVLO, and Thermal Fault Protection sections).
DAC Inputs and Internal
Multiplexers (SUS)
The MAX1816/MAX1994 have a unique internal VID input
multiplexer (mux) that can select one of two different VID
DAC code settings for different processor states. When
the logic level at SUS is low, the mux selects the VID DAC
code settings from the D0–D4 inputs (Table 5). Do not
leave D0–D4 floating—use 100kΩ pullup resistors if the
inputs float. When SUS is high, the suspend mode mux
selects the VID DAC code settings from the S0/S1 input
decoder. The outputs of the decoder are determined by
______________________________________________________________________________________
Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers
MAX1816/MAX1994
Table 4. BUCK1 and BUCK2 Operating Mode Truth Table
OVP
SKP1/SDN SKP2/SDN
DL1
DL2
MODE
PGOOD
X
GND
VCC
HIGH
Switching
BUCK2
LOW
Enabled
VCC
GND
Switching
HIGH
BUCK1
Monitor BUCK1 only
Disabled
VCC
GND
Switching
LOW
BUCK1
Monitor BUCK1 only
Enabled
GND
GND
HIGH
HIGH
Shutdown
LOW
Disabled
GND
GND
HIGH
LOW
Shutdown
LOW
X
VCC
VCC
Switching
Switching
Both in skip mode
Monitor both
Enabled
>10.8V
GND
Switching
HIGH
BUCK1 no-fault test mode
Monitor BUCK1 only
Disabled
>10.8V
GND
Switching
LOW
BUCK1 no-fault test mode
Monitor BUCK1 only
X
>10.8V
VCC
Switching
Switching
No-fault test mode
Monitor both
X
>10.8V
Float
Switching
Switching in
forced PWM
mode
No-fault test mode
Monitor both
Enabled
Float
GND
Switching in
forced PWM
mode
HIGH
BUCK1 in forced PWM
mode
Monitor BUCK1 only
Disabled
Float
GND
Switching in
forced PWM
mode
LOW
BUCK1 in forced PWM
mode
Monitor BUCK1 only
X
Float
VCC
Switching in
forced PWM
mode
Switching
BUCK1 in forced PWM
mode, BUCK2 in skip
mode
Monitor both
X
Float
Float
Switching in
forced PWM
mode
Switching in
forced PWM
mode
BUCK1 and BUCK2 in
forced PWM Mode
Monitor both
X
GND
Float
HIGH
Switching in
forced PWM
mode
BUCK1 off, BUCK in
forced PWM mode
LOW
X
VCC
Float
Switching
Switching in
forced PWM
mode
BUCK1 in skip mode,
BUVK2 in forced PWM
mode
Monitor both
Enabled
VCC or
float
VCC or
float
HIGH
HIGH
OVP and UVP faults
LOW
Disabled
VCC or
float
VCC or
float
HIGH
HIGH
UVP faults only
LOW
X = Don’t care.
inputs S0 and S1, which are four-level digital inputs
(Table 6). All code transitions (even those asking for the
exact same code) activate the slew-rate controller. In
other words, up-going or down-going transitions from one
code to another, soft-start and soft-stop are all handled in
the same way.
BUCK1 Output-Voltage Offset Control
(SUS, PERF, DPSLP, and OFS_)
The MAX1816/MAX1994 support three independent offsets to the voltage-positioned load line. The offsets are
adjusted using resistive voltage-dividers at the
OFS0–OFS2 inputs (see Figure 10). For inputs from 0 to
0.8V, a negative offset is added to the output that is
______________________________________________________________________________________
33
MAX1816/MAX1994
Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers
Table 5. Output Voltage vs. DAC Codes
D4
D3
D2
D1
D0
VOUT (V)
MAX1816
VOUT (V)
MAX1994
0
0
0
0
0
1.750
2.000
0
0
0
0
1
1.700
0
0
0
1
0
1.650
0
0
0
1
1
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
Table 6. Output Voltage vs. Suspend
Mode DAC Codes
S1
S0
VOUT (V)
MAX1816/MAX1994
1.950
GND
GND
1.075
1.900
GND
REF
1.050
1.600
1.850
GND
OPEN
1.025
0
1.550
1.800
GND
VCC
1.000
1
1.500
1.750
REF
GND
0.975
1
0
1.450
1.700
REF
REF
0.950
1
1
1
1.400
1.650
REF
OPEN
0.925
0
0
0
1.350
1.600
REF
VCC
0.900
1
0
0
1
1.300
1.550
OPEN
GND
0.875
0
1
0
1
0
1.250
1.500
OPEN
REF
0.850
0
1
0
1
1
1.200
1.450
OPEN
OPEN
0.825
0
1
1
0
0
1.150
1.400
OPEN
VCC
0.800
0
1
1
0
1
1.100
1.350
VCC
GND
0.775
0
1
1
1
0
1.050
1.300
VCC
REF
0.750
0
1
1
1
1
1.000
No CPU
VCC
OPEN
0.725
1
0
0
0
0
0.975
1.275
VCC
VCC
0.700
1
0
0
0
1
0.950
1.250
1
0
0
1
0
0.925
1.225
1
0
0
1
1
0.900
1.200
1
0
1
0
0
0.875
1.175
1
0
1
0
1
0.850
1.150
1
0
1
1
0
0.825
1.125
1
0
1
1
1
0.800
1.100
1
1
0
0
0
0.775
1.075
1
1
0
0
1
0.750
1.050
1
1
0
1
0
0.725
1.025
BUCK1 Output-Voltage Transition Timing
1
1
0
1
1
0.700
1.000
1
1
1
0
0
0.675
0.975
1
1
1
0
1
0.650
0.950
1
1
1
1
0
0.625
0.925
1
1
1
1
1
0.600
No CPU
The MAX1816/MAX1994 are designed to perform output voltage transitions in a controlled manner, automatically minimizing input surge currents. This feature
allows the regulator to perform nearly ideal transitions,
guaranteeing just-in-time arrival at the new output voltage level with the lowest possible peak currents for a
given output capacitance.
equal to 1/8th the voltage appearing at the selected
OFS input (∆VOUT = -0.125 × VOFS_). For inputs from
1.2V to 2V, a positive offset is added to the output that
is equal to 1/8th the difference between the reference
voltage and the voltage appearing at the selected OFS
input (∆V OUT = 0.125 × (V REF - V OFS_ )). With this
scheme, both positive and negative offsets can be
achieved with a single voltage-divider. The piecewise
linear transfer function is shown in Figure 9.
34
The regions of the transfer function below zero, above
2.0V, and between 0.8V and 1.2V are undefined. OFS
inputs are disallowed in these regions, and the respective effects on the output are not specified.
The offset control inputs are selected using a combination of the three logic inputs (SUS, PERF, and DPSLP),
which also define the operating mode for the
MAX1816/MAX1994. Table 7 details which OFS input is
selected based on these control inputs.
Modern mobile CPUs operate at multiple clock frequencies that require multiple VID settings. It is common
when transitioning from one clock frequency to another
for the CPU to go into a low-power state before changing the output voltage and clock frequency. The change
must be accomplished within a fixed time interval—often
less than 100µs.
______________________________________________________________________________________
Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers
OUTPUT OFFSET VOLTAGE (V)
0.15
0.10
0.05
0
-0.05
-0.10
 1 
VOLD − VNEW
t SLEW ≤ 4 µs + 
1 +

f
25mV
 SLEW
-0.15
0
0.5
0.8 1.0 1.2
1.5
2.0
OFS_ INPUT VOLTAGE (V)
Figure 9. Offset-Control Transfer Function
REF OR VOUT1
REF OR VOUT1
OFS0



where fSLEW = 252kHz × 143kΩ / RTIME, VOLD is the
original DAC setting, and VNEW is the new DAC setting.
See Time Frequency Accuracy in the Electrical
Characteristics table for fSLEW accuracy. The practical
range of RTIME is 68kΩ to 680kΩ, corresponding to
1.9µs to 19µs per 25mV step. Although the DAC takes
discrete 25mV steps, the output filter makes the transitions relatively smooth. The average inductor current
required to make an output voltage transition is:
IL ≅ COUT ✕ 25mV ✕ fSLEW
OFS0
OFS1
OR
OFS1
OFS1
OFS2
The slew-rate controller also performs a soft-start and
soft-stop function. The soft-start function works by
counting up from zero, in order to minimize turn-on
surge currents. The soft-stop executes this process in
reverse, eliminating the negative output voltages and
the need for an external Schottky output clamp diode
that would otherwise be required if DL1 were simply
forced high.
Setting BUCK2 Output Voltage
Figure 10. Simplified Offset-Control Circuits
At the beginning of an output voltage transition, the regulator is placed in forced-PWM mode and the PGOOD
output is high. If there is a fault on BUCK2 during this
period, PGOOD goes low. The output voltage follows the
internal DAC code, which changes in 25mV increments
until it reaches the programmed VID code. The regulator
remains in forced-PWM mode for 32 clock cycles after
the transition to ensure that the output settles properly.
The PGOOD output is forced high for 4 clock cycles after
the transition also to allow the output to settle. The slewrate clock frequency (set by the RTIME resistor) must be
set fast enough to ensure that the longest transition is
completed within the allotted time interval.
BUCK2’s Dual Mode™ operation allows the selection of
common voltages without requiring external components (Figure 1). In fixed mode, connect FB2 to AGND
for 2.5V output, or connect FB2 to VCC for 1.8V output.
In adjustable mode, the output voltage can be adjusted
from 1.0V to 5.5V using a resistive voltage-divider from
the BUCK2 output to AGND with the center tap connected to FB2 (Figure 11). The equation for adjusting
the output voltage is:
 R1 
VOUT2 = VFB2 1+ 
 R2 
where VFB2 is 1.0V.
Dual Mode is a trademark of Maxim Integrated Products, Inc.
______________________________________________________________________________________
35
MAX1816/MAX1994
The output voltage transition is performed in 25mV steps,
preceded by a 4µs delay and followed by one additional
clock period. The total time for a transition depends on
RTIME, the voltage difference, and the accuracy of the
MAX1816/MAX1994s’ slew-rate clock, and is not dependent on the total output capacitance. The greater the output capacitance, the higher the surge current required
for the transition. The MAX1816/MAX1994 automatically
control the current to the minimum level required to complete the transition in the calculated time. As long as the
surge current is less than the current limit set by ILIM1,
the transition time is given by:
UNDEFINED
MAX1816/MAX1994
Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers
Table 7. Offset Selection Truth Table
INPUTS
MODE
ACTIVE OFS INPUTS
SUS
PERF
DPSLP
OFS2
OFS1
Battery Sleep
0
0
0
1
0
0
Battery
0
0
1
0
1
0
Performance Sleep
0
1
0
0
0
1
Performance
0
1
1
0
0
0
Suspend
1
0
0
0
0
0
Suspend
1
0
1
0
0
0
Suspend
1
1
0
0
0
0
Suspend
1
1
1
0
0
0
OFS0
0 = Logic low or input not selected.
1 = Logic high or input selected.
Output Overvoltage Protection
Output overvoltage protection (OVP) is available on
BUCK1, BUCK2, and the linear regulator. The LINFB
input is always monitored for overvoltage. The FBS and
OUT2 inputs are only monitored for overvoltages when
OVP is enabled. When any output exceeds the desired
OVP threshold, the fault latch is set and the regulator is
turned off. In the fault mode, DL1 and DL2 are forced
high, DH1 and DH2 are forced low, and the linear regulator is turned off. For BUCK1 and BUCK2, if the condition that caused the overvoltage (such as a shorted
high-side MOSFET) persists, the battery fuse will blow.
DL1 is also kept high continuously when VCC UVLO is
active, as well as in shutdown mode (Table 4). The
device remains in the fault mode until VCC is cycled, or
either SKP_/SDN or LIN/SDN is toggled. The triggering
of the reset condition occurs on the rising edge of the
SKP_/SDN or LIN/SDN signals.
For BUCK1, the default OVP threshold is 2V for the
MAX1816 and 2.25V for the MAX1994. For BUCK2, the
OVP threshold is 115% of the nominal voltage for OUT2
(FB2 if external feedback is used for BUCK2). The overvoltage detection level for FBS can be adjusted through
an external resistive voltage-divider. Connecting OVPSET
to a voltage between 1.0V and 2.0V sets the OVP threshold for FBS. For the MAX1816, the fault latch is set when
VFBS > VOVPSET. For the MAX1994, the fault latch is set
when VFBS > 1.125 ✕ VOVPSET. The OVP threshold on
OUT2 is not adjustable and remains at the default value
of 115%. Connecting OVPSET to VCC disables OVP for
BUCK1 and BUCK2. The operation of the linear regulator
is not affected by OVPSET. Overvoltage protection can
be disabled using the NO FAULT test mode (see the NO
FAULT Test Mode section).
36
VBATT
DH2
MAX1816
MAX1994
VOUT
DL2
CS2
OUT2
R1
FB2
R2
PGND
AGND
Figure 11. Adjusting BUCK2 Output Voltage with a Resistive
Voltage-Divider
Output Undervoltage Protection
The output undervoltage protection (UVP) is available on
BUCK1, BUCK2, and the linear regulator. The protection
is similar to foldback current limiting, but employs a timer
rather than a variable current limit. If the output voltage is
under 70% of the nominal value for BUCK1 and BUCK2,
and under 90% for the linear regulator (see the Electrical
Characteristics table for the respective UVP thresholds),
the fault latch is set. In the fault mode, DL1 and DL2 are
forced high, DH1 and DH2 are forced low, and the linear
regulator is turned off. The controller does not restart until
VCC power is cycled, or either SKP_/SDN or LIN/SDN is
toggled. The triggering of the reset condition occurs on
the rising edge of the SKP_/SDN or LIN/SDN signals.
______________________________________________________________________________________
Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers
UVLO
The MAX1816/MAX1994 provide input undervoltage lockout (UVLO) protection. If the VCC voltage drops low
enough to trip the UVLO comparator, it is assumed that
there is not enough supply voltage to make valid decisions. In order to protect the output from overvoltage
faults, DL1 and DL2 are forced high if OVP is enabled,
DH_ is forced low, and the linear regulator is turned off. If
OVP is disabled, DL1 is forced high, DL2 is forced low,
DH_ is forced low, and the linear regulator is turned off.
For BUCK1 (and also for BUCK2 if OVP is enabled), this
condition rapidly forces the outputs to zero since the
slew-rate controller is not active. The fault results in large
negative inductor currents and possibly small negative
output voltages. If VCC is likely to drop in this fashion, the
outputs can be clamped with Schottky diodes to PGND to
reduce the negative excursions.
Thermal Fault Protection
The MAX1816/MAX1994 feature a thermal fault-protection circuit. When the junction temperature rises above
+160°C, a thermal sensor sets the fault latch, which
pulls DL_ high, DH_ low, and turns off the linear regulator. The device remains in fault mode until the junction
temperature cools by 15°C, and either VCC power is
cycled, or SKP_/SDN or LIN/SDN is toggled.
NO FAULT Test Mode
The over/undervoltage protection features can complicate the process of debugging prototype breadboards
since there are (at most) a few milliseconds in which to
determine what went wrong. Therefore, a test mode is
provided to disable the OVP, UVP, and thermal shutdown features, and clear the fault latch if it has been
set. Test mode applies to BUCK1, BUCK2, and the linear regulator. In the test mode, BUCK1 operates as if
SKP1/SDN was high (skip mode). Set the voltage on
SKP1/SDN between 10.8V to 13.2V to enable the NO
FAULT test mode.
BUCK1/BUCK2
Design Procedure
Firmly establish the input voltage range and maximum
load current for BUCK1 and BUCK2 before choosing a
switching frequency and inductor operating point (ripple-current ratio). The primary design trade-off lies in
choosing a good switching frequency and inductor
operating point, and the following four factors dictate
the rest of the design:
1) Input Voltage Range. The maximum value
(VIN(MAX)) must accommodate the worst-case high
AC adapter voltage. The minimum value (VIN(MIN))
must account for the lowest battery voltage after
drops due to connectors, fuses, and battery selector switches. If there is a choice, lower input voltages result in better efficiency.
2) Maximum Load Current. There are two values to
consider. The peak load current (ILOAD(MAX)) determines the instantaneous component stresses and
filtering requirements, and thus drives output
capacitor selection, inductor saturation rating, and
the design of the current-limit circuit. The continuous load current (ILOAD) determines the thermal
stresses and thus drives the selection of input
capacitors, MOSFETs, and other critical heat-contributing components. Modern notebook CPUs generally exhibit ILOAD = ILOAD(MAX) ✕ 80%.
3) Switching Frequency. This choice determines the
basic trade-off between size and efficiency. The
optimal frequency is largely a function of maximum
input voltage, due to MOSFET switching losses that
are proportional to frequency and VIN. The optimum
frequency is also a moving target, due to rapid
improvements in MOSFET technology that are making higher frequencies more practical.
4) Inductor Operating Point. This choice provides
tradeoffs between size and efficiency. Low inductor
values cause large ripple currents, resulting in the
smallest size, but poor efficiency and high output
noise. The minimum practical inductor value is one
that causes the circuit to operate at the edge of critical conduction (where the inductor current just
touches zero with every cycle at maximum load).
Inductor values lower than this grant no further sizereduction benefit. The MAX1816/MAX1994s’ pulseskipping algorithm initiates skip mode at the critical
conduction point. So, the inductor operating point
also determines the load current value at which
PFM/PWM switchover occurs. The optimum point is
usually found between 20% and 50% ripple current.
______________________________________________________________________________________
37
MAX1816/MAX1994
To allow startup, UVP is ignored during the undervoltage
blanking time (the first 256 cycles of the slew rate after
startup for BUCK1, the first 4096 cycles for BUCK2 and
the first 512 cycles for the linear regulator). UVP can be
disabled using the NO FAULT test mode (see the NO
FAULT Test Mode section).
MAX1816/MAX1994
Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers
5) Inductor Ripple Current. The inductor ripple current also impacts transient response performance,
especially at low VIN - VOUT differentials. Low inductor values allow the inductor current to slew faster,
replenishing charge removed from the output filter
capacitors by a sudden load step. The amount of
output sag is also a function of the maximum duty
factor, which can be calculated from the on-time
and minimum off-time:
 V

(ILOAD1 − ILOAD2 )2 × L ×  K OUT + t OFF(MIN) 
V


IN
VSAG =
  VIN − VOUT 

− t OFF(MIN) 
2 × COUT × VOUT × K

VIN

 

where t OFF(MIN) is the minimum off-time (see the
Electrical Characteristics table) and K is from Table 3.
Inductor Selection
The switching frequency and operating point (% ripple
current or LIR) determine the inductor value as follows:
L=
VOUT × (VIN − VOUT )
VIN × fSW × LIR × ILOAD(MAX)
Example: ILOAD(MAX) = 19A, VIN = 7V, VOUT = 1.25V,
fSW = 300kHz, 30% ripple current or LIR = 0.30:
L=
1.25V × (7V − 1.25V)
= 0.60µH
7V × 300kHz × 0.30 × 19A
Find a low-loss inductor having the lowest possible DC
resistance that fits in the allotted dimensions. Ferrite
cores are often the best choice, although powdered iron
is inexpensive and can work well at 200kHz. The core
must be large enough not to saturate at the peak inductor current (IPEAK):
 LIR 
IPEAK = ILOAD(MAX) × 1+

2 

Setting the Current Limit for BUCK1
Connect ILIM1 to VCC for a default 50mV (CS1+ to CS1-)
current-limit threshold. For an adjustable threshold, connect a resistive voltage-divider from REF to GND, with
ILIM1 connected to the center tap. The current-limit
threshold is precisely 1/10th of the voltage at ILIM1. When
adjusting the current limit, use 1% tolerance resistors for
the divider and a 10µA divider current to prevent a significant increase of errors in the current-limit threshold.
38
The minimum current-limit threshold must be great
enough to support the maximum load current when the
current limit is at the minimum tolerance value. The valley of the inductor current occurs at ILOAD(MAX) minus
half of the ripple current; therefore:
 LIR 
ILIMIT(MIN) > ILOAD(MAX) × 1−


2 
The current-sense resistor value (R1 in Figure 1) is calculated according to the worst-case (minimum) currentlimit threshold voltage (see the Electrical Characteristics
table) and the valley current-limit threshold ILIMIT(MIN)
described above:
RSENSE =
50mV × 0.8
ILIMIT(MIN)
(Fixed Mode)
× 0.1 × 0.8
V
(Adjustable Mode)
RSENSE = ILIM1
ILIMIT(MIN)
where 0.8 is a factor for the worst-case low current-limit
threshold.
To protect against component damage during short-circuit conditions, use the calculated value of RSENSE to
size the MOSFET switches and specify inductor saturation-current ratings according to the worst-case high
current-limit threshold:
IPEAK (MAX) =
50mV × 1.2
× (1 + LIR)
RSENSE
(Fixed Mode)
× 0.1 × 1.2
V
× (1 + LIR)
IPEAK (MAX) = ILIM1
RSENSE
(Adjustable Mode)
where 1.2 is a factor for worst-case high current-limit
threshold.
Low-inductance resistors, such as surface-mount metal
film, are recommended.
Setting the Current Limit for BUCK2
Connect ILIM2 to VCC for a default 50mV CS2 to GND
current-limit threshold. For an adjustable threshold,
connect a resistive voltage-divider from REF to GND,
with ILIM2 connected to the center tap. The currentlimit threshold is precisely 1/10th of the voltage at
ILIM2. When adjusting the current limit, use 1% tolerance resistors for the divider and a 10µA divider current to prevent a significant increase of errors in the
current-limit threshold.
______________________________________________________________________________________
Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers
 LIR 
ILIMIT(MIN) > ILOAD(MAX) × 1−


2 
where I LIMIT(MIN) equals the minimum current-limit
threshold voltage divided by the current-sense resistor.
The sense resistor (R2 in Figure 1) determines the achievable current-limit accuracy. There is a trade-off between
current-limit accuracy and sense-resistor power dissipation. Most applications employ a current-sense voltage of
50mV to 100mV. Choose a sense resistor so that:
RSENSE =
RSENSE =
50mV × 0.8
(Fixed Mode)
ILIMIT(MIN)
VILIM 2 × 0.1 × 0.8
(Adjustable Mode)
ILIMIT(MIN)
where 0.8 is a factor for worst-case low current-limit
threshold.
Extremely cost-sensitive applications that do not require
high-accuracy current sensing can use the on-resistance of the low-side MOSFET switch in place of the
sense resistor by connecting CS2 to LX2. Use the worstcase maximum value for RDS(ON) from the MOSFET
data sheet taking into account the rise in RDS(ON) with
temperature. A good general rule is to allow 0.5% additional resistance for each °C temperature rise.
Assume the current-sense resistor in the application circuit in Figure 1 is removed and CS2 is directly tied to
LX2. The Q4 maximum RDS(ON) = 3.8mΩ at TJ = +25°C
and 5.7mΩ at TJ = +125°C.
The minimum current-limit threshold is:
500mV × 0.1× 0.8
= 7A
ILIMIT(MIN) =
5.7mΩ
and the required valley current limit is:
ILIMIT(MIN) > 7A ✕ (1 - 0.30/2) = 5.95A
since 7A is greater than the required 5.95A, the circuit
can deliver the 7A full-load current.
Output Capacitor Selection
(BUCK1 and BUCK2)
The output filter capacitor must have low enough effective series resistance (ESR) to meet output ripple and
load-transient requirements, yet have high enough ESR
to satisfy stability requirements. Also, the capacitance
value must be high enough to absorb the inductor energy going from a full-load to no-load condition without
tripping the OVP circuit.
In CPU core voltage regulators and other applications
where the output is subject to violent load transients,
the output capacitor’s size typically depends on how
much ESR is needed to prevent the output from dipping
too low under a load transient. Ignoring the sag due to
finite capacitance:
RESR ≤
VDIP
ILOAD(MAX)
In non-CPU applications, the output capacitor’s size
often depends on how much ESR is needed to maintain
an acceptable level of output-voltage ripple:
RESR ≤
VP − P
LIR × ILOAD(MAX)
The actual microfarad capacitance value required often
relates to the physical size needed to achieve low ESR,
as well as to the chemistry of the capacitor technology.
Thus, the capacitor is usually selected by ESR and voltage rating rather than by capacitance value (this is true
of tantalums, OSCONs, and other electrolytics).
When using low-capacity filter capacitors such as
ceramic or polymer types, capacitor size is usually determined by the capacity needed to prevent VSAG and
VSOAR from causing problems during load transients.
Generally, once enough capacitance is added to meet
the overshoot requirement, undershoot at the rising load
edge is no longer a problem.
The amount of overshoot due to stored inductor energy
can be calculated as:
VSOAR =
L × IPEAK 2
2 × COUT × VOUT
where IPEAK is the peak inductor current.
______________________________________________________________________________________
39
MAX1816/MAX1994
The minimum current-limit threshold must be great
enough to support the maximum load current when the
current limit is at the minimum tolerance value. The valley of the inductor current occurs at ILOAD(MAX) minus
half of the ripple current; therefore:
MAX1816/MAX1994
Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers
BUCK1 Stability Considerations
BUCK1 is fundamentally different from previous QuickPWM controllers in two respects: it uses a current-sense
amplifier to obtain the current feedback signal (ramp),
and it uses differential remote sense to compensate for
voltage drops along the high-current path. The regulator
adds the differential remote-sense signal to the currentfeedback signal to correct the output voltage. As long
as the amplitude of the resulting signal is greater than
1% of the output voltage, the regulator remains stable.
Stability can be determined by comparing the zero
formed with the current-sense feedback network to the
switching frequency.
The boundary condition of stability is given by the following expression:
f
fZ ≤ SW
π
fZ ≈
1
RDROOP × (COUT1 + CREMOTE ) +

2π × 

RLOCAL × COUT1 + RREMOTE × CREMOTE 
where COUT1 is the local output capacitance (Figure 1),
CREMOTE is the remote output capacitance, RLOCAL is
the ESR of the local capacitors, RREMOTE is the ESR of
the remote capacitors, and RDROOP is the effective
voltage-positioning resistance, which is determined by
the voltage-positioning gain AVPS and current-sense
resistor RSENSE:
RDROOP = AVPS x RSENSE
Like previous Quick-PWM controllers, larger values of
ESR and sense resistance increase stability. The voltage-positioning gain A VPS effectively increases the
sense resistance, which further enhances stability.
The RC time constants of the local and remote capacitors affect the stability criteria. These two time constants are defined as follows:
τLOCAL = (RDROOP + RLOCAL + RPCB_TRACE) x COUT1
τREMOTE = (RDROOP + RREMOTE) x CREMOTE
where RPCB_TRACE is the PC board trace resistance
shown in Figure 1.
40
When the local capacitance time constant is either
much greater or much smaller than that of the remote
capacitance, the stability criteria is:
RDROOP × (COUT1 + CREMOTE ) + RLOCAL ×
COUT1 + RREMOTE × CREMOTE ≥
1
2 × fSW
In applications where these two time constants are
approximately equal, the criteria for stable operation
reduces to:
(RDROOP + RLOCAL ) × COUT1 ≥ 2 ×1f and
SW
(RDROOP + RREMOTE ) × CREMOTE ≥ 2 ×1f
SW
The standard application circuit (Figure 1) operating at
300kHz easily achieves stable operation because the
time constant of the local capacitors is much greater
than that of the remote capacitors.
In this example, COUT1 = 990µF, RLOCAL = 3.3mΩ,
CREMOTE = 10µF, RREMOTE = 5mΩ, and RDROOP = 2 x
1mΩ = 2mΩ:
2mΩ × (990µF + 10µF) + 3.3mΩ
× 990µF + 5mΩ × 10µF ≥
1
2 × 300kHz
5.32µs ≥ 1.67µs
When voltage positioning is not used (AVPS = 0) and the
ESR of the output capacitors alone cannot meet the stability requirement, the current feedback signal must be
generated from a different source. The current ramp signal at CS1+ and the output voltage must be summed at
the FBS input. For stable operation, a 3.3µF feed-forward capacitor is added from the CS1+ input to FBS
and a 10Ω resistor is inserted from the remote load to
FBS forming an RC filter (Figure 12). The cutoff frequency of the RC filter should be approximately an order of
magnitude lower than the regulator’s switching frequency to prevent sluggish transient response. To avoid
input-bias current-induced offset errors, the resistor
should be less than 20Ω.
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Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers
RSENSE
1mΩ × (990µF + 10µF) + 3.3mΩ
× 990µF + 5mΩ × 10µF ≥
CS1+
3.3µF
REMOTE
LOAD
COUT
PC BOARD TRACE
RESISTANCE
CS1-
10Ω
FBS
GDS
Figure 12. Output Feed Forward for Nonvoltage-Positioned
Applications
For nonvoltage-positioned applications using a feedforward circuit, the RC time constants of the local and
remote capacitors are defined as:
τLOCAL = (RSENSE + RLOCAL) x COUT1
τREMOTE = (RSENSE + RREMOTE + RPCB_TRACE)
x CREMOTE
The new stability criteria for nonvoltage-positioned
applications using feed forward becomes:
RSENSE × (COUT1 + CREMOTE ) + RLOCAL ×
COUT1 + RREMOTE × CREMOTE ≥
1
2 × fSW
for τ LOCAL much greater or much smaller than
τREMOTE, and
(RSENSE + RLOCAL ) × COUT1 ≥ 2 ×1f and
SW
(RSENSE + RREMOTE ) × CREMOTE ≥ 2 ×1f
SW
when τLOCAL and τREMOTE are approximately equal.
If the voltage-positioning gain in the standard application circuit (Figure 1) is set to zero and the feed-forward
compensation circuit shown in Figure 12 is used, stable
operation can still be easily achieved.
In this example, COUT1 = 990µF, RLOCAL = 3.3mΩ,
CREMOTE = 10µF, RREMOTE = 5mΩ, RSENSE = 1mΩ,
and RPCB_TRACE = 2mΩ, and the local time constant is
much greater than the remote time constant.
1
2 × 300kHz
4.32µs ≥ 1.67µs
Unstable operation manifests itself in two related but
distinctly different ways: double-pulsing and fast-feedback loop instability. Double-pulsing occurs due to
noise on the output or because the ESR is so low that
there is not enough voltage ramp in the output-voltage
signal. This “fools” the error comparator into triggering
a new cycle immediately after the 400ns minimum offtime period has expired. Double-pulsing is more annoying than harmful, resulting in nothing worse than
increased output ripple. However, it can indicate the
possible presence of loop instability, which is caused
by insufficient current feedback signal.
Loop instability can result in oscillations at the output
after line or load perturbations that can trip the overvoltage protection latch or cause the output voltage to fall
below the tolerance limit. The easiest method for checking stability is to apply a very fast zero-to-max load
transient and carefully observe the output-voltage ripple envelope for overshoot and ringing. It can help to
simultaneously monitor the inductor current with an AC
current probe. Do not allow more than one cycle of
ringing after the initial step-response under/overshoot.
BUCK2 Stability Considerations
The stability criterion for BUCK2 is the same as previous
Quick-PWM controllers like the MAX1714. Stability is
determined by comparing the value of the ESR zero to
the switching frequency. The point of stability is given by
the following expression:
f
fESR ≤ SW
π
1
where
fESR =
2π × RESR × COUT
For good phase margin, it is recommended to increase
the equivalent RC time constant by a factor of two. The
standard application circuit (Figure 1) operating at
390kHz with COUT = 330µF and RESR = 10mΩ, easily
meets this requirement.
______________________________________________________________________________________
41
MAX1816/MAX1994
Therefore:
PC BOARD TRACE
RESISTANCE
MAX1816/MAX1994
Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers
Input Capacitor Selection
The input capacitor must meet the ripple current
requirement (IRMS) imposed by the switching currents
defined by the following equation:
IRMS = ILOAD
VOUT (VIN − VOUT )
VIN
The RMS input currents for BUCK1 and BUCK2 can be
calculated using the above equation. Use the sum
of these two currents as the total RMS current. Note
that this is a very conservative estimation because the
two regulators are never in phase 100% of the time.
The actual RMS current is always lower than the
calculated value.
For most applications, nontantalum chemistries (ceramic
or OSCON) are preferred due to their resilience to
inrush surge currents typical of systems with a switch
or a connector in series with the battery. If the
MAX1816/MAX1994 operate as the second stage of a
two-stage power conversion system, tantalum input
capacitors are acceptable. In either configuration,
choose an input capacitor that exhibits less than +10°C
temperature rise at the RMS input current for optimal
circuit longevity.
Power MOSFET Selection
Most of the following MOSFET guidelines focus on the
challenge of obtaining high load-current capability
(>12A) when using high-voltage (>20V) AC adapters.
Low-current applications usually require less attention.
The high-side MOSFET (Q1 in Figure1) must be able to
dissipate the resistive losses plus the switching losses
at both VIN(MIN) and VIN(MAX). Calculate both of these
sums. Ideally, the losses at VIN(MIN) should be roughly
equal to the losses at VIN(MAX), with lower losses in
between. If the losses at VIN(MIN) are significantly higher than the losses at VIN(MAX), consider increasing the
size of Q1. Conversely, if the losses at VIN(MAX) are significantly higher than the losses at VIN(MIN), consider
reducing the size of Q1. If VIN does not vary over a
wide range, the minimum power dissipation occurs
where the resistive losses equal the switching losses.
Choose a low-side MOSFET (Q2) that has the lowest
possible RDS(ON), comes in a moderate-sized package
(i.e., two or more 8-pin SOs, DPAKs, or D2PAKs), and is
reasonably priced. Ensure that the MAX1816/MAX1994
DL_ gate driver can drive Q2; in other words, check that
the dV/dt caused by Q1 turning on does not pull up the
gate of Q2 due to drain-to-gate capacitance, causing
cross-conduction problems. Switching losses are not an
42
issue for the low-side MOSFET, since it is a zero-voltage
switched device when used in the buck topology.
MOSFET Power Dissipation
The high-side MOSFET conduction power dissipation
due to on-state channel resistance is:
V
PD(Q1_ Conduction) = OUT × ILOAD2 × RDS(ON)1
VIN
Generally, a small high-side MOSFET is desired to
reduce switching losses at high input voltages.
However, the RDS(ON) required to stay within package
power-dissipation limits often constrains how small the
MOSFET can be.
Switching losses in the high-side MOSFET can become
an insidious heat problem when maximum AC adapter
voltages are applied, due to the squared term in the
CV2fSW switching-loss equation. If the high-side MOSFET
chosen for adequate RDS(ON) at low battery voltages
becomes extraordinarily hot when subjected to VIN(MAX),
reconsider the MOSFET selection.
Calculating the power dissipation in Q1 due to switching losses is difficult since it must allow for difficult
quantifying factors that influence the turn-on and turnoff times. These factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and PC board layout characteristics. The following switching-loss calculation provides only a very
rough estimate and is no substitute for breadboard
evaluation and thermal measurements:
PD(Q1_ Switching) =
CRSS × VIN(MAX)2 × fSW × ILOAD
IGATE
where CRSS is the reverse transfer capacitance of Q1
and IGATE is the peak gate-drive source/sink current
(1.5A typ for BUCK1, 0.75A typ for BUCK2).
For the low-side MOSFET (Q2), the worst-case power
dissipation always occurs at maximum battery voltage:

VOUT 
2
PD(Q2) = 1 −
 × ILOAD × RDS(ON)2
V
IN(MAX) 

The worst case for MOSFET power dissipation occurs
under heavy overloads that are greater than ILOAD(MAX)
but are not quite high enough to exceed the current limit
and cause the fault latch to trip. To protect against this
possibility, “overdesign” the circuit to tolerate:
ILOAD = ILIMIT(HIGH ) + (LIR/2) ✕ ILOAD(MAX)
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Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers
The MOSFETs must have a good-sized heat sink to
handle the overload power dissipation. If short-circuit
protection without overload protection is enough, a
normal ILOAD value can be used for calculating component stresses.
Choose a Shottky diode (D1) having a forward voltage
low enough to prevent the Q2 MOSFET body diode
from turning on during the dead time. As a general rule,
a diode having a DC current rating equal to 1/3 of the
load current is sufficient. This diode is optional and can
be removed if efficiency is not critical.
Linear Regulator
Design Procedure
Output Voltage Selection
Adjust the linear regulator’s output voltage by connecting a resistive voltage-divider from VLIN to AGND with
the center tap connected to LINFB (Figure 1). Select R9
in the range of 10kΩ to 100kΩ. Calculate R8 with the
following equation:
R8 = R9 [(VLIN / 1.00V) - 1]
Pass Transistor Selection
The PNP pass transistor must meet specifications for
current gain (hFE), input capacitance, emitter-collector
saturation voltage, and power dissipation. The
transistor’s current gain limits the guaranteed maximum
output current to:

ILOAD(MAX) = IDRV

−
VEB 
hFE(MIN)
REB 
where IDRV is the minimum base-drive current, and REB
is the pullup resistor connected between the transistor’s emitter and base. Furthermore, the transistor’s current gain increases the linear regulator’s DC loop gain
(see the Linear Regulator Stability Requirements section), so excessive gain destabilizes the output.
Therefore, transistors with current gain over 300A/A at
the maximum output current are not recommended.
The transistor’s input capacitance and input resistance
also create a second pole, which could be low enough
to make the output unstable when heavily loaded.
The transistor’s saturation voltage at the maximum output current determines the minimum input-to-output
voltage differential that the linear regulator supports.
Alternatively, the package’s power dissipation could
limit the usable maximum input-to-output voltage differential. The maximum power dissipation capability of the
transistor’s package and mounting must exceed the
actual power dissipation in the device.
The power dissipation equals the maximum load current
times the maximum input-to-output voltage differential:
P = ILOAD(MAX) x (VLDOIN - VLIN) = ILOAD(MAX) x VCE
Linear Regulator Stability Requirements
The MAX1816/MAX1994 linear-regulator controller uses
an internal transconductance amplifier to drive an
external pass transistor. The transconductance amplifier, the pass transistor, the emitter-base resistor, and
the output capacitor determine the loop stability. If the
output capacitor and pass transistor are not properly
selected, the linear regulator is unstable.
The transconductance amplifier regulates the output
voltage by controlling the pass transistor’s base current. Since the output voltage is a function of the load
current and load resistance, the total DC loop gain is
approximately:
V
 I
h 
A V(LDO) =  REF  1 +  BIAS FE   5.5
 VT    ILOAD  
where VT is 26mV at room temperature, IBIAS is the current though the emitter-base resistor (REB), and VREF =
1.0V. This bias resistor is typically 220Ω, providing
approximately 3.2mA of bias current.
The output capacitor and the load resistance create the
dominant pole in the system. However, the pass transistor’s input capacitance creates a second pole in the
system. Additionally, the output capacitor’s ESR generates a zero. To achieve stable operation, use the following equations to verify that the linear regulator is
properly compensated:
1) First, determine the dominant pole set by the linear
regulator’s output capacitor and the load resistor:
fPOLE(CLDO) =
1
2πCLDORLOAD
=
ILOAD(MAX)
2πCLDOVLDO
The unity gain crossover of the linear regulator is:
fCROSSOVER = AV(LDO)fPOLE(CLDO)
2) Next, determine the second pole set by the emitterbase capacitance (including the transistor’s input
capacitance), the transistor’s input resistance, and
the emitter-base pullup resistor:
______________________________________________________________________________________
43
MAX1816/MAX1994
where I LIMIT(HIGH) is the maximum valley current
allowed by the current-limit circuit, including threshold
tolerance and on-resistance variation.
MAX1816/MAX1994
Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers
R I
+ VThFE
1
fPOLE(CEB) =
= EB LOAD
2πCEB (REB || RIN )
2πCEB REB VThFE
3) A third pole is set by the linear regulator’s feedback
resistance and the capacitance between LINFB
and GND, including the stray capacitance:
fPOLE(FB) =
1
2πCFB (R8 || R9)
4) If the second and third poles occur well after unity
gain crossover, the linear regulator remains stable:
fPOLE(CEB) > 2fPOLE(CLDO)AV(LDO)
However, if the ESR zero occurs before the unity gain
crossover, cancel the zero with the feedback pole by
changing circuit components such that:
fPOLE(FB) ≈
1
2πCLDORESR
For most applications where ceramic capacitors are
used, the ESR zero always occurs after the crossover.
Output Capacitor Selection
Typically, more output capacitance provides the best
performance, since this also reduces the output voltage
drop immediately after a load transient. Connect at
least a 10µF capacitor between the linear regulator’s
output and ground, as close to the external pass transistor as possible. Depending on the selected pass
transistor, larger capacitor values may be required
for stability (see the Linear Regulator Stability
Requirements section). Furthermore, the output capacitor’s ESR affects stability. Use output capacitors with an
ESR less than 200mΩ to ensure stability and optimum
transient response. Once the minimum capacitor value
for stability is determined, verify that the linear regulator’s output does not contain excessive noise. Although
adequate for stability, small capacitor values can provide too much bandwidth, making the linear regulator
sensitive to noise. Larger capacitor values reduce the
bandwidth, thereby reducing the regulator’s noise sensitivity.
Applications Information
Voltage Positioning
Powering new mobile processors requires new techniques to reduce cost, size, and power dissipation.
Voltage positioning reduces the total number of output
capacitors to meet a given transient response require44
ment. Setting the no-load output voltage slightly higher
allows a larger step down when the output current suddenly increases, and regulating at the lower output voltage under load allows a larger step up when the output
current suddenly decreases. Allowing a larger step size
means that the output capacitance can be reduced
and the capacitor’s ESR can be increased.
Adding a series output resistor positions the full-load
output voltage below the actual DAC programmed voltage. Connect FB directly to the inductor side of the
voltage-positioning resistor (R1, 1mΩ). The other side
of the voltage-positioning resistor should be connected
directly to the output filter capacitor with a short, wide
PC board trace. With the gain pin floating (GAIN = 2), a
20A full-load current causes a 40mV drop in the output.
This 40mV is a -3.2% droop.
An additional benefit of voltage positioning is reduced
power consumption at high load currents. Because the
output voltage is lower under load, the CPU draws less
current. The result is lower power dissipation in the
CPU, although some extra power is dissipated in R1.
For a nominal 1.25V, 20A output, reducing the output
voltage by 3.2% gives an output voltage of 1.21V and
an output current of 19.4A. Given these values, CPU
power consumption is reduced from 25W to 23.5W. The
additional power consumption of R1 is:
1mΩ ✕ (19.4A)2 = 0.38W
And the overall power savings is as follows:
25W - (23.5W + 0.38W) = 1.12W
In effect, 1.5W of CPU dissipation is saved, and the
power supply dissipates some of the power savings,
but both the net savings and the transfer of dissipation
away from the hot CPU are beneficial.
High-Current Master-Slave Applications
The MAX1816/MAX1994 can be used in high-current
applications using additional slave regulators. Figure 2
illustrates a 40A master-slave application using this
technique. The MAX1994 is placed in forced PWM
mode to simplify operation with the slave. Refer to the
MAX1980 data sheet for a detailed description of the
master-slave architecture and how to configure correctly
the slave circuit.
Dropout Performance
The output voltage adjustment range for continuousconduction operation is restricted by the nonadjustable
500ns (max) minimum off-time one-shot (375ns max at
550kHz and 1000kHz). For best dropout performance,
use the slower (200kHz) on-time settings.
______________________________________________________________________________________
Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers
A reasonable minimum value for h is 1.5, but this can
be adjusted up or down to allow trade-offs between
VSAG, output capacitance, and minimum operating voltage. For a given value of h, the minimum operating voltage can be calculated as:
VIN(MIN) =
(VOUT + VDROP1)
+ VDROP2 − VDROP1
T

OFF(MIN) × h
1− 


K


where VDROP1 and VDROP2 are the parasitic voltage
drops in the discharge and charge paths, respectively
(see the On-Time One-Shot (TON) section), TOFF(MIN)
is from the Electrical Characteristics table, and K is
taken from Table 3. The absolute minimum input voltage is calculated with h = 1.
If the calculated VIN(MIN) is greater than the required
minimum input voltage, then operating frequency must
be reduced or output capacitance added to obtain
an acceptable V SAG . If operation near dropout is
anticipated, calculate VSAG to be sure of adequate
transient response.
Dropout Design Example
VOUT = 1.2V
fSW = 300kHz
K = 3.3µs, worst-case K = 2.97µs
TOFF(MIN) = 500ns
VDROP1 = VDROP2 = 100mV
h = 1.5
VIN(MIN) =
(1.2V + 0.1V)
+ 0.1V − 0.1V = 1.74V
 0.5µs × 1.5 
1− 

 2.97µs 
Calculate again with h = 1 gives the absolute limit of
dropout:
VIN(MIN) =
(1.2V + 0.1V)
+ 0.1V − 0.1V = 1.56V
 0.5µs × 1
1− 

 2.97µs 
Since 1.56V is less than the lower limit of the input voltage range (2V), the practical minimum input voltage
with reasonable output capacitance would be 2V.
One-Stage (Battery Input) vs.
Two-Stage (5V Input) Conversion
The MAX1816/MAX1994 can be used with a direct battery connection (one stage) or can obtain power from a
regulated 5V supply (two stage). Each approach has
advantages, and careful consideration should go into
the selection of the final design.
The one-stage approach offers smaller total inductor
size and fewer capacitors overall due to the reduced
demands on the 5V supply. The transient response of
the single stage is better due to the ability to ramp up
the inductor current faster. The total efficiency of a single stage is better than the two-stage approach.
The two-stage approach allows flexible placement due
to smaller circuit size and reduced local power dissipation. The power supply can be placed closer to the
CPU for better regulation and lower I2R losses from PC
board traces. Although the two-stage design has worse
transient response than the single stage, this can be
offset by the use of a voltage-positioned converter.
Ceramic Output Capacitor Applications
Ceramic capacitors have advantages and disadvantages. They have ultra-low ESR and are noncombustible, relatively small, and nonpolarized. They are
also expensive and brittle, and their ultra-low ESR characteristic can result in excessively high ESR zero frequencies (affecting stability in nonvoltage-positioned
circuits). In addition, their relatively low capacitance
value can cause output overshoot when going abruptly
from full-load to no-load conditions, unless the inductor
value can be made small (high switching frequency), or
there are some bulk tantalum or electrolytic capacitors
in parallel to absorb the stored energy in the inductor.
In some cases, there may be no room for electrolytic
capacitors, creating a need for a DC-DC design that
uses nothing but ceramic capacitors.
______________________________________________________________________________________
45
MAX1816/MAX1994
When working with low-input voltages, the duty-factor limit
must be calculated using worst-case values for on- and
off-times. Manufacturing tolerances and internal propagation delays introduce an error to the TON K factor. This
error is greater at higher frequencies (Table 3).
Also, keep in mind that transient response performance
of buck regulators operated close to dropout is poor,
and bulk output capacitance must often be added (see
the VSAG equation in the Design Procedure section).
The absolute point of dropout is when the inductor current ramps down during the minimum off-time (∆IDOWN)
as much as it ramps up during the on-time (∆IUP). The
ratio h = ∆IUP/∆IDOWN is an indicator of ability to slew
the inductor current higher in response to increased
load, and must always be greater than 1. As h
approaches 1, the absolute minimum dropout point, the
inductor current is less able to increase during each
switching cycle and VSAG greatly increases, unless
additional output capacitance is used.
MAX1816/MAX1994
Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers
The MAX1816/MAX1994 can take full advantage of the
small size and low ESR of ceramic output capacitors in
a voltage-positioned circuit. The addition of the positioning resistor increases the ripple at FB, lowering the
effective ESR zero frequency of the ceramic output
capacitor.
Output overshoot (V SOAR) determines the minimum
output capacitance requirement (see the Output
Capacitor Selection section). Often the switching frequency is increased to 550kHz or 1000kHz, and the
inductor value is reduced to minimize the energy transferred from inductor to capacitor during load-step
recovery. The efficiency penalty for operating at
550kHz is about 2% to 3% and about 5% at 1000kHz
when compared to the 300kHz voltage-positioned circuit, primarily due to the high-side MOSFET switching
losses.
PC Board Layout Guidelines
Careful PC board layout is critical to achieve low
switching losses and clean, stable operation. The
switching power stage requires particular attention
(Figure 13). Refer to the MAX1816/MAX1994 EV kit data
sheet for a specific layout example.
If possible, mount all of the power components on the
top side of the board with their ground terminals flush
against one another. Follow these guidelines for good
PC board layout:
1) Isolate the power components on the top side from
the sensitive analog components on the bottom
side with a ground shield. Use a separate PGND
plane under the BUCK1 and BUCK2 sides (called
PGND1 and PGND2). Avoid the introduction of AC
currents into the PGND1 and PGND2 ground
planes.
2) Use a star ground connection on the power plane
to minimize the crosstalk between BUCK1 and
BUCK2.
3) Keep the high-current paths short, especially at the
ground terminals. This is essential for stable, jitterfree operation.
4) Connect all analog grounds to a separate solid
copper plane, which connects to the AGND pin of
the MAX1816/MAX1994. This includes the V CC
bypass capacitor, REF bypass capacitor, compensation components, the TIME resistor, as well as
any other resistive dividers.
46
5) Tie AGND and PGND together close to the IC. Do
not connect them together anywhere else. Carefully
follow the grounding instructions in the Layout
Procedure.
6) In high-current master-slave applications, the master controller should have a separate analog
ground. Return the appropriate noise-sensitive
components to this plane. Since the reference in
the master is sometimes connected to the slave, it
may be necessary to couple the analog ground in
the master to the analog ground in the slave to prevent ground offsets. A low value (≤10Ω) resistor is
sufficient to link the two grounds.
7) Keep the power traces and load connections short.
This is essential for high efficiency. The use of thick
copper PC boards (2oz vs. 1oz) can enhance full
load efficiency by 1% or more. Correctly routing PC
board traces is a difficult task that must be
approached in terms of fractions of centimeters,
where a single milliohm of excess trace resistance
causes a measurable efficiency penalty.
8) Keep the high-current gate-driver traces (DL_, DH_,
LX_, and BST_) short and wide to minimize trace
resistance and inductance. This is essential for
high-power MOSFETs that require low-impedance
gate drivers to avoid shoot-through currents.
9) CS1+, CS1-, CS2, and AGND connections for current limiting must be made using Kelvin-sense connections to guarantee the current-limit accuracy.
Kelvin connections to LX2 and AGND must also be
made if the synchronous rectifier R DS(ON) of
BUCK2 is used for current limiting. With 8-pin SO
MOSFETs, this is best done by routing power to the
MOSFETs from the outside using the top copper
layer, while connecting GND and LX inside (underneath) the 8-pin SO package.
10) When trade-offs in trace lengths must be made, it is
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
it is better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the lowside MOSFET or between the inductor and the output filter capacitor.
11) Route high-speed switching nodes away from sensitive analog areas (CC, REF, ILIM_). Make all pinstrap control input connections (SKP_/SDN, ILIM_,
etc.) to analog ground or VCC rather than power
ground or VDD.
______________________________________________________________________________________
Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers
MAX1816/MAX1994
COUT1
COUT1
POWER GROUND
TOP LAYER
VOUT1
VIA TO POWER GROUND
REF CAP
COUT1
POWER GROUND
COUT1
VDD CAP
COUT2
COUT2
L1
VOUT2
L2
MAX1816
MAX1994
LX1
ANALOG
GROUND
VCC CAP
LX2
POWER GROUND
BOTTOM LAYER
CIN
CIN
CIN
CIN
CIN
CIN
INPUT (V+)
LX1
LX2
Figure 13. Power-Stage PC Board Layout Example
Layout Procedure
1) Place the power components first, with ground terminals adjacent (low-side MOSFET sources, CIN_,
COUT_, D1/D2 anodes). If possible, make all these
connections on the top layer with wide, copperfilled areas.
2) Mount the controller IC adjacent to the low-side MOSFET, preferably on the backside in order to keep LX_,
PGND_, and the DL_ drive lines short and wide. The
DL_ gate traces must be short and wide, measuring
10 to 20 squares (50 mils to 100 mils wide if the
MOSFET is 1in from the controller IC).
3) Group the gate-drive components (BST_ diodes
and capacitors, VDD bypass capacitor) together
near the controller IC.
4) Make the MAX1816/MAX1994 controllers’ ground
connections as shown in Figure 13. This diagram
can be viewed as having three separate ground
planes: input/output ground, where all the high-
power components go; the power ground plane,
where the PGND pin and VDD bypass capacitors
go; and an analog ground plane where sensitive
analog components go. The analog ground plane
and power ground plane must meet only at a single
point close to the IC. These two planes are then
connected to the high-power output ground with a
short connection from PGND to the source of the
low-side MOSFET (the middle of the star ground).
This point must also be very close to the output
capacitor ground terminal.
5) Connect the output power planes (VCORE and system ground planes) directly to the output filter
capacitor positive and negative terminals with multiple vias. Place the entire DC-DC converter circuit
as close to the CPU as is practical.
Chip Information
TRANSISTOR COUNT: 13,313
______________________________________________________________________________________
47
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
32, 44, 48L QFN .EPS
MAX1816/MAX1994
Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers
D2
D
CL
D/2
b
D2/2
k
E/2
E2/2
E
CL
(NE-1) X e
E2
k
L
DETAIL A
e
(ND-1) X e
CL
CL
L
L
e
A1
A2
e
A
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE
32, 44, 48L QFN THIN, 7x7x0.8 mm
APPROVAL
DOCUMENT CONTROL NO.
21-0144
48
______________________________________________________________________________________
REV.
A
1
2
Dual Step-Down Controllers Plus LinearRegulator Controller for Notebook Computers
COMMON DIMENSIONS
EXPOSED PAD VARIATIONS
** NOTE: T4877-1 IS A CUSTOM 48L PKG. WITH 4 LEADS DEPOPULATED.
TOTAL NUMBER OF LEADS ARE 44.
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE
32, 44, 48L QFN THIN, 7x7x0.8 mm
APPROVAL
DOCUMENT CONTROL NO.
21-0144
REV.
A
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 49
© 2002 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
MAX1816/MAX1994
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)