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PowerPoint PresentationI = C dV/dt -> tpd (C/I) DV

low capacitance

high current

small swing

pMOS are the enemy!

Can we take the pMOS capacitance off the input?

Various circuit families try to do this…

EE 447 VLSI Design

Instead, use pull-up transistor that is always ON

In CMOS, use a pMOS that is always ON

Ratio issue

EE 447 VLSI Design

to compare with unit inverter.

pMOS fights nMOS

to compare with unit inverter.

pMOS fights nMOS

to compare with unit inverter.

pMOS fights nMOS

to compare with unit inverter.

pMOS fights nMOS

Pseudo-nMOS Design

Ex: Design a k-input AND gate using pseudo-nMOS. Estimate the delay driving a fanout of H

G =

F =

P =

N =

D =

Pseudo-nMOS Design

Ex: Design a k-input AND gate using pseudo-nMOS. Estimate the delay driving a fanout of H

G = 1 * 8/9 = 8/9

N = 2

A few mA / gate * 1M gates would be a problem

This is why nMOS went extinct!

Use pseudo-nMOS sparingly for wide NORs

Turn off pMOS when not in use

EE 447 VLSI Design

Two modes: precharge and evaluate

EE 447 VLSI Design

Use series evaluation transistor to prevent fight.

EE 447 VLSI Design

0 -> 0

0 -> 1

1 -> 1

Illegal for one dynamic gate to drive another!

EE 447 VLSI Design

Illegal for one dynamic gate to drive another!

EE 447 VLSI Design

Produces monotonic outputs

Domino Optimizations

Each domino gate triggers next one, like a string of dominos toppling over

Gates evaluate sequentially but precharge in parallel

Thus evaluation is more critical than precharge

HI-skewed static stages can perform logic

EE 447 VLSI Design

AND, OR but not NAND, NOR, or XOR

Dual-rail domino solves this problem

Takes true and complementary inputs

Produces true and complementary outputs

sig_h

sig_l

Meaning

0

0

Precharged

0

1

‘0’

1

0

‘1’

1

1

invalid

Compute Y_h = A * B, Y_l = ~(A * B)

EE 447 VLSI Design

Compute Y_h = A * B, Y_l = ~(A * B)

Pulldown networks are conduction complements

EE 447 VLSI Design

EE 447 VLSI Design

Transistors are leaky (IOFF 0)

Dynamic value will leak away over time

Formerly miliseconds, now nanoseconds!

Must be weak enough not to fight evaluation

EE 447 VLSI Design

EE 447 VLSI Design

EE 447 VLSI Design

EE 447 VLSI Design

Typically need to precharge every other node

Big load capacitance CY helps as well

EE 447 VLSI Design

Inputs: VIH Vtn

Noise sources

Capacitive crosstalk

Charge sharing

1.5 – 2x faster than static CMOS

But many challenges:

EE 447 VLSI Design

CMOS + Transmission Gates:

Use weak pMOS feedback to pull fully high

Ratio constraint

Avoids need for ratioed feedback

Optional cross-coupling for rail-to-rail swing

B

A

1

1

4

4

Y

V

out

V

in

16/2

P/2

I

ds

load

0

0.3

0.6

0.9

1.2

1.5

1.8

0

0.3

0.6

0.9

1.2

1.5

1.8

violates monotonicity

during evaluation

Y

f

Precharge

Evaluate

W

Precharge

X

Y

Z

A

f

B

C

f

f

f

C

A

B

W

X

Y

Z

low capacitance

high current

small swing

pMOS are the enemy!

Can we take the pMOS capacitance off the input?

Various circuit families try to do this…

EE 447 VLSI Design

Instead, use pull-up transistor that is always ON

In CMOS, use a pMOS that is always ON

Ratio issue

EE 447 VLSI Design

to compare with unit inverter.

pMOS fights nMOS

to compare with unit inverter.

pMOS fights nMOS

to compare with unit inverter.

pMOS fights nMOS

to compare with unit inverter.

pMOS fights nMOS

Pseudo-nMOS Design

Ex: Design a k-input AND gate using pseudo-nMOS. Estimate the delay driving a fanout of H

G =

F =

P =

N =

D =

Pseudo-nMOS Design

Ex: Design a k-input AND gate using pseudo-nMOS. Estimate the delay driving a fanout of H

G = 1 * 8/9 = 8/9

N = 2

A few mA / gate * 1M gates would be a problem

This is why nMOS went extinct!

Use pseudo-nMOS sparingly for wide NORs

Turn off pMOS when not in use

EE 447 VLSI Design

Two modes: precharge and evaluate

EE 447 VLSI Design

Use series evaluation transistor to prevent fight.

EE 447 VLSI Design

0 -> 0

0 -> 1

1 -> 1

Illegal for one dynamic gate to drive another!

EE 447 VLSI Design

Illegal for one dynamic gate to drive another!

EE 447 VLSI Design

Produces monotonic outputs

Domino Optimizations

Each domino gate triggers next one, like a string of dominos toppling over

Gates evaluate sequentially but precharge in parallel

Thus evaluation is more critical than precharge

HI-skewed static stages can perform logic

EE 447 VLSI Design

AND, OR but not NAND, NOR, or XOR

Dual-rail domino solves this problem

Takes true and complementary inputs

Produces true and complementary outputs

sig_h

sig_l

Meaning

0

0

Precharged

0

1

‘0’

1

0

‘1’

1

1

invalid

Compute Y_h = A * B, Y_l = ~(A * B)

EE 447 VLSI Design

Compute Y_h = A * B, Y_l = ~(A * B)

Pulldown networks are conduction complements

EE 447 VLSI Design

EE 447 VLSI Design

Transistors are leaky (IOFF 0)

Dynamic value will leak away over time

Formerly miliseconds, now nanoseconds!

Must be weak enough not to fight evaluation

EE 447 VLSI Design

EE 447 VLSI Design

EE 447 VLSI Design

EE 447 VLSI Design

Typically need to precharge every other node

Big load capacitance CY helps as well

EE 447 VLSI Design

Inputs: VIH Vtn

Noise sources

Capacitive crosstalk

Charge sharing

1.5 – 2x faster than static CMOS

But many challenges:

EE 447 VLSI Design

CMOS + Transmission Gates:

Use weak pMOS feedback to pull fully high

Ratio constraint

Avoids need for ratioed feedback

Optional cross-coupling for rail-to-rail swing

B

A

1

1

4

4

Y

V

out

V

in

16/2

P/2

I

ds

load

0

0.3

0.6

0.9

1.2

1.5

1.8

0

0.3

0.6

0.9

1.2

1.5

1.8

violates monotonicity

during evaluation

Y

f

Precharge

Evaluate

W

Precharge

X

Y

Z

A

f

B

C

f

f

f

C

A

B

W

X

Y

Z