RF2431 8 HIGH FREQUENCY LNA/MIXER Typical Applications • UHF Digital and Analog Receivers • Commercial and Consumer Systems • Digital Communication Systems • Portable Battery-Powered Equipment • Spread-Spectrum Communication Systems • General Purpose Frequency Conversion Product Description .157 .150 1 GaAs HBT Si Bi-CMOS SiGe HBT ü .010 .004 .393 .386 .050 .244 .228 8 .065 .043 8 °MAX 0°MIN .050 .016 Optimum Technology Matching® Applied Si BJT .018 .014 FRONT-ENDS The RF2431 is a monolithic integrated UHF receiver front-end. The IC contains all of the required components to implement the RF functions of the receiver except for the passive filtering and LO generation. It contains an LNA (low-noise amplifier), a second RF amplifier, a dualgate GaAs FET mixer, and an IF output buffer amplifier which will drive a 50Ω load. Alternatively, the IF output may be matched to a higher impedance at significantly reduced current. The output of the LNA is made available as an output to permit the insertion of a bandpass filter between the LNA and the RF/Mixer section. The LNA output is buffered to permit a wide range of choices for the interstage filter without altering the VSWR or noise figure at the LNA input and to provide high isolation from the LO to the input port. .010 .007 Package Style: SOP-16 GaAs MESFET Si CMOS Features • Single 3V to 6.5V Power Supply • 1500MHz to 2500MHz Operation LN A 16 LN A O U T • 23dB Small Signal Gain GND 2 15 G N D • 3.5dB Cascaded Noise Figure VDD1 3 14 N /C VDD2 4 13 N /C LN A IN 1 IF 1 5 12 D E C IF 2 6 • 13mA DC Current Consumption • -14dBm Input IP3 11 N /C BUFFER GND 7 10 G N D RF AMP LO IN 8 9 R F IN M IX E R Functional Block Diagram Rev B1 010329 Ordering Information RF2431 High Frequency LNA/Mixer RF2431 PCBA-L Fully Assembled Evaluation Board (1.8GHz) RF2431 PCBA-H Fully Assembled Evaluation Board (2.5GHz) RF Micro Devices, Inc. 7625 Thorndike Road Greensboro, NC 27409, USA Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com 8-43 RF2431 Absolute Maximum Ratings Parameter Supply Voltage Input LO and RF Levels Operating Ambient Temperature Storage Temperature Parameter (1800MHz) Rating Unit -0.5 to 7.0 +6 -40 to +85 -40 to +150 VDC dBm °C °C Specification Min. Typ. Max. Caution! ESD sensitive device. RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s). Unit T = 25°C, VCC =5V, RF=1800MHz, LO=0dBm Overall RF Frequency Range IF Frequency Range Cascade Gain 15 Cascade IP3 Cascade Noise Figure Condition 1500 to 2500 DC to 400 23 19 -14 3.5 MHz MHz dB dB dBm dB 2.6 2.5:1 +2 13 30 1.5:1 dB IF=100MHz, 50Ω load IF=350MHz, 50Ω load Referenced to the input Single sideband First Section (LNA) FRONT-ENDS 8 Noise Figure Input VSWR Input IP3 Gain Reverse Isolation Output VSWR No external matching dBm dB dB No external matching High impedance output, 1.3kΩ load Second Section (RF Amp, Mixer, IF1) Noise Figure Input VSWR Input IP3 Conversion Gain Output Impedance 9.5 1.7:1 -1 6 4 dB dBm dB kΩ Second Section (RF Amp, Mixer, IF2) Noise Figure Input VSWR Input IP3 Conversion Gain Output VSWR 9.5 1.7:1 -1 6 1.2:1 dB Single sideband Open drain Buffered output, 50Ω load Single sideband dBm dB LO Input LO Level LO to RF Rejection LO to IF Rejection LO Input VSWR -6 to +6 15 25 1.5:1 dBm dB dB Power Supply Voltage Current Consumption 8-44 3 to 6.5 19 13 25 V mA mA VDD =5.0V, LNA On, Mixer On, Buffer On VDD =5.0V, LNA On, Mixer On, Buffer Off Rev B1 010329 RF2431 Parameter (2400MHz) Specification Min. Typ. Max. Unit T = 25°C, VCC =5V, RF=2400MHz, LO=0dBm Overall RF Frequency Range IF Frequency Range Cascade Gain Cascade IP3 Cascade Noise Figure Condition 2.0 to 2.5 DC to 400 13 10 -11 4.5 GHz MHz dB dB dBm dB 2.9 1.8:1 0 10 25 1.6:1 dB IF=100MHz, 50Ω load IF=350MHz, 50Ω load Referenced to the input Single sideband First Section (LNA) No external matching dBm dB dB No external matching High impedance output, 1.3kΩ load Second Section (RF Amp, Mixer, IF1) Noise Figure Input VSWR Input IP3 Conversion Gain Output Impedance 10 1.5:1 -1 3 4 dB dBm dB kΩ Second Section (RF Amp, Mixer, IF2) Noise Figure Input VSWR Input IP3 Conversion Gain Output VSWR 10 1.5:1 -1 3 1.2:1 dB Single sideband Open drain Buffered output, 50Ω load 8 Single sideband FRONT-ENDS Noise Figure Input VSWR Input IP3 Gain Reverse Isolation Output VSWR dBm dB LO Input LO Level LO to RF Rejection LO to IF Rejection LO Input VSWR -6 to +6 15 20 1.4:1 dBm dB dB 3 to 6.5 19 13 V mA mA Power Supply Voltage Current Consumption Rev B1 010329 VDD =5.0V, LNA On, Mixer On, Buffer On VDD =5.0V, LNA On, Mixer On, Buffer Off 8-45 RF2431 Pin 1 FRONT-ENDS 8 Function LNA IN 2 GND 3 VDD1 4 VDD2 5 IF1 OUT 6 7 8 IF2 OUT GND LO IN 9 RF IN+ 10 11 12 GND NC RF BYP 13 14 15 NC NC GND 8-46 Description This pin is NOT internally DC blocked. An external blocking capacitor must be provided if the pin is connected to a device with DC present. A DC path to ground (i.e. an inductor or resistor to ground) is, however, acceptable at this pin. If a blocking capacitor is required, a value of 22pF is recommended. Interface Schematic LNA IN Ground connection. Keep traces physically short and connect immediately to ground plane for best performance. Supply voltage for the LNA only. A 22pF external bypass capacitor is required and an additional 0.01µF is required if no other low frequency bypass capacitors are nearby. The trace length between the pin and the bypass capacitors should be minimized. The ground side of the bypass capacitors should connect immediately to ground plane. Power supply for the IF buffer amplifier. If the high impedance mixer output is being used, then this pin is not connected. Open drain output port, one of the two output options. This pin must be connected to VDD through a resistor in order to bias the mixer, even when using the IF2 Output. In addition, a 0.1µF bypass capacitor is required at the other end of the bias resistor. This output is intended to drive high impedance IF filters. The intrinsic output impedance is about 4kΩ, which means that the actual impedance is set by the external resistor to VDD. IF1 OUT 50Ω buffered output port, one of the two output options. This is an open drain output, therefore a resistor to ground is needed. The typical value for this resistor is 470Ω. Pin 4 must be connected to VDD in order to turn the buffer amplifier on. Current drain will increase by approximately 6mA at 5V; by approximately 3mA at 3V.This pin is not connected when using the high impedance port. Same as pin 2. Mixer LO input. An high-pass matching network, such as a single shunt inductor (as shown in the application schematics), is the recommended topology because it also rejects IF noise at the mixer input. The value of this inductor is depending on the frequency, see the application schematics. This filtering is required to achieve the specified noise figures. This pin is NOT internally DC blocked. An external blocking capacitor must be provided if the pin is connected to a device with DC present. A DC path to ground (i.e. an inductor or resistor to ground) is, however, acceptable at this pin. If a blocking capacitor is required, a value of 22pF is recommended. Mixer RF Input port. This pin is NOT internally DC blocked. An external blocking capacitor must be provided if the pin is connected to a device with DC present. A DC path to ground (i.e. an inductor or resistor to ground) is, however, acceptable at this pin. If a blocking capacitor is required, a value of 22pF is recommended. Matching is required; see the applications schematics.To minimize the noise figure it is recommended to have a bandpass filter before this input. This will prevent the noise at the image frequency from being converted to the IF. Same as pin 2. IF2 OUT LO IN RF IN No connection Connection for the external bypass capacitor for the mixer input buffer amplifier. 1nF is recommended. The trace length between the pin and the capacitor should be minimized. The ground side of the bypass capacitor should connect immediately to ground plane. No connection. No connection. Same as pin 2. Rev B1 010329 RF2431 Pin 16 Function LNA OUT Description Interface Schematic 50Ω output. Internally DC blocked. LNA OUT FRONT-ENDS 8 Rev B1 010329 8-47 RF2431 Application Schematic 1800MHz, High Impedance Output LN A R F IN VD 1 16 2 15 3 14 4 13 5 12 6 11 D 1 00 n F 22 p F < 1 kΩ 5 0 Ω Im a ge F ilter 1 nF IF O U T BUFFER 1 nF 10 7 M IX E R LO IN RF AMP 3 .3 n H 9 8 4.7 nH 8 1 .8 p F FRONT-ENDS Application Schematic 2400MHz, High Impedance Output LN A R F IN VD 1 16 2 15 3 14 4 13 5 12 6 11 D 1 00 n F 22 p F < 1 kΩ 5 0 Ω Im a ge F ilter 1 nF IF O U T BUFFER 1 nF 10 7 M IX E R LO IN 8 1.8 nH 8-48 1 .8 n H RF AMP 9 0 .9 p F Rev B1 010329 RF2431 Application Schematic 1800MHz, Buffered Output LN A R F IN VDD 10 0 nF 1 16 2 15 3 14 4 13 5 12 6 11 22 p F < 1 kΩ 5 0 Ω Im a ge F ilter 1 nF 1 nF IF O U T 4 70 Ω BUFFER 10 7 M IX E R LO IN RF AMP 3.3 nH 9 8 4 .7 nH 1 .8 p F 8 FRONT-ENDS Application Schematic 2400MHz, Buffered Output LN A R F IN VDD 10 0 nF 1 16 2 15 3 14 4 13 5 12 6 11 22 p F < 1 kΩ 5 0 Ω Im a ge F ilter 1 nF 1 nF IF O U T 4 70 Ω BUFFER 10 7 M IX E R LO IN 8 1 .8 nH Rev B1 010329 RF AMP 1.8 nH 9 0 .9 p F 8-49 RF2431 Evaluation Board Schematic 2400MHz (Download Bill of Materials from www.rfmd.com.) P1 P 1 -1 P 1 -3 C1 4 7 pF C2 10 0 nF L O IN J4 C4 1 nF R2 80 0 Ω R1 47 0 Ω FRONT-ENDS GND 2 43 14 00 R ev D T un ed for 2 .4 G H z LO M atch @ 2 .4 G H z 3 5 0 Ω µstrip 1 16 2 15 3 14 4 13 5 12 6 11 LN A O U T J2 C3 1 nF BUFFER 10 7 50 Ω µstrip M IX E R 8 L1 4 .7 n H 8-50 2 LNA P 1-1 8 VCC 5 0 Ω µstrip L N A IN J1 IF O U T J5 1 RF AMP L2 1 .8 nH 50 Ω µstrip 9 R F IN J3 C5 0.9 pF Rev B1 010329 RF2431 Evaluation Board Schematic 1800MHz P1 P 1 -1 P 1 -3 2 GND C1 4 7 pF C2 10 0 nF C4 1 nF 2 43 14 01 R ev D T un ed for 1 .8 G H z LO M atch @ 1 .8 G H z 3 5 0 Ω µstrip LNA P 1-1 L O IN J4 VCC 5 0 Ω µstrip L N A IN J1 IF O U T J5 1 R2 80 0 Ω R1 47 0 Ω 1 16 2 15 3 14 4 13 5 12 6 11 C3 1 nF BUFFER 10 7 5 0 Ω µstrip M IX E R 8 RF AMP L2 3 .3 nH 50 Ω µstrip 9 8 R F IN J3 C5 1.8 pF FRONT-ENDS L1 4 .7 n H LN A O U T J2 Rev B1 010329 8-51 RF2431 Evaluation Board Layout 2400MHz Evaluation Board Layout 1800MHz FRONT-ENDS 8 8-52 Rev B1 010329