FDMS7672 N-Channel PowerTrench® MOSFET 30 V, 5.0 mΩ Features General Description This N-Channel MOSFET has been designed specifically to improve the overall efficiency and to minimize switch node ringing of DC/DC converters using either synchronous or conventional switching PWM controllers. It has been optimized for low gate charge, low rDS(on), fast switching speed and body diode reverse recovery performance. Max rDS(on) = 5.0 mΩ at VGS = 10 V, ID = 19 A Max rDS(on) = 6.9 mΩ at VGS = 4.5 V, ID = 15 A Advanced Package and Silicon design for low rDS(on) and high efficiency Next generation enhanced body diode technology, engineered for soft recovery. Provides Schottky-like performance with minimum EMI in sync buck converter applications Applications IMVP Vcore Switching for Notebook MSL1 robust package design VRM Vcore Switching for Desktop and Server 100% UIL tested OringFET / Load Switch RoHS Compliant DC-DC Conversion Bottom Top S D D D Pin 1 S S G D 5 4 G D 6 3 S D 7 2 S D 8 1 S D Power 56 MOSFET Maximum Ratings TA = 25 °C unless otherwise noted Symbol VDS Drain to Source Voltage Parameter VGS Gate to Source Voltage (Note 4) Drain Current -Continuous (Package limited) ID TC = 25 °C -Continuous (Silicon limited) TC = 25 °C -Continuous TA = 25 °C PD TJ, TSTG Units V ±20 V 28 80 (Note 1a) 19 (Note 3) 72 -Pulsed A 90 Single Pulse Avalanche Energy EAS Ratings 30 Power Dissipation TC = 25 °C Power Dissipation TA = 25 °C 48 (Note 1a) Operating and Storage Junction Temperature Range 2.5 -55 to +150 mJ W °C Thermal Characteristics RθJC Thermal Resistance, Junction to Case RθJA Thermal Resistance, Junction to Ambient 2.6 (Note 1a) 50 °C/W Package Marking and Ordering Information Device Marking FDMS7672 Device FDMS7672 ©2009 Fairchild Semiconductor Corporation FDMS7672 Rev.D Package Power 56 1 Reel Size 13 ’’ Tape Width 12 mm Quantity 3000 units www.fairchildsemi.com FDMS7672 N-Channel PowerTrench® MOSFET April 2009 Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250 µA, VGS = 0 V ∆BVDSS ∆TJ Breakdown Voltage Temperature Coefficient ID = 250 µA, referenced to 25 °C IDSS Zero Gate Voltage Drain Current VDS = 24 V, VGS = 0 V 1 µA IGSS Gate to Source Leakage Current, Forward VGS = 20 V, VDS = 0 V 100 nA 3.0 V 30 V 15 mV/°C On Characteristics VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 µA ∆VGS(th) ∆TJ Gate to Source Threshold Voltage Temperature Coefficient ID = 250 µA, referenced to 25 °C -7 VGS = 10 V, ID = 19 A 3.6 5.0 rDS(on) Static Drain to Source On Resistance VGS = 4.5 V, ID = 15 A 5.2 6.9 VGS = 10 V, ID = 19 A, TJ = 125 °C 4.9 6.8 VDS = 5 V, ID = 19 A 64 gFS Forward Transconductance 1.25 2.0 mV/°C mΩ S Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Rg Gate Resistance VDS = 15 V, VGS = 0 V, f = 1 MHz 2225 2960 pF 685 910 pF 90 130 pF 0.7 1.5 Ω 13 23 ns Switching Characteristics td(on) Turn-On Delay Time tr Rise Time td(off) Turn-Off Delay Time tf Fall Time Qg VDD = 15 V, ID = 19 A, VGS = 10 V, RGEN = 6 Ω 5 10 ns 25 40 ns 4 10 ns Total Gate Charge VGS = 0 V to 10 V 31 44 nC VGS = 0 V to 4.5 V VDD = 15 V, ID = 19 A 14 19 nC 7.6 nC 3.7 nC Qg Total Gate Charge Qgs Gate to Source Charge Qgd Gate to Drain “Miller” Charge Drain-Source Diode Characteristics VGS = 0 V, IS = 2.1 A (Note 2) 0.7 0.95 VGS = 0 V, IS = 19 A (Note 2) 0.8 1.1 VSD Source to Drain Diode Forward Voltage trr Reverse Recovery Time 32 51 ns Qrr Reverse Recovery Charge 14 24 nC ta Reverse Recovery Fall Time 15 nC tb Reverse Recovery Rise Time 17 nC S Softness (tb/ta) 1.1 trr Reverse Recovery Time Qrr Reverse Recovery Charge IF = 19 A, di/dt = 100 A/µs IF = 19 A, di/dt = 300 A/µs V 26 42 ns 25 40 nC Notes: 1. RθJA is determined with the device mounted on a 1in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined by the user's board design. a. 50 °C/W when mounted on a 1 in2 pad of 2 oz copper. b. 125 °C/W when mounted on a minimum pad of 2 oz copper. 2. Pulse Test: Pulse Width < 300 µs, Duty cycle < 2.0%. 3. EAS of 72 mJ is based on starting TJ = 25 °C, L = 1 mH, IAS = 12 A, VDD = 27 V, VGS = 10 V. 100% test at L = 0.3 mH, IAS = 17 A. 4. As an N-ch device, the negative Vgs rating is for low duty cycle pulse occurrence only. No continuous rating is implied. FDMS7672 Rev. D 2 www.fairchildsemi.com FDMS7672 N-Channel PowerTrench® MOSFET Electrical Characteristics TJ = 25 °C unless otherwise noted 90 ID, DRAIN CURRENT (A) VGS = 5 V VGS = 4 V 60 PULSE DURATION = 80 µs DUTY CYCLE = 0.5% MAX VGS = 4.5 V 30 VGS = 3.5 V 0 0.0 0.5 1.0 1.5 6 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE VGS = 10 V PULSE DURATION = 80 µs DUTY CYCLE = 0.5% MAX 5 VGS = 3.5 V 4 VGS = 4 V 3 VGS = 4.5 V 2 1 2.0 0 30 VDS, DRAIN TO SOURCE VOLTAGE (V) 90 Figure 2. Normalized On-Resistance vs Drain Current and Gate Voltage 1.6 16 ID = 19 A VGS = 10 V rDS(on), DRAIN TO 1.4 1.2 1.0 0.8 0.6 -75 -50 SOURCE ON-RESISTANCE (mΩ) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 60 ID, DRAIN CURRENT (A) Figure 1. On Region Characteristics ID = 19 A PULSE DURATION = 80 µs DUTY CYCLE = 0.5% MAX 12 8 TJ = 125 oC 4 TJ = 25 oC 0 -25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (oC) 2 4 6 8 10 VGS, GATE TO SOURCE VOLTAGE (V) Figure 3. Normalized On Resistance vs Junction Temperature Figure 4. On-Resistance vs Gate to Source Voltage 90 100 IS, REVERSE DRAIN CURRENT (A) PULSE DURATION = 80 µs DUTY CYCLE = 0.5% MAX ID, DRAIN CURRENT (A) VGS = 10 V VGS = 5 V 0 VDS = 5 V 60 TJ = 150 oC 30 TJ = 25 oC TJ = -55 oC 1 2 3 4 10 TJ = 150 oC 1 5 TJ = 25 oC 0.1 0.01 TJ = -55 oC 0.001 0.0 0 0 VGS = 0 V 0.2 0.4 0.6 0.8 1.0 VGS, GATE TO SOURCE VOLTAGE (V) VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 5. Transfer Characteristics Figure 6. Source to Drain Diode Forward Voltage vs Source Current FDMS7672 Rev.D 3 1.2 www.fairchildsemi.com FDMS7672 N-Channel PowerTrench® MOSFET Typical Characteristics TJ = 25 °C unless otherwise noted 5000 ID = 19 A 8 VDD = 10 V CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE (V) 10 VDD = 15 V 6 VDD = 20 V 4 2 Ciss 1000 Coss 100 0 0 4 8 12 16 20 24 28 f = 1 MHz VGS = 0 V 1 Figure 7. Gate Charge Characteristics 90 TJ = ID, DRAIN CURRENT (A) 10 25 oC TJ = 100 oC TJ = 125 oC 60 VGS = 10 V VGS = 4.5 V 30 o RθJC = 2.6 C/W Limited by Package 1 0.01 0.1 1 10 0 25 100 50 P(PK), PEAK TRANSIENT POWER (W) 100 µs 1 ms 10 ms 0.1 100 ms 1s SINGLE PULSE TJ = MAX RATED 10 s RθJA = 125 oC/W DC TA = 25 oC 0.01 0.01 0.1 1 10 150 1000 VGS = 10 V 100 200 SINGLE PULSE Rθ JA = 125 oC/W TA = 25 oC 100 10 1 0.5 -4 10 -3 10 -2 10 -1 10 1 10 100 1000 t, PULSE WIDTH (sec) VDS, DRAIN to SOURCE VOLTAGE (V) Figure 11. Forward Bias Safe Operating Area FDMS7672 Rev.D 125 Figure 10. Maximum Continuous Drain Current vs Case Temperature 200 100 THIS AREA IS LIMITED BY rDS(on) 100 o Figure 9. Unclamped Inductive Switching Capability 10 75 TC, CASE TEMPERATURE ( C) tAV, TIME IN AVALANCHE (ms) 1 30 Figure 8. Capacitance vs Drain to Source Voltage 50 IAS, AVALANCHE CURRENT (A) 10 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) ID, DRAIN CURRENT (A) Crss 50 0.1 32 Figure 12. Single Pulse Maximum Power Dissipation 4 www.fairchildsemi.com FDMS7672 N-Channel PowerTrench® MOSFET Typical Characteristics TJ = 25 °C unless otherwise noted 2 NORMALIZED THERMAL IMPEDANCE, ZθJA 1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 0.1 PDM t1 t2 0.01 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA SINGLE PULSE o RθJA = 125 C/W 0.001 -4 10 -3 -2 10 -1 10 10 1 10 100 1000 t, RECTANGULAR PULSE DURATION (sec) Figure 13. Junction-to-Ambient Transient Thermal Response Curve Figure 15. 20 16 CURRENT (A) di/dt = 300 A/µs 12 8 4 0 -4 0 25 50 75 100 125 150 TIMES (nS) Figure 14. Body Diode Reverse Recovery Characteristics FDMS7672 Rev.D 5 www.fairchildsemi.com FDMS7672 N-Channel PowerTrench® MOSFET Typical Characteristics TJ = 25 °C unless otherwise noted FDMS7672 N-Channel PowerTrench® MOSFET Dimensional Outline and Pad Layout FDMS7672 Rev.D 6 www.fairchildsemi.com tm tm tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. 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