CY2048WAF Flash Programmable Capacitor Tuning Array Die for Crystal Oscillator(XO) Features Benefits • Flash-programmable capacitor tuning array for low ppm initial frequency clock output • Enables fine-tuning of output clock frequency by adjusting CLoad of the crystal • Low clock output jitter • Allows multiple programming opportunities to correct errors, and control excess inventory — 4 ps typ. RMS period jitter • Enables programming of output frequency after packaging — ±30 ps typ. peak-to-peak period jitter • Flash-programmable dividers • PPM clock output error can be adjusted in package • Two-pin programming interface • Provides flexibility in output configurations and testing • On-chip oscillator runs from 10–48-MHz crystal • Enables low-power operation or output enable function • Five selectable post-divide options, using reference oscillator output • Provides flexibility for system applications through selectable instantaneous or synchronous change in outputs • Programmable asynchronous or synchronous OE and PWR_DWN modes • Enables encapsulation in small-size, surface-mount packages • 2.7V to 3.6V operation • Controlled rise and fall times and output slew rate Block Diagram PD#/OE (SDATA/VPP) CONFIGURATION XIN CRYSTAL XOUT OSCILLATOR OUT (SCL) / 1, 2, 4, 8, 16 VDD VSS Die Pad Description H o riz o n ta l S c rib e 1 VDD 2 XOUT 3 X IN 4 P D # /O E Notes: OUT 6 X(max): 980 µm, Y(max): 988 µm Y (m a x ) V e rtic a l S c rib e 7C80330A VSS Scribe: X = 70 µm, Y = 86 µm Bond pad opening: 85 µm x 85 µm Pad pitch: 175 µm (min.) 5 d ie # /re v Wafer thickness: 11 mils (Typ.) X (m a x ) Cypress Semiconductor Corporation Document #: 38-07738 Rev. *A • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised December 12, 2005 CY2048WAF Die Pad Summary (Pad coordinates are referenced from the center of the die (X = 0, Y = 0)) X coordinate (µm) Y coordinate (µm) VDD Name Pad Number 1 Voltage Supply –360.8 353.7 XOUT 2 Oscillator Drain –360.8 134.1 XIN 3 Oscillator Gate –360.8 –42.6 PD#/OE 4 Programmable power-down or output enable pin –360.8 –275.9 360.0 353.7 360.0 –354.5 VPP High voltage for programming NV memory SDATA OUT Serial data pin used for programming in test mode 6 SCL VSS Description Clock output Serial clock for programming in test mode 5 Ground Document #: 38-07738 Rev. *A Page 2 of 7 CY2048WAF Absolute Maximum Conditions Output Short Circuit Current ..................................... ± 50 mA Storage Temperature (Non-condensing) .... –55°C to +125°C (Above which the useful life may be impaired. For user guidelines, not tested.) Junction Temperature ................................ –40°C to +125°C Supply Voltage (VDD) ........................................–0.5 to +7.0V Data Retention @ Tj = 125°C................................> 10 years DC Input Voltage...................................... –0.5V to VDD + 0.5 ESD (Human Body Model) MIL-STD-883................. > 2000V Crystal Specifications[1] Description Comments FNOM Parameter Nominal crystal frequency Fundamental mode, AT cut Min. Typ. R1 Equivalent series resistance (ESR) Fundamental mode R3/R1 Ratio of third overtone mode ESR to fundamental mode ESR Ratio used because typical R1 values are much less than the maximum spec C0 C1 Max. Unit 10 – 48 MHz – – 40 Ω 4.5 – – – Crystal shunt capacitance – – 5 pF Crystal motional capacitance 2 – – fF Operating Conditions Min. Typ. Max. Unit VDD Parameter Operating Voltage Description 2.7 – 3.6 V TJ Junction Temperature –40 – 125 °C CXIN Capacitance XIN, all tuning caps OFF – 10 – pF CXOUT Capacitance XOUT, all tuning caps OFF – 10 – pF CL All tuning Caps OFF 4 5 6 pF All tuning Caps ON 9.2 10 11.4 pF – – 15 pF COUT Output Load Capacitance tRAMP Power-up time for VDD to reach minimum specified voltage (power ramps must be monotonic) 0.05 – 500 ms TS Start up time, 90% VDD to valid frequency on output – – 10 ms DC Electrical Specifications TJ = –40 to 125°C over the operating range Parameter Description Condition Min. Typ. Max. Unit VIL Input Low Voltage CMOS Levels – – 20 %VDD VIH Input High Voltage CMOS Levels 80 – – %VDD VOL Output Low Voltage VDD = 2.7V–3.6V, IOL = 8 mA – – 0.4 V VOH Output High Voltage VDD = 2.7V–3.6V, IOL = –8 mA VDD–0.4 – – V IIL Input Low Current Input = VSS – 1 10 µA IIH Input High Current Input = VDD – 1 10 µA IOZL Output Leakage Current Output = VSS – 1 10 µA IOZH Output Leakage Current Output = VDD – – 50 µA IDD Power Supply Current No Load, VDD = 3.3V, 48 MHz – – 20 mA IPD Power Down Current PD# = 0V – – 25 µA RUP Input Pull-up resistor VIN = VSS 1 3 6 MΩ VIN> = 0.8VDD 80 120 150 kΩ RDN Output Pull-down resistor VIN = 0.5VDD 500 900 1500 kΩ CIN Input Pin Capacitance PD#/OE pin – – 7 pF RF Crystal Feedback R XIN = 0 300 – 800 kΩ Note: 1. Not 100% tested. Document #: 38-07738 Rev. *A Page 3 of 7 CY2048WAF AC Electrical Specifications[1] over the operating range, except as noted Parameter[1] Description Condition Min. Typ. Max. Unit 0.625 – 48 MHz 45 50 55 % FOUT Output Frequency DC Output Duty Cycle XTAL Buffered or Divided TR Rise Time Output Clock Rise Time, Measured from 20% to 80% of VDD, COUT = 15 pF. 2.5 ns TF Fall Time Output Clock Fall Time, Measured from 80% to 20% of VDD, COUT = 15 pF. 2.5 ns tPJ1 RMS Period Jitter XIN = 10–48 MHz. Measured at VDD/2 – 4 15 ps tPJ2[2] Peak-to-peak Period Jitter XIN = 10–48 MHz. Measured at VDD/2 – 30 80 ps DL Crystal drive level 48-MHz crystal, CL = 7 pF, C0 = 2 pF, R1 = 10 Ohms, Temp. = 25°C, VDD = 3.6V –R Negative Resistance Measured at 48 MHz, CL = 10 pF, C0 = 5 pF – – –150 Ω FDRIFT Output Frequency Drift 3.0V ± 10%, 3.3V ± 10% for Temp. = 25°C –2 – 2 ppm µW 350–400 Phase Noise, Temp = 25°C, VDD = 3.3V, FNOM = 10MHz, XCAP = 7F (Hex) Offset dBc/Hz (Typ) 10 Hz –90 100 Hz –115 1 kHz –130 10 kHz –140 100 kHz –140 1 MHz –140 Crystal Oscillator Tuning Capacitor Values Capacitor Bit Capacitance (pF) per Side C7 5.000 C6 2.500 C5 1.250 C4 0.625 C3 0.313 C2 0.156 C1 0.078 C0 0.039 XIN XOUT CXOUT CXIN C7 C6 C5 C4 C3 C2 C1 C0 C0 C1 C2 C3 C4 C5 C6 C7 Figure 1. Programmable Load Capacitance Notes: 2. TPJ2 measured using DTS-2075, # of events set to 10, 000. Document #: 38-07738 Rev. *A Page 4 of 7 CY2048WAF Timing Parameters over the operating range Parameter Description Min. Max. Unit TSTP,SYNC Time from falling edge on PD# to stopped output, synchronous mode, T=1/Fout TSTP,ASYNC Time from falling edge on PD# to stopped output, asynchronous mode TPU,SYNC Time from rising edge on PD# to output at valid frequency, synchronous mode, T = 1/Fout TPU,ASYNC Time from rising edge on PD# to output at valid frequency, asynchronous mode TPZX,SYNC Time from rising edge on OE to running output, synchronous mode, T=1/Fout TPZX,ASYNC Time from rising edge on OE to running output, asynchronous mode TPXZ,SYNC Time from falling edge on OE to high impedance output, synchronous mode, T = 1/Fout TPXZ,ASYNC Time from falling edge on OE to high impedance output, asynchronous mode 350 ns 1.5T + 350 ns 350 ns 3 ms 3 ms 1.5T + 350 ns 350 ns 1.5T + 350 ns PD TPU CLOCK SYNC Weakly pulled LOW TSTP Weakly pulled LOW CLOCK ASYNC T TSTP Figure 2. Power-down Timing OE CLOCK SYNC Weakly pulled LOW T PZX TPXZ Weakly pulled LOW CLOCK ASYNC T TPXZ T PZX Figure 3. Output Enable Timing VDD - 10% POWER TS 0V tRAMP OUT Figure 4. VDD Power-up Timing Document #: 38-07738 Rev. *A Page 5 of 7 CY2048WAF Test and Measurement Set-up VDD Output 0.1 µF CLOAD DUT GND Voltage and Timing Definitions t1 t2 VDD 50% of VDD Clock Output 0V Figure 5. Duty Cycle Definition tF tR V DD 80% of V DD 20% of VDD Clock Output 0V Figure 6. Ordering Information Ordering Code CY2048WAF[3] Package Type Wafer Operating Range (TJ) Industrial,–40 °C to 125°C Note: 3. The product is offered as tested die-on-wafer form. Contact Cypress Sales for additional programming information and support. All product or company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07738 Rev. *A Page 6 of 7 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY2048WAF Document History Page Document Title: CY2048WAF Flash Programmable Capacitor Tuning Array Die for Crystal Oscillator(XO) Document Number: 38-07738 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 319840 See ECN RGL New data sheet *A 413511 See ECN RGL Minor Change: Pls. post in the web Document #: 38-07738 Rev. *A Page 7 of 7