HA16150T/P High-Speed Current Mode Push-Pull PWM Control IC REJ03F0146-0300 Rev.3.00 Jan 30, 2007 Description The HA16150 is a high-speed current mode PWM control IC with push-pull dual outputs, suitable for high-reliability, high-efficiency, high-mounting-density isolated DC-DC converter and high-output AC-DC converter control. The HA16150 can be used in various applications, including push-pull converters and half-bridge, double-forward, and single-forward applications. The HA16150 incorporates 180-degree phase-inverted push-pull dual outputs, and directly drives a power MOS FET. Operation at a maximum of 1 MHz is possible on an oscillator reference frequency. The package lineup comprises an ultra-thin surface-mount TSSOP-16 suitable for slim communication system modules, and a general-purpose insertion DILP-6 suitable for characteristics evaluation. Features <Maximum Ratings> Supply voltage Vcc: 20 V Peak output current Ipk-out: ±1.0 A Operating junction temperature Tjopr: –40°C to +125°C <Electrical Characteristics> VREF output voltage VREF: 5.0 V ± 1% UVLO start threshold VH: 9.3 V ± 0.7 V UVLO shutdown threshold VL: 8.3 V ± 0.7 V Operating current Icc: 4 mA typ. Standby current Is: 150 µA typ. <Functions> Soft start (one external timing capacitance) Remote on/off control Independent dead band time adjustment Current limiter adjustment (set drooping characteristic adjustment) Push-pull/single-end output switching Package lineup: TSSOP-16/DILP-16 Rev.3.00 Jan 30, 2007 page 1 of 24 HA16150T/P Pin Arrangement INP 1 16 VREF INM 2 15 REMOTE EOUT 3 14 VCC CSLIM 4 13 OUT2 CS 5 12 PGND RT 6 11 OUT1 CT 7 10 TDB SS 8 9 SGND (Top view) Pin Functions Pin No. Pin Name Pin Functions 1 2 INP INM Error amplifier non-inverted (+) input Error amplifier inverted (–) input 3 4 EOUT CSLIM Error amplifier output Current limiter level adjustment 5 6 CS RT Current sense signal input Operating frequency setting resistance connection 7 8 CT SS Operating frequency setting capacitance connection Soft start time setting timing capacitance connection 9 10 SGND TDB Small signal system ground Dead band time setting timing capacitance connection 11 12 OUT1 PGND Power MOS FET driver output 1 Power system ground 13 14 OUT2 VCC Power MOS FET driver output 2 Supply voltage 15 16 REMOTE VREF Remote on/off control Reference voltage Rev.3.00 Jan 30, 2007 page 2 of 24 HA16150T/P Block Diagram VREF 16 VCC 14 VREF 22.2V 300µA Vref Generator UVL REMOTE 15 REMOTE Comp. VREF 1.1V Vref good Vref Good Vref good R Q S Q UVL TDB Comp. 0.5V Single End Comp. 5µA 10 TDB SS 8 SS Comp. S Q R Q 4V TDB Latch Vcc SS Ramp Vref good SS Ramp 11 OUT1 CT PGND VREF VREF RT 6 D Driver Vcc Q CK Q CT 7 13 OUT2 1/2 Divider Vref good 12 PGND Oscillator R Q S Q Blanking Pulse IN CS Latch Vcc OUT 5 CS VREF CS Comp. 400µA 2R INM 2 R (VCOMP-2VF)/3 9 SGND E-Amp. INP 1 1.4V 3 4 EOUT CSLIM Rev.3.00 Jan 30, 2007 page 3 of 24 65ns Blanking Enable Comp. HA16150T/P Absolute Maximum Ratings (Ta = 25°C) Item Power supply voltage Symbol Ratings 20 Unit V Vcc OUT1 output current (peak) OUT2 output current (peak) Ipk-out1 Ipk-out2 ±1.0 ±1.0 A A OUT1 output current (DC) OUT2 output current (DC) Idc-out1 Idc-out2 ±0.1 ±0.1 A A OUT1 output voltage OUT2 output voltage Vout1 Vout2 –0.3 to Vcc –0.3 to Vcc V V INM pin voltage REMOTE pin voltage Vinm Vremote –0.3 to Vcc –0.3 to Vcc V V REMOTE pin current INP pin voltage Iremote Vinp +0.2 –0.3 to Vcc mA V SS pin voltage RT pin voltage Vss Vrt –0.3 to Vref –0.3 to Vref V V RT pin current CT pin voltage Irt Vct –0.2 –0.3 to Vref mA V CSLIM pin voltage EOUT pin voltage Vcslim Veout –0.3 to Vref –0.3 to Vref V V VREF pin voltage TDB pin voltage Vref Vtdb –0.3 to Vref –0.3 to Vref V V CS pin voltage Operating junction temperature Vcs Tj-opr –0.3 to Vref –40 to +125 V °C Storage temperature Tstg –55 to +150 Notes: 1. Rated voltages are with reference to the GND (SGND, PGND) pin. 2. For rated currents, inflow to the IC is indicated by (+), and outflow by (–). 3. Shows the transient current when driving a capacitive load. 4. HA16150T (TSSOP): θja = 250°C/W This value is based on actual measurements on a 110% wiring density glass epoxy circuit board (55 mm × 45 mm × 1.6 mm). HA16150P (DILP): θja = 124°C/W Rev.3.00 Jan 30, 2007 page 4 of 24 °C Note 3 3 4 HA16150T/P Electrical Characteristics (Ta = 25°C, Vcc = 12 V, Fosc = 100 kHz) Supply VREF Oscillator PWM Comparator Error amplifier Current sense Remote Item Start threshold Symbol VH Min 8.6 Typ 9.3 Max 10.0 Unit V Shutdown threshold UVLO hysteresis VL dVUVL 7.6 0.7 8.3 1.0 9.0 1.3 V V Start-up current Operating current Is Icc 100 – 150 4 250 6 µA mA Vcc zenner shunt voltage Vz temperature stability Vz 21.2 22.2 23.2 V dVz/dTa – 4.5 – mV/°C Output voltage Line regulation Vref Vref-line 4.95 – 5.0 5 5.05 20 V mV Load regulation Temperature stability Vref-load dVref/dTa – – 5 80 20 – mV ppm/°C Oscillator frequency fosc 88 100 112 kHz Temperature stability dfosc/dTa – ±0.1 – %/°C High voltage Low voltage Vth Vtl – – 3.0 2.0 – – V V DC * 1 DC * Differential voltage Input bias current dVt Ifb – –1 1.0 – – +1 V µA DC * Open loop gain EOUT sink current Av Isnk-eout – – 70 3.0 – – dB mA f = 1.0kHz * 1 Veout = 1.1V * EOUT source current Low voltage Isrc-eout – –0.4 – mA Veout = 3.0V * Vol-eout – 0.8 1.1 V EOUT : Open High voltage Voltage gain Voh-eout Avcs 4.7 2.85 5.0 3.00 – 3.15 V V/V EOUT : Open Delay to output Leading edge blanking time td-cs tbl – – 150 65 230 – ns ns * Leading edge blanking disable voltage On threshold voltage Vbl-off 1.3 1.4 1.5 V Measured pin : EOUT Von 1.40 – – V * Voff – – 3.00 V * Iremote 60 90 120 µA Vremote = 4V –7.0 –5.0 –3.0 µA Vss = 1V Off threshold voltage Sink current Soft start Source current Iss Note: 1. Reference values for design. Rev.3.00 Jan 30, 2007 page 5 of 24 Test Conditions Vcc = 8V Vinm = 1.0V, Vinp = 1.25V, Vcs = 0V Icc = 10mA 1 Icc = 10mA * Iref = –1mA Vcc = 11V to 18V Iref = –1mA to –20mA Ta = –40 to 125°C Measured at OUT1 and OUT2 RT = 27kΩ, CT = 1000pF 1 Ta = –40 to 125°C * 1 1 1 1 1 1 1 HA16150T/P Electrical Characteristics (cont.) (Ta = 25°C, Vcc = 12 V, Fosc = 100 kHz) OUT1 OUT2 Dead-band time Note: Item Minimum duty cycle Symbol Dmin-out1 Min – Typ – Max 0 Unit % Test Conditions Veout = 0V Maximum duty cycle Rise time Dmax-out1 48 49 – % TDB : OPEN tr-out1 – 30 65 ns CL = 1000pF Fall time Low voltage tf-out1 Vol1-out1 – – 30 0.05 65 0.2 ns V CL = 1000pF Iout = 20mA High voltage Vol2-out1 Voh1-out1 – 11.5 0.5 11.9 2.0 – V V Iout = 200mA (pulse) Iout = –20mA Minimum duty cycle Voh2-out1 Dmin-out2 10.0 – 11.0 – – 0 V % Iout = –200mA (pulse) Veout = 0V Maximum duty cycle Rise time Dmax-out2 48 49 – % TDB : OPEN tr-out2 – 30 65 ns CL = 1000pF Fall time Low voltage tf-out2 Vol1-out2 – – 30 0.05 65 0.2 ns V CL = 1000pF Iout = 20mA High voltage Vol2-out2 Voh1-out2 – 11.5 0.5 11.9 2.0 – V V Iout = 200mA (pulse) Iout = –20mA Dead-band time Voh2-out2 tdb0 10.0 – 11.0 60 – – V ns Iout = –200mA (pulse) 1 TDB : OPEN * – 140 – ns Ctdb = 47pF * tdb 1. Reference values for design. Rev.3.00 Jan 30, 2007 page 6 of 24 1 HA16150T/P Timing Diagram 1. Start-up Timing 9.3V 8.3V VCC VREF 3V V_CT 2V RESET (internal signal) Q (internal signal) Q (internal signal) V_TDB term. V_TDB comp. out (internal signal) tdb tdb Dead-band pulse (internal signal) OUT1 OFF ON OFF ON OFF ON OFF ON OFF ON OUT2 ON OFF ON OFF ON OFF ON OFF ON OFF Rev.3.00 Jan 30, 2007 page 7 of 24 ON HA16150T/P 2. Current Sense VREF 3V V_CT 2V RESET (internal signal) Dead-band pulse (internal signal) Q (internal signal) Q (internal signal) V_EOUT V_CS V_CS comp.(−) OUT1 OUT2 Rev.3.00 Jan 30, 2007 page 8 of 24 V_CS comp.(−) = (V_EOUT − 2VF) / 3 HA16150T/P 3. Soft Start VREF 3V V_CT 2V RESET (internal signal) V_TDB term. Dead-band pulse (internal signal) V_SS SS comp. IN+ (internal signal) SS comp. out (internal signal) OUT1 OUT2 Rev.3.00 Jan 30, 2007 page 9 of 24 HA16150T/P 4. Leading Edge Blanking 3V V_CT 2V RESET (internal signal) Dead-band pulse (internal signal) Q (internal signal) Q (internal signal) V_EOUT 1.4V V_CS V_CS comp.(−) (internal signal) Blanking pulse (internal signal) V_CS comp.(+) (internal signal) OUT1 OUT2 Rev.3.00 Jan 30, 2007 page 10 of 24 Blanking Time reset HA16150T/P 5. Push-Pull/Single-End Switching (1) Push-pull operation: Leave the TDB pin open or connect a capacitance to GND 3V V_CT 2V RESET (internal signal) V_TDB term. Dead-band pulse (internal signal) OUT1 OUT2 (2) Single-end operation: Perform pull-up connection of the TDB pin to the VREF pin 3V V_CT 2V RESET (internal signal) 5V V_TDB term. Dead-band pulse (internal signal) 0V OUT1 OUT2 0V Rev.3.00 Jan 30, 2007 page 11 of 24 HA16150T/P Functional Description 1. UVL Circuit The UVL circuit monitors the Vcc voltage and halts operation of the IC in the event of a low voltage. The voltage for detecting Vcc has a hysteresis characteristic, with 9.3 V as the start threshold and 8.3 V as the shutdown threshold. When the IC has been halted by the UVL circuit, control is performed to fix driver circuit output low, halt VREF output and the oscillator, and reset the soft start circuit. 9.3V VCC 8.3V 4.5V VREF 4.5V 3V V_CT 2V V_SS OUT1 OUT2 Figure 1 2. Remote ON/OFF Circuit A remote on/off control function is incorporated, enabling the IC to be halted without cutting the supply voltage by pulling the REMOTE pin up to 3.0 V or higher. This function halts VREF output and driver output. At this time the IC enters Remote-OFF mode and IC current dissipation can be decreased. This function can thus be used for power management, etc. When remote off control is performed, the soft start circuit is also reset, and therefore a soft start is effected when restarting, preventing overshoot. However, when restarting by the remote on control function before the SS pin is completely discharged, soft start operation may not be performed normally. In such a case, add a circuit to pull the SS pin out in conjunction with a remote off signal. SS REMOTE 100kΩ Figure 2 Example of Circuit to Pull out SS Pin Rev.3.00 Jan 30, 2007 page 12 of 24 HA16150T/P If the remote on/off control function is not used, the REMOTE pin should be permanently pulled down to GND with a resistance of about 100 kΩ. The remote on/off control function halts only reference voltage. Other functions will be stopped when the reference voltage is below 4.5 V (typ.). Large stabilizing capacitance of the VREF pin results in a difference between the timing of remote off signal and the timing to stop the IC (1) VREF is halted by REMOTE. 4.5V(Typ) (2) When VREF is blow 4.5 V(Typ), other functions are stopped. CH3: REMOTE CH4: VREF CH1: SS CH2: OUT1 Figure 3 Operation When Remote is Off (Reference Data) 3. Soft Start Circuit This function gradually increases the pulse width of the OUT pin from 0% duty at start-up to prevent a sudden increase in the pulse width that may cause problems such as transient stress on external parts or overshoot of the secondary-side output voltage. The soft start time can easily be set with a single external capacitance. V_CT V_SS SS comp. IN+ (internal signal) 1.1V SS comp. out OUT1 OUT2 Figure 4 Rev.3.00 Jan 30, 2007 page 13 of 24 HA16150T/P Soft start time tss is determined by SS pin connection capacitance Css and an internal constant, and can be estimated using the equation shown below. Soft start time tss is the time until the first pulse is output to the driver output OUT pin after VREF starts up following UVLO release. This is equivalent to the time until the SS pin voltage reaches IC-internal SS comparator reference voltage VTL (1.1 V), and can be calculated using the approximate equation shown below. Soft start time tss when Css is 1000pF is given by the following equation. tss = Css × VTL = Iss 1000 [pF] × 1.1 [V] 5 [µA] ≈ 220 [µs] * Iss: SS pin source current, 5 µA typ. Note: A soft start circuit operates only once at the start-up of the IC (after the VREF pin voltage is launched and the VrefGOOD circuit is operated). If the SS pin is lowered to 1.1 V or less after the SS pin becomes once high, the pulse of OUT1 and OUT2 is not halt. Each duty cycle of OUT1 and OUT2 is fixed to 25%. 4. Dead Band Generation Circuit "Dead band" refers to the time when both push-pull dual outputs are off. By setting the dead band time arbitrarily, it is possible to configure a system in which the dual outputs are never on simultaneously with respect to input and load variations. V_CT 0.5V V_TDB SS comp. out (internal signal) OUT1 OUT2 Figure 5 Dead band time tdb is determined by TDB pin connection capacitance Cdb and an internal constant, and can be estimated using the equation shown below. Even when the TDB pin is open, the dead band time does not become zero due to floating capacitance of the IC package, etc. This dead band time is designated tdb0. Dead band time tdb when Cdb is 47 pF is given by the following equation. tdb = tdb0 + 47 [pF] × 0.5 [V] Cdb × Vth = tdb0 + 300 [µA] Idb = 60 [ns] + 78 [ns] = 138 [ns] * Idb: TDB pin source current, 300 µA typ. * Vth: IC-internal TDB comparator reference voltage Rev.3.00 Jan 30, 2007 page 14 of 24 HA16150T/P 5. Operating Frequency The operating frequency is adjusted by means of CT and RT. Adjustment examples are shown in the graph below. This graph shows driver output operating frequencies. The reference operating frequency generated at the CT pin is twice the driver output frequency. The driver output operating frequency can be estimated using the approximate equation shown below. This is only an approximate equation, and the higher the frequency, the greater will be the degree of error of the approximate equation due to the effects of CT pin voltage overshoot, undershoot and so forth. When the operating frequency is adjusted, it is essential to confirm operation using the actual system. 8 8 = 3 × CT × RT 3 × C6 × R7 8 = 3 × 470 [pF] × 27 [kΩ] fosc = = 210 [kHz] 10000 fosc (RT = 5.1kΩ) fosc (RT = 10kΩ) fosc (RT = 27kΩ) fosc (RT = 75kΩ) fosc (kHz) 1000 100 0 100 1000 CT (pF) Figure 6 Rev.3.00 Jan 30, 2007 page 15 of 24 10000 HA16150T/P 6. Current Limiter Level The drooping characteristic of the power supply output can be adjusted by adjusting the CSLIM pin voltage. For example, the drooping characteristic can easily be adjusted, as shown in the figure below, by setting VREF to a divided value with resistances R1 and R2 and connecting adjustment resistance Rx in parallel to R2. Rx R2 12k Vref 16 Vcc − + VREF R1 15k 5 CS CS Comp. − + E-amp. 2R R 3 EOUT 4 CSLIM Figure 7 CSLIM Peripheral Circuit The graph below shows examples of power supply output drooping characteristic adjustment in a push-pull converter. As shown in this graph, the point at which the power supply output current limit begins to be applied can be adjusted by adjustment of the CSLIM pin voltage. 3.60 Rx: 24k (VCSLIM = 1.75V) 3.40 Rx: 33k (VCSLIM = 1.85V) Rx: open (VCSLIM = 2.22V) Vout (V) 3.20 3.00 2.80 Rx: 47k (VCSLIM = 1.95V) Rx: 15k (VCSLIM = 1.55V) 2.60 2.40 2.20 2.00 0.0 2.0 4.0 6.0 8.0 10.0 Iout (A) Figure 8 Adjustment of Power Supply Output Drooping Characteristic Rev.3.00 Jan 30, 2007 page 16 of 24 HA16150T/P 7. VREF Circuit (1) For the VREF pin, make sure to connect stabilizing capacitance to GND. (2) When the value of stabilizing capacitance is small or the load of VREF pin is heavy, either OUT1 or OUT2 may be halted at high level if the IC is stopped by a remote off function. In such a case, increase the capacitance value. The minimum value of capacitance to be connected is approximated by the following equation. Cref > 10µs × (Iref + 6mA) 4.95V (3) Depending on the value of capacitance to be connected, overshoot may result at the rising of the VREF pin (see the figure below). Take extra care when the VREF pin voltage is used as the power supply and reference voltage of external circuit. Overshoot voltage (V) 1.0 0.8 0.6 0.4 0.2 0 1E–9 10E–9 100E–9 1E–6 10E–6 Vref pin capacitance (F) Figure 9 Overshoot Voltage of Vref Pin (Reference Data) 8. CS Pin RC filter is generally inserted into the CS pin to prevent the pin from malfunction due to noise. The CS pin has an internal circuit to pull out electric charge while both of the OUT1 and OUT2 are at the low level (dead band time). However, please be aware that the electric charge may not be pulled out when the duration of dead band time is short and the filter constant is not appropriate. Rev.3.00 Jan 30, 2007 page 17 of 24 HA16150T/P 9. Usage on Half-bridge Power Supply The HA16150 is operated in the current mode. However, the half-bridge power supply becomes unstable in principle by using current mode control. The HA16150, therefore, cannot be used basically. In order to use the HA16150 with the half-bridge power supply, add a circuit as shown below and operate the HA16150 in the voltage mode. VREF R1 R2 OUT1 Q1 Q2 OUT2 C2 C1 CS input filter Vslope R3 Dead Band Time 1/fosc OUT1 OUT2 (CSLIM – 2VF) 3 CS Figure 10 Example of Circuit for Voltage Mode Operation Design the charging circuits for R1 (R2), C1 (C2), Q1 (Q2) and R3 so that the peak voltage of CS is lower than (CSLIM-2VF)/3 at the maximum ON pulse width of OUT1 and OUT2. Furthermore, set the input filter values between R3 and CS pin so that the CS voltage is discharged assuredly while both of the OUT1 and OUT2 are at low level. Rev.3.00 Jan 30, 2007 page 18 of 24 HA16150T/P Characteristic Curves Power Supply Current vs. Power Supply Voltage Characteristics 6.0 Ta = 25°C fosc = 100kHz 5.0 Icc (mA) 4.0 3.0 2.0 1.0 0.0 7.0 7.5 8.0 8.5 9.0 9.5 10.0 Vcc (V) Standby Current vs. Power Supply Voltage Characteristics 1.0 Ta = 25°C fosc = 100kHz Is (mA) 0.8 0.6 0.4 0.2 0.0 0 1 2 3 4 5 Vcc (V) Rev.3.00 Jan 30, 2007 page 19 of 24 6 7 8 9 10 HA16150T/P Power Supply Current vs. Power Supply Voltage (Clamp Zener Voltage) Characteristics 18.0 Ta = 25°C 16.0 fosc = 100kHz Icc (mA) 14.0 12.0 10.0 8.0 6.0 4.0 20.0 20.5 21.0 21.5 22.0 22.5 23.0 Vcc (V) VREF Output Voltage vs. REMOTE Pin Voltage Characteristics 6.0 Ta = 25°C 5.0 VREF (V) 4.0 3.0 2.0 1.0 0.0 0.0 0.5 1.0 1.5 2.0 VREMOTE (V) Rev.3.00 Jan 30, 2007 page 20 of 24 2.5 3.0 3.5 4.0 HA16150T/P VREF Output Voltage vs. Ambient Temperature Characteristics 5.20 Iref = 1mA 5.15 VREF (V) 5.10 5.05 5.00 4.95 4.90 4.85 4.80 −50 −25 0 25 50 75 100 125 Ta (°C) Operating Frequency vs. Ambient Temperature Characteristics 120 RT = 27kΩ CT = 1000pF fosc (kHz) 110 100 90 80 −50 −25 0 25 50 Ta (°C) Rev.3.00 Jan 30, 2007 page 21 of 24 75 100 125 HA16150T/P UVL Start-up Voltage vs. Ambient Temperature Characteristics 10.0 9.8 9.6 VH (V) 9.4 9.2 9.0 8.8 8.6 8.4 8.2 8.0 −50 −25 0 25 50 75 100 125 Ta (°C) UVL Shutdown Voltage vs. Ambient Temperature Characteristics 9.0 8.8 8.6 8.4 VL (V) 8.2 8.0 7.8 7.6 7.4 7.2 7.0 −50 −25 0 25 50 Ta (°C) Rev.3.00 Jan 30, 2007 page 22 of 24 75 100 125 HA16150T/P Application Circuit Example The following diagram shows a sample application circuit for a push-pull converter with a 48 V input voltage, 3.3 V output voltage, and 10 A output current. L2 1.5µH R14 R18 680 390 Core : PQ20/16 Bobin : BPQ20/16-1114CP + Vin 48V 2T 10T 2T R15 R19 2k 1k C12 R17 0.033µ 3.3k R10 15k C3 0.1µ C2 47µ/100V 10T OUT(+) + C13 470µ/10V R16 5.1k HA17431VP OUT(–) D3 20V L1 100µ D2 IS2076A C9+ 4.7µ C10+ 0.1µ D1 IS2076A VREF 16 7T VCC 14 VREF 22.2V R8 120k 300µA Vref Generator REMOTE UVL 15 R9 120k REMOTE Comp. Vref good 1.1V VREF Vref good Vref Good R Q S Q UVL TDB Comp. 0.5V Single End Comp. 5µA 10 TDB SS 8 C7 1000p SS Comp. S Q R Q 4V TDB Latch Vcc SS Ramp Vref good SS Ramp 11 R12 OUT1 10 H5N2001LS CT PGND VREF RT R7 27k VREF 6 D CT Driver Vcc Q CK Q 7 C7 1000p 13 1/2 Divider Vref good 12 Oscillator R Q S Q R11 OUT2 10 PGND Blanking Pulse IN CS Latch Vcc OUT CS Comp. 400µA 2R VREF INM R6 5.1k 2 INP 9 E-Amp. 1 1.4V 3 VREF 4 EOUT CSLIM R5 5.1k C4 0.01µ R1 15k VREF R2 12k C14 6800p Photo Coupler Rev.3.00 Jan 30, 2007 page 23 of 24 Blanking Enable Comp. R4 1k CS C5 680p R (VCOMP-2VF)/3 R3 5.1k 65ns 5 VREF SGND R13 0.15/2W HA16150T/P Package Dimensions As of January, 2003 19.20 20.00 Max Unit: mm 1 7.40 Max 9 6.30 16 8 1.3 0.48 ± 0.10 7.62 2.54 Min 5.06 Max 2.54 ± 0.25 0.51 Min 1.11 Max + 0.13 0.25 – 0.05 0° − 15° Package Code JEDEC JEITA Mass (reference value) JEITA Package Code P-TSSOP16-4.4x5-0.65 RENESAS Code PTSP0016JB-B *1 Previous Code TTP-16DA DP-16 Conforms Conforms 1.07 g MASS[Typ.] 0.05g D F 16 9 NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. bp c c1 *2 E HE b1 Index mark Terminal cross section 1 Reference Symbol 8 *3 Z bp x M L1 A e A1 θ y Rev.3.00 Jan 30, 2007 page 24 of 24 L Detail F D E A2 A1 A bp b1 c c1 θ HE e x y Z L L1 Dimension in Millimeters Min Nom Max 5.00 5.30 4.40 0.03 0.07 0.10 1.10 0.15 0.22 0.30 0.20 0.12 0.17 0.22 0.15 0° 8° 6.20 6.40 6.60 0.65 0.13 0.10 0.65 0.40 0.50 0.60 1.0 Sales Strategic Planning Div. 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Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. 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Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145 Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510 © 2007. Renesas Technology Corp., All rights reserved. Printed in Japan. Colophon .7.0