Si9102 Vishay Siliconix 3-W High-Voltage Switchmode Regulator DESCRIPTION FEATURES The Si9102 high-voltage switchmode regulator is a monolithic BiC/DMOS integrated circuit which contains most of the components necessary to implement a high-efficiency dc-todc converter up to 3 watts. It can either be operated from a low-voltage dc supply, or directly from a 10 to 120 V unregulated dc power source. • • • • • • • This device may be used with an appropriate transformer to implement most single-ended isolated power converter topologies (i.e., flyback and forward). 10 to 120 V Input Range Current-Mode Control On-chip 200 V, 7 Ω MOSFET Switch SHUTDOWN and RESET High Efficiency Operation (> 80 %) Internal Start-Up Circuit Internal Oscillator (1 MHz) The Si9102 is available in both standard and lead (Pb)-free 14-pin plastic DIP and 20-pin PLCC packages which are specified to operate over the industrial temperature range of - 40 °C to 85 °C. FUNCTIONAL BLOCK DIAGRAM FB COMP 14 (20) OSC IN DISCHARGE 13 (18) 9 (12) 8 (11) Error Amplifier VREF OSC OUT 7 (10) OSC - 10 (14) + Clock (1/2 fOSC) 2V - 4 V (1 %) Current-Mode Comparator R + Ref Gen Q S 3 (5) + - C/L Comparator 5 (8) 1.2 V 1 (2) BIAS VCC +VIN Current Sources To Internal Circuits 4 (7) VCC 6 (9) 2 (3) 8.8 V + Undervoltage Comparator S Q R 11 (16) 12 (17) DRAIN - VIN (BODY) SOURCE SHUTDOWN RESET + 9.4 V Note: Figures in parenthesis represent pin numbers for 20-pin package. Document Number: 70001 S-70497-Rev. H, 19-Mar-07 www.vishay.com 1 Si9102 Vishay Siliconix ABSOLUTE MAXIMUM RATINGS Parameter Voltages Referenced to - VIN (VCC < + VIN + 0.3 V) VCC +VIN VDS ID (Peak) (Note: 300 µs pulse, 2 % duty cycle) ID (rms) Logic Inputs (RESET, SHUTDOWN, OSC IN) Linear Inputs (FEEDBACK, SOURCE) HV Pre-Regulator Input Current (continuous) Storage Temperature Operating Temperature Junction Temperature (TJ) Limit 14-Pin Plastic DIP (J Suffix)b 20-Pin PLCC (N Suffix)c 14-Pin Plastic DIP 20-Pin PLCC Power Dissipation (Package)a Thermal Impedance (ΘJA) Unit 15 120 200 2 250 - 0.3 V to VCC + 0.3 V - 0.3 to 7 3 - 65 to 125 - 40 to 85 150 750 1400 167 90 V A mA V mA °C mW °C/W Notes: a. Device Mounted with all leads soldered or welded to PC board. b. Derate 6 mW/°C above 25 °C. c. Derate 11.2 mW/°C above 25 °C. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING RANGE Parameter Voltages Referenced to - VIN VCC ROSC Linear Inputs + VIN fOSC Digital Inputs Limit Unit 9.5 to 13.5 25 kΩ to 1 MΩ 0 to 7 10 to 120 40 kHz to 1 MHz 0 to VCC V V V SPECIFICATIONSa Limits D Suffix - 40 to 85 °C Test Conditions Unless Otherwise Specified DISCHARGE = - VIN = 0 V VCC = 10 V, + VIN = 48 V RBIAS = 390 kΩ, ROSC = 330 kΩ Tempb Mind Typc Maxd Unit VR OSC IN = - VIN (OSC Disabled) RL = 10 MΩ Room Full 3.92 3.86 4.0 4.08 4.14 V Short Circuit Current Temperature Stabilitye ZOUT ISREF TREF VREF = - VIN Room Room Full 15 70 30 100 0.5 45 130 1.0 kΩ µA mV/°C Oscillator Maximum Frequencye fMAX Room Room Room Room Full 1 80 160 3 100 200 10 200 120 240 15 500 Parameter Symbol Reference Output Voltage Output Impedancee Initial Accuracy fOSC Voltage Stability Temperature Coefficiente Δf/f TOSC www.vishay.com 2 ROSC = 0 ROSC = 330 kΩg ROSC = 150 kΩg Δf/f = f(13.5 V) - f(9.5 V)/f(9.5 V) MHz kHz % ppm/°C Document Number: 70001 S-70497-Rev. H, 19-Mar-07 Si9102 Vishay Siliconix SPECIFICATIONSa Parameter Symbol Test Conditions Unless Otherwise Specified DISCHARGE = - VIN = 0 V VCC = 10 V, + VIN = 48 V RBIAS = 390 kΩ, ROSC = 330 kΩ VFB FB Tied to COMP OSC IN = - VIN (OSC Disabled) Limits D Suffix - 40 to 85 °C Tempb Mind Typc Maxd Unit Room 3.96 4.00 4.04 V 25 500 nA Room 60 80 Room 0.7 Error Amplifier Feedback Input Voltage Input BIAS Current IFB Open Loop Voltage Gaine Unity Gain Bandwidth e AVOL BW Room OSC IN = - VIN, VFB = 4 V, OSC IN = - VIN (OSC Disabled) dB 1 MHz Room 1000 2000 Ω Room - 2.0 - 1.4 mA ± 15 ± 40 mV Dynamic Output Impedancee ZOUT Output Current IOUT Source (VFB = 3.4 V) Input OFFSET Voltage VOS OSC IN = - VIN (OSC Disabled) Room Output Current IOUT Sink (VFB = 4.5 V) Room 0.12 0.15 mA PSRR 9.5 V ≤ VCC ≤ 13.5 V Room 50 70 dB VSOURCE RL = 100 Ω from DRAIN to VCC VFB = 0 V Room 1.0 1.2 1.4 V td RL = 100 Ω from DRAIN to VCC VSOURCE = 1.5 V, See Figure 1 Room 100 200 ns Power Supply Rejection Current Limit Threshold Voltage Delay to Outpute Pre-Regulator/Start-Up Input Voltage + VIN IIN = 10 µA Room 120 V Input Leakage Current + IIN VCC ≥ 10 V Room 10 µA Pre-Regulator Start-Up Current ISTART Pulse Width ≤ 300 µs, VCC = 7 V Room 8 15 VCC Pre-Regulator Turn-Off Threshold Voltage VREG IPRE-REGULATOR = 10 µA Room 7.8 9.4 9.7 Undervoltage Lockout VUVLO RL = 100 Ω from DRAIN to VCC See Detailed Description Room 7.0 8.8 9.2 V VREG, - VUVLO VDELTA Room 0.3 0.6 ICC Room 0.45 0.6 1.0 mA IBIAS Room 10 15 20 µA 50 100 Supply Supply Current Bias Current Logic SHUTDOWN Delaye tSD SHUTDOWN Pulse Widthe tSW RESET Pulse Widthe tRW Latching Pulse Widthe SHUTDOWN and RESET Low Input Low Voltage VSOURCE = - VIN, See Figure 2 Room Room 50 Room 50 tLW Room 25 See Figure 3 ns VIL Room Input High Voltage VIH Room Input Current Input Voltage High IIH VIN = 10 V Room Input Current Input Voltage Low IIL VIN = 0 V Room - 35 - 25 200 220 MOSFET Switch Breakdown Voltage Drain-Source On Resistancef Drain Off Leakage Current VBR(DSS) IDRAIN = 100 µA Full rDS(on) IDRAIN = 100 mA Room IDSS VDRAIN = 100 V Room mA 2.0 8.0 1 5 5 V µA V 7 Ω 10 µA Room 35 pF Drain Capacitance CDS Notes: a. Refer to PROCESS OPTION FLOWCHART for additional information. b. Room = 25 °C, Full = as determined by the operating temperature suffix. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. e. Guaranteed by design, not subject to production test. f. Temperature coefficient of rDS(on) is 0.75 % per °C, typical. g. CSTRAY Pin 8 = ≤ 5 pF. Document Number: 70001 S-70497-Rev. H, 19-Mar-07 www.vishay.com 3 Si9102 Vishay Siliconix TIMING WAVEFORMS 1.5 V SOURCE 0 VCC - VCC SHUTDOWN 0 - tr ≤ 10 ns 50 % td DRAIN 0 tf ≤ 10 ns 50 % tSD VCC DRAIN 0 10 % 10 % Figure 2. Figure 1. tSW VCC SHUTDOWN 0 - 50 % 50 % tr, tf ≤ 10 ns tLW VCC RESET 0 - 50 % 50 % 50 % tRW Figure 3. TYPICAL CHARACTERISTICS 1M 140 VCC = - VIN 120 f OUT (Hz) +V IN (V) 100 80 60 100 k 40 20 0 10 k 10 15 +IIN (mA) Figure 4. + VIN vs. + IIN at Start-Up www.vishay.com 4 20 10 k 100 k 1M rOSC - Oscillator Resistance (Ω) Figure 5. Output Switching Frequency vs. Oscillator Resistance Document Number: 70001 S-70497-Rev. H, 19-Mar-07 Si9102 Vishay Siliconix PIN CONFIGURATIONS PIN DESCRIPTION PDIP-14 1 Function 14 Pin 14-Pin DIP 20-Pin PLCC* 13 BIAS 1 2 3 12 + VIN 2 3 4 11 5 2 5 10 6 9 7 8 Top View PLCC-20 3 2 1 20 19 DRAIN 3 SOURCE 4 7 - VIN 5 8 VCC 6 9 OSC OUT 7 10 OSC IN 8 11 DISCHARGE 9 12 VREF 10 14 SHUTDOWN 11 16 RESET 12 17 COMP 13 18 FB 14 20 *Pins 1, 4, 6, 13, 15, and 19 = N/C 4 18 5 17 6 16 7 15 ORDERING INFORMATION 8 14 Standard Part Number 9 10 11 12 13 Top View Lead (Pb)-free Part Number Si9102DJ02 Si9102DJ02-E3 Si9102DN02 Si9102DN02-E3 Si9102DN02-T1 Si9102DN02-T1-E3 (With Tape (With Tape and Reel) and Reel) Temperature Range Package PDIP-14 - 40 to 85 °C PLCC-20 DETAIL DESCRIPTION Pre-Regulator/Start-Up Section Due to the low quiescent current requirement of the Si9102 control circuitry, bias power can be supplied from the unregulated input power source, from an external regulated lowvoltage supply, or from an auxiliary "bootstrap" winding on the output inductor or transformer. When power is first applied during start-up, + VIN will draw a constant current. The magnitude of this current is determined by a high-voltage depletion MOSFET device which is connected between + VIN and VCC. This start-up circuitry provides initial power to the IC by charging an external bypass capacitance connected to the VCC pin. The constant current is disabled when VCC exceeds 9.4 V. If VCC is not forced to exceed the 9.4 V threshold, then VCC will be regulated to a nominal value of 9.4 V by the pre-regulator circuit. Document Number: 70001 S-70497-Rev. H, 19-Mar-07 As the supply voltage rises toward the normal operating conditions, an internal undervoltage (UV) lockout circuit keeps the output MOSFET disabled until VCC exceeds the undervoltage lockout threshold (typically 8.8 V). This guarantees that the control logic will be functioning properly and that sufficient gate drive voltage is available before the MOSFET turns on. The design of the IC is such that the undervoltage lockout threshold will not exceed the pre-regulator turn-off voltage. Power dissipation can be minimized by providing an external power source to VCC such that the constant current source is always disabled. Note: During start-up or when VCC drops below 9.4 V the start-up circuit is capable of sourcing up to 20 mA. This may lead to a high level of power dissipation in the IC (for a 48 V input, approximately 1 W). Excessive start-up time caused by external loading of the VCC supply can result in device damage. Figure 4 gives the typical pre-regulator current at start-up as a function of input voltage. www.vishay.com 5 Si9102 Vishay Siliconix DETAIL DESCRIPTION BIAS SHUTDOWN and RESET To properly set the bias for the Si9102, a 390 kΩ resistor should be tied from BIAS to - VIN. This determines the magnitude of bias current in all of the analog sections and the pull-up current for the SHUTDOWN and RESET pins. The current flowing in the bias resistor is nominally 15 µA. SHUTDOWN and RESET are intended for overriding the output MOSFET switch via external control logic. The two inputs are fed through a latch preceding the output switch. Depending on the logic state of RESET, SHUTDOWN can be either a latched or unlatched input. The output is off whenever SHUTDOWN is low. By simultaneously having SHUTDOWN and RESET low, the latch is set and SHUTDOWN has no effect until RESET goes high. The truth table for these inputs is given in Table 1. Reference Section The reference section of the Si9102 consists of a temperature compensated buried zener and trimmable divider network. The output of the reference section is connected internally to the non-inverting input of the error amplifier. Nominal reference output voltage is 4 V. The trimming procedure that is used on the Si9102 brings the output of the error amplifier (which is configured for unity gain during trimming) to within ± 1 % of 4 V. This automatically compensates for the input offset voltage in the error amplifier. The output impedance of the reference section has been purposely made high so that a low impedance external voltage source can be used to override the internal voltage source, if desired, without otherwise altering the performance of the device. Both pins have internal current source pull-ups and should be left disconnected when not in use. An added feature of the current sources is the ability to connect a capacitor and an open-collector driver to the SHUTDOWN or RESET pins to provide variable shutdown time. Table 1. Truth Table for the SHUTDOWN and RESET Pins SHUTDOWN RESET Output H H Normal Operation H Normal Operation (No Change) L H L L Off (Not Latched) Off (Latched) L Off (Latched, No Change) Error Amplifier Closed-loop regulation is provided by the error amplifier, which is intended for use with "around-the-amplifier" compensation. A MOS differential input stage provides for low input current. The noninverting input to the error amplifier (VREF) is internally connected to the output of the reference supply and should be bypassed with a small capacitor to ground. Output Switch The output switch is a 7 Ω , 200 V lateral DMOS device. Like discrete MOSFETs, the switch contains an intrinsic bodydrain diode. However, the body contact in the Si9102 is connected internally to - VIN and is independent of the SOURCE. Oscillator Section The oscillator consists of a ring of CMOS inverters, capacitors, and a capacitor discharge switch. Frequency is set by an external resistor between the OSC in and OSC out pins. (See Figure 5 for details of resistor value vs. frequency.) The DISCHARGE pin should be tied to - VIN for normal internal oscillator operation. A frequency divider in the logic section limits switch duty cycle to ≤ 50 % by locking the switching frequency to one half of the oscillator frequency. Remote synchronization can be accomplished by capacitive coupling of a synchronization pulse into the OSC IN terminal. For a 5 V pulse amplitude and 0.5 µs pulse width, typical values would be 100 pF in series with 3 kΩ to OSC IN. www.vishay.com 6 Document Number: 70001 S-70497-Rev. H, 19-Mar-07 Si9102 Vishay Siliconix APPLICATIONS +VIN 1N5819 100 µH GND 2 300 µH 20 µF 1 +5V 3 0.1 µF 220 µF GND 4 5 7 0.1 µF 18 kΩ 390 kΩ 1 14 2 13 3 12 4 Si9102DJ 0.022 µF 10 6 9 7 8 6 -5V 0.1 µF 0.1 µF 1/ 2 8 11 5 2Ω W 1N5819 240 kΩ 47 µF 12 kΩ 1N4148 150 kΩ - VIN (- 96 VDC) Figure 6. Flyback Converter for Double Battery Telecommunications Power Supplies Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?70001. Document Number: 70001 S-70497-Rev. H, 19-Mar-07 www.vishay.com 7 Package Information Vishay Siliconix PLCC: 2O-LEAD (POWER IC ONLY) D−SQUARE A2 MILLIMETERS D1−SQUARE B1 B e1 D2 Document Number: 72812 28-Jan-04 INCHES Min Max Min Max 4.20 4.57 0.165 0.180 2.29 3.04 0.090 0.120 0.51 − 0.020 − 0.331 0.553 0.013 0.021 0.661 0.812 0.026 0.032 9.78 10.03 0.385 0.395 8.890 9.042 0.350 0.356 7.37 8.38 0.290 0.330 1.27 BSC 0.050 BSC ECN: S-40081—Rev. A, 02-Feb-04 DWG: 5917 A1 A Dim A A1 A2 B B1 D D1 D2 e1 0.101 mm 0.004″ www.vishay.com 1 Package Information Vishay Siliconix PDIP: 14-LEAD (POWER IC ONLY) 14 13 12 11 10 9 8 E E1 1 2 3 4 5 6 7 D S Q1 A A1 B1 e1 L B Dim A A1 B B1 C D E E1 e1 eA L Q1 S 15° MAX C eA MILLIMETERS Min Max INCHES Min Max 3.81 5.08 0.150 0.200 0.38 1.27 0.015 0.050 0.38 0.51 0.015 0.020 0.89 1.65 0.035 0.065 0.20 0.30 0.008 0.012 17.27 19.30 0.680 0.760 7.62 8.26 0.300 0.325 5.59 7.11 0.220 0.280 2.29 2.79 0.090 0.110 7.37 7.87 0.290 0.310 2.79 3.81 0.110 0.150 1.27 2.03 0.050 0.080 1.02 2.03 0.040 0.080 ECN: S-40081—Rev. A, 02-Feb-04 DWG: 5919 Document Number: 72814 28-Jan-04 www.vishay.com 1 Legal Disclaimer Notice Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners. Document Number: 91000 Revision: 11-Mar-11 www.vishay.com 1