SiP11206 Vishay Siliconix Half-Bridge Controller with Primary MOSFET Drivers for Intermediate Bus Converters DESCRIPTION FEATURES SiP11206 is a controller for the primary side of a half-bridge intermediate bus converter (IBC). It is ideally suited for isolated applications such as telecom, data communications and other products requiring an IBC architecture and conversion of standard bus voltages such as 48 V to a lower intermediate voltage, where high efficiency is required at low output voltages (24 V, 12 V, 9 V or 5 V). • 36 V to 75 V input voltage range • Withstand 100 V, 100 ms transient capability • Integrated ± 1.6 A typical high- and low-side MOSFET drivers • Oscillator frequency is programmable from 200 kHz to 1 MHz and can be externally synchronized • High voltage pre-regulator operates during start-up • Current sensing on primary low-side switch • Hiccup mode • System low input voltage detection • Chip UVLO function • Programmable soft-start function • Over temperature protection (160 °C) • Greater than 95 % efficiency Designed to operate within the telecom voltage range of 36 V to 75 V and withstand 100 V transients for a period of 100 ms, the IC is designed for controlling and driving both the low- and high-side switching devices of a half-bridge converter. The SiP11206 operates with a fixed duty cycle to provide the highest efficiency over a wide input voltage range. SiP11206 has advanced current monitoring and control circuitry, which allows the user to set the maximum current in the primary circuit. This feature acts as protection against overcurrent, output short circuit. Current sensing is by means of a sense resistor connected in series with the primary low-side MOSFET. APPLICATIONS • • • • • Intermediate bus architectures Telecom and Datacom Routers and servers Storage area network Base station • 1/8 and 1/4 bricks TYPICAL APPLICATION CIRCUIT Vin+ Si2303BDS 36 V to 75 V 100 V/100 ms Vin- 4 5 6 7 8 BST VIN DH VCC LX COMP CS DL PGND AGND SS VREF RDB ROSC COSC 16 15 14 13 12 Si7848DP 3 VINDET Si7848DP 2 Si7456DP 1 11 10 Vo+ Vo- 9 Si2303BDS Si7456DP SiP11206 RDB Document Number: 69232 S-81795-Rev. C, 04-Aug-08 www.vishay.com 1 SiP11206 Vishay Siliconix TECHNICAL DESCRIPTION SiP11206 is a switching controller on the primary side of a half-bridge intermediate bus converter. With 100 V depletion mode MOSFET in the chip, the SiP11206 is capable of being powered directly from the high voltage bus to VCC through an external PNP pass transistor, or may be powered by an external supply directly to the VCC pin. result in over temperature protection activating hiccup operation whenever the pre-regulator power dissipation becomes excessive. The external high- and low-side N-Channel power MOSFETs are driven by a built in driver with ± 1.6 A peak current capability. SiP11206 is available in the MLP44-16 PowerPAK® package and TSSOP-16 PowerPAK® package and is specified over the ambient temperature range of - 40 °C to + 85 °C Without the use of an external pass transistor, failure of the converter output to power VCC above the VREG level will SIP11206 BLOCK DIAGRAM VIN VCC VREG COMP Pre Reg BST UVLO + VSD Level Shift + VINDET VREF VUV + - VCC BG VUV - ISS Driver + 250 mV SS IDSS EN Control DL Le SS Comp + 4.8 V LX Hi-side driver 0.85 VSS AGND CS DH Low-side driver EN D MAX OTP Over Current protection PGND PWM Comp Ramp EN 0.13 V VREF OSC EN Le EN VREF EN IDSS IBIAS ISS IBIAS 0.200 V R OSC R DB C OSC www.vishay.com 2 Document Number: 69232 S-81795-Rev. C, 04-Aug-08 SiP11206 Vishay Siliconix ABSOLUTE MAXIMUM RATINGS all voltages referenced to GND = 0 V Parameter VIN, VLX Limit Continuous 80 100 ms 100 VCC VBST 14.5 Continuous 95 100 ms 112 VBST - VLX Logic Inputs - 0.3 to VCC + 0.3 - 0.3 to VCC + 0.3 HV Pre-Regulator Input Current (continuous) 10 Storage Temperature - 65 to 150 Maximum Junction Temperature 150 PowerPAK MLP44-16a ,b 2564 a, c 2630 PowerPAK TSSOP-16 Thermal Impedance (ΘJA) V 15 Linear Inputs Power Dissipation Unit PowerPAK MLP44-16a ,b 39 PowerPAK TSSOP-16a, c 38 mA °C mW °C/W Notes: a. Device mounted with all leads soldered or welded to PC board. b. Derate 25.6 mW/°C above 25 °C. c. Derate 26.3 mW/°C above 25 °C. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING RANGE all voltages referenced to GND = 0 V Parameter VIN VBST Limit Continuous 100 ms Unit 36 to 75 100 VIN + 10.5 to VIN + 13.2 VBST - VLX 10.5 to 13.2 VCC 10.5 to 13.2 Logic Inputs - 0.3 to VCC + 0.3 Linear Inputs - 0.3 to VCC + 0.3 V FOSC 200 to 1000 kHz ROSC 40 to 200 kΩ COSC 100 to 220 pF CSS 10 to 100 CCOMP VREF Capacitor to GND 2.2 1 CBOOST 0.1 VCC Capacitor to GND 4.7 Document Number: 69232 S-81795-Rev. C, 04-Aug-08 nF µF www.vishay.com 3 SiP11206 Vishay Siliconix SPECIFICATIONS Parameter Symbol Test Conditions Unless Otherwise Specified TA = - 40 °C to + 85 °C, FOSC = 800 kHz, 10.5 V ≤ VCC ≤ 13.2 V, VINDET = 4.8 V, VIN = 48 V, RDB = 47.5 kΩ, ROSC = 47.5 kΩ, COSC = 100 pF Limits Min. Typ. Max. Unit 36 48 75 V Pre-Regulator VIN Range VIN Pre-Reg Current (cut-off) IVINLKG VIN = 75 V, VCC > 10.5 V Pre-Reg Current (standby) IVINSD VIN = 75 V, VINDET = 0 V Pre-Reg Current (switching) IVINSW VIN = 75 V, VINDET = 7.5 V 3.3 6.0 8.7 mA Pre-Reg Output Voltage VREG VCC Voltage with VIN = 48 V 7.8 9.3 10.4 V Pre-Reg Drive Current 20 ISTART VCC < VREG Pre-Reg Load Regulation LDR ILOAD: 0 to 20 mA Pre-Reg Line Regulation LNR ISRC Regulator Compensation ISNK VCC = 12 V 10 90 200 µA mA 100 mV 0.05 %/V - 35 - 20 - 10 40 87 130 µA VCC Supply Voltage VCC Range VCC 10.5 12 13.2 V Shut Down Current ISD VINDET = 0 V 50 150 350 µA Quiescent Current IQ VINDET < VREF 4.0 5.0 6.2 Supply Current ICC VINDET > VREF 5.5 7.2 9.5 UVLO Off-Threshold UVLOH VCC rising 7.6 9.0 10 Hysteresis HUVLO VCC Clamp Voltage VCLAMP Force 20 mA into VCC 14 15.3 16.2 Current Limit Threshold 1 (MOC)a VMOC ISS = 20 µA, CSS= 1 nF 105 130 160 b VSOC ISS = 400 nA, CSS= 1 nF 165 200 235 mA V 1.2 Current Sense Current Limit Threshold 2 (SOC) CS to DL Delay TD Leading Edge Blanking Period TBL 150 DL(ON) blanking time mV ns 20 Pulse Width Modulator Maximum Duty Cyclec DMAX 47 Maximum Duty Cycle Asymmetry RDB Voltage 50 1 VRDB 3.18 % V Oscillator Oscillator Frequencyd FOSC Oscillator Bias Voltage VROSC ROSC = 47 kΩ, COSC = 100 pF 680 800 920 3.24 kHz V Soft Start Soft Start Charging Current ISS SS Ramp Completion Voltage VSS VSS = 0 V - 26 - 20 - 14 5.4 µA V MOC Discharge Current IDSS1 CS = VMOC SOC Discharge Current IDSS2 CS = VSOC 400 nA Reset Voltage VSSL CS < VMOC 0.25 V 14 20 26 µA Reference VREF VCC = 12 V 3.2 3.3 Short Circuit Current IREFSC VREF = 0 V - 50 - 42 mA Load Regulation ΔVR/ΔIR (0 mA ≤ ILOAD ≤ 2.5 mA) - 33 - 16 mV Output Voltage www.vishay.com 4 3.4 V Document Number: 69232 S-81795-Rev. C, 04-Aug-08 SiP11206 Vishay Siliconix SPECIFICATIONS Parameter Symbol Test Conditions Unless Otherwise Specified TA = - 40 °C to 85 °C, FOSC = 800 kHz, 10.5 V ≤ VCC ≤ 13.2 V, VINDET = 4.8 V, VIN = 48 V, RDB = 47.5 kΩ, ROSC = 47.5 kΩ, COSC = 100 pF Min. 30 VINDET rising 0.33 VINDET rising at ICC 3.14 Limits Typ. Max. Unit 46 70 kΩ 0.58 0.76 VINDET Function VIndet Pin Input Impedance RINDET VSDH Shutdown Threshold High Voltage Shutdown Hysteresis Voltage HSD Under Voltage OFF Voltage VUVH Under Voltage Hysteresis Voltage HUV 0.15 3.30 3.46 V 0.26 Over Temperature Protection (OTP) Activating Temperature OTPON TJ rising 160 De-activating Temperature OTPOFF TJ falling 145 °C High-Side MOSFET Driver (DH Output) Output High Voltage (differential) VDHH Sourcing 10 mA, VDH - VBST Output Low Voltage (differential) VDHL Sinking 10 mA, VDH -VLX Peak Output Sourcing Current IDHH Peak Output Sinking Current IDHL Driver Frequency FDH Rise Time tHR CLOAD = 3 nF 20 Fall Time tHF CLOAD = 3 nF 20 Boost Pin Current (switching) IBST LX Pin Current (switching) ILX LX Pin Leakage Current ILX-LKG - 0.3 0.3 - 2.2 VCC = 10.5 V, CLOAD = 3 nF VLX = 75 V, VBST = VLX + VCC A 1.6 340 400 460 kHz ns 1.3 2.6 3.9 - 2.1 - 1.4 - 0.7 VINDET = 0 V, VLX = 40 V V 10 mA µA Low-Side MOSFET Driver (DL Output) Output High Voltage (differential) VDLH Sourcing 10 mA, VDL - VCC Output Low Voltage (differential) VDLL Sinking 10 mA, VDL - VAGND Peak Output Sourcing Current IDLH Peak Output Sinking Current IDLL Driver Frequency FDL Rise Time tLR CLOAD = 3 nF 20 Fall Time tLF CLOAD = 3 nF 20 - 0.3 0.3 - 1.6 VCC = 10.5 V, CLOAD = 3 nF A 1.6 340 400 V 460 kHz ns Notes: a. MOC stands for moderate overcurrent voltage at CS pin. b. SOC stands for severe overcurrent voltage at CS pin. c. RDB should be chosen for each application to provide adequate dead time. For production testing RDB is chosen to test at 47 % target duty. d. Not tested. Guaranteed by driver frequency test. The driver frequency is half of the oscillator frequency. Document Number: 69232 S-81795-Rev. C, 04-Aug-08 www.vishay.com 5 SiP11206 Vishay Siliconix PACKAGE AND PIN CONFIGURATION VCC TSSOP-16 PowerPAK Package DH BST VIN VINDET MLP44-16 PowerPAK Package 1 2 3 4 5 6 7 8 LX 1 COMP DL TOP VIEW CS PGND AGND R DB C OSC R OSC VREF SS Top View 16 15 14 13 12 11 10 9 Notes: For MLP44-16 package the bottom pin 1 indicator is connected to EPAD or AGND. TSSOP-16 MLP44-16 Symbol 3 1 VCC Description 4 2 COMP 5 3 CS 6 4 AGND 7 5 VREF 3.3 V reference output and bypass capacitor connection pin 8 6 ROSC Oscillator resistor connection 9 7 COSC Oscillator capacitor connection and external frequency sync. connection 10 8 RDB Pre-regulator output and supply voltage for internal circuitry Pre-regulator compensation pin Current sense comparator input Analog ground (connected to package’s exposed pad) Dead time setting resistor connection 11 9 SS 12 10 PGND Soft start capacitor connection 13 11 DL Primary low-side MOSFET drive signal 14 12 LX High-side MOSFET source and transformer connection node 15 13 DH Primary high-side MOSFET drive signal 16 14 BST Bootstrap voltage pin for the high-side driver 1 15 VINDET Shut down/under voltage/enable control pin 2 16 VIN Power ground High voltage pre-regulator input ORDERING INFORMATION Part Number Package SiP11206DQP-T1-E3 TSSOP-16 SiP11206DLP-T1-E3 MLP44-16 www.vishay.com 6 Marking Temperature 11206 - 40 °C to + 85 °C Document Number: 69232 S-81795-Rev. C, 04-Aug-08 SiP11206 Vishay Siliconix TIMING DIAGRAM AND SOFT START DUTY CYCLE CONTROL RDB COSC SS DL DH DMAX. Time HICCUP RESPONSE TO MODERATE OVERCURRENT FAULTS SS Clamp Level DMAX. Clamp Level Hiccup Trigger Level SS DL DH Hiccup Triggered CS IN OC_DET CLK Over current protection operation showing reduction in duty cycle down to the hiccup trigger point. SS continues to discharge down to 250 mV (400 nA IDISCHARGE), and then will recharge at 20 µA. Document Number: 69232 S-81795-Rev. C, 04-Aug-08 www.vishay.com 7 SiP11206 Vishay Siliconix CIRCUIT FOR FREQUENCY SYNCHRONIZATION 220 pF 100 2N3904 SYNC IN Cosc SiP11206 1k DETAILED OPERATIONAL DESCRIPTION Start Up The controller supply (VCC) is linearly regulated up to its target voltage VREG by the on chip pre-regulator circuit. During power up with VINDET ramping up from 0, the VCC capacitor minimum charge current is 20 mA and the pre-regulator voltage is typically 9.3 V. As VINDET exceeds VREF, the DL/DH outputs are capable of driving 3 nF MOSFET gate capacitances and hence the pre-regulator load regulation can easily handle 120 µA to 20 mA load step with a typical load regulation of 1 %. Current into the external VCC capacitor is limited to typically 20 mA by the internal pre-regulator unless an external power source is connected to VCC pin. This source may be a DC supply or from VIN by connecting a PNP pass transistor between VIN and VCC. The VCC pin is protected by a 20 mA clamp when this pin exceeds 14.5 V. The clamp turns on when VCC is between 14.5 V and 16 V. When VCC exceeds the UVLO voltage (UVLOH) a soft start cycle of the switch mode supply is initiated. The VCC supply continues to be charged by the pre-regulator until VCC equals VREG. During this period, between UVLOH and VREG, excessive load may result in VCC falling below UVLOH and stopping switch mode operation. This situation is avoided by the hysteresis between VREG and UVLO Off-Threshold level UVLOL. PWM Operation During startup, DL always turns on before DH and both switch on and off at half the oscillator frequency. The driver duty cycle increases as SS voltage increases, since the SS comparator sets the ON pulse width by comparing the SS ramp voltage with the oscillator ramp voltage. When SS ramp reaches a voltage that equals to RDB voltage, the PWM comparator, which compares RDB voltage to the oscillator ramp, takes over and the maximum duty cycle is now set by the oscillator ramp and RDB voltage. Mathematically, the total duty cycle is determined by the following formula: formula may be slightly different. The PWM operation during start up can be better understood by referring to "Timing diagram and soft start duty cycle control" graph. The soft start completion voltage at SS pin is clamped above the internal ramp waveform's upper turning point. Soft Start The soft start circuit plays an important role in protecting the controller. At startup it prevents high in-rush current. During a normal start-up sequence (VCS < VMOC. VCS is the voltage at CS pin), or following any event that would cause a hiccupand-soft-start sequence, CSS will be charged from about 0 V to a final voltage of 4.8 V at a 20 µA rate. As the voltage on the CSS rises towards the final voltage, the maximum permitted DL and DH duty cycles will increase from 0 % to a maximum defined by the RDB resistor. When a mild fault condition is detected (VCS = VMOC), CSS goes into a hiccup mode until fault condition is removed. The hiccup is activated when CSS discharges to 0.85 VSS at 20 µA and subsequently at 0.4 µA until the fault condition is removed. Refer to "Fault Conditions and Responses" for details. Fault Conditions and Responses The faults that can cause a hiccup-and-retry cycle are moderate over-current (MOC), severe over-current (SOC), chip level UVLO, system level UVLO, and over temperature protection (OTP). Prior to detailing the various fault conditions and responses, some definitions are given: 1. A complete switching period, T, consists of two oscillator cycles, TDL and TDH. 2. TDL (TDH) is the oscillator cycle during which the DL (DH) output is in the high state. 3. T is defined as starting at the beginning of TDL, and terminating at the end of TDH. DTOTAL = RDB/ROSC And the duty cycle on DL or DH will be approximately half of DTOTAL. Please note that due to oscillator comparator overshoot the exact duty cycle calculated using above www.vishay.com 8 Response to MOC Faults (VMOC < VCS < VSOC): Once SiP11206 has completed a normal soft-start cycle, VSS will be clamped at 4.5 V, allowing the maximum possible duty cycle on DL and DH. Document Number: 69232 S-81795-Rev. C, 04-Aug-08 SiP11206 Vishay Siliconix If an MOC fault occurs following the start-up (due to a condition such as an excessive load on the converter’s output), SiP11206 will respond by gradually reducing the available maximum duty cycle of its DL and DH outputs each to be equal to approximately 42 % of their possible 47 % maximum values. This is before any effects of deadtime introduced by RDB are added in. This reduction in available maximum duty cycle is achieved by reducing the voltage on the SS pin to 4 V, as follows: 1. If VMOC < VCS < VSOC at any time during TDL, a current of 20 µA will be drawn out of the SS pin until the beginning of the next TDL. 2. If the voltage on the SS pin remains above the value that would allow an available maximum DL and DH duty cycle of 42 %, SiP11206 will continue operating. 3. If the voltage on the SS pin goes below the value that would allow an available maximum DL and DH duty cycle of 42 %, a hiccup interval is started, during which both DL and DH are held in their low states. 4. The SS pin is discharged towards 0 V by a 400 nA sink current. 5. The hiccup interval is terminated when the SS pin is discharged to 0.25 V. After the above actions have been taken switching on the DL and DH outputs will then resume with a normal soft-start cycle. Response to MOC faults is enabled after the successful completion of any normal soft-start cycle. Response to SOC Faults (VCS > VSOC): This is an immediate, single-cycle response over current shutdown, followed by a hiccup delay and a normal soft-start cycle. Since this is a gross fault protection mechanism, its triggering mechanism is asynchronous to the timing of TDL and TDH. 1. If VCS > VSOC, a hiccup interval is started, during which both DL and DH are held in their low states. 2. The SS pin is discharged towards 0 V by a 400 nA sink current. 3. The hiccup interval is terminated when the SS pin is discharged to 0.25 V. 4. Switching on the DL and DH outputs will then resume with a normal soft-start cycle. Severe over current response is enabled at all times, including the initial ramp-up period of the soft-start pin. This allows SiP11206 to provide rapid fault protection for the converter’s power train. Immediate Response to UVLO Faults: The under voltage protection conditions at converter-level (VINDET pin UVLO) and chip-level (VCC UVLO) will immediately trigger a shutdown-and-retry SS response, with the restart requirements being that: Document Number: 69232 S-81795-Rev. C, 04-Aug-08 1. The SS pin has been discharged at a 20 µA rate to the 0.25 V level. 2. The affected supply has recovered to its turn-on threshold. Once these conditions are met, switching will resume with a normal soft-start cycle. Response to UVLO faults is enabled at all times, including the initial ramp-up period of the softstart pin. Immediate Response to an OTP Condition: Failure of the application circuit to provide an external voltage to the VCC pin above the VREG level may result in an OTP condition (TJ > OTPON). Other conditions, such as excessive ambient temperature or, where applicable, failure of airflow over the DC-DC converter circuit, can also trigger an OTP condition. An OTP condition will immediately trigger a shutdown-and-retry soft start response, with the restart requirements being that: 1. The SS pin has been discharged at a 20 µA rate to the 0.25 V level. 2. The chip junction temperature has fallen below the lower OTP threshold. Once these conditions are met, switching will resume with a normal soft-start cycle. Response to the OTP condition is enabled at all times, including the initial ramp-up period of the soft-start pin. Reference The reference voltage of SiP11206 is set at 3.3 V at VREF pin. This pin should be decoupled externally with a 0.1 µF to 1 µF capacitor to GND. Up to 5 mA may be drawn internally from this reference to power external circuits. Note that if the VINDET pin is pulled below 0.55 V (typical), the reference will be turned off, and SiP11206 will enter a low-power "standby" mode. During startup or when VREF is accidentally shorted to ground, this pin has internal short circuit protection limiting the source current to 50 mA. VREF load regulation for 5 mA step is typically 0.45 %. Oscillator The oscillator is designed to operate from 200 kHz to 1 MHz with temperature stability within 15 %. This operating frequency range allows the converter to minimize the inductor and capacitor size, improving the power density of the converter. The oscillator frequency, and therefore the switching frequency, is programmable by the value of resistor and capacitor connected to the ROSC and COSC pins respectively. Note that the switching frequency at pins DL and DH is half of the oscillator frequency, i.e., the DL output will be active during one oscillator cycle, and the DH during the next oscillator cycle. VINDET The VINDET pin controls several modes of operation and the modes of operation are controlled by shutdown (VSD) and under voltage (VUV) comparators (see block diagram). When the IC is powered solely by VIN and VINDET is less than VSDH www.vishay.com 9 SiP11206 Vishay Siliconix due to some external reset condition the pre-regulator is in low power standby mode and the internal bias network is powered down. When VINDET is greater than VSDH but less than VREF and VCC is forced to 12 V the pre-regulator shuts off drawing only leakage current from VIN and quiescent current from VCC. In this mode the controller output drivers remains static (non-switching). When VINDET is above VREF the controller is enabled and both drivers are switching at half the oscillator frequency. If SiP11206 is shut down via this pin, its restart will be by means of a soft-start cycle, as described under "Soft Start" and "Hiccup-Mode Operation" above. The input impedance to ground of this pin is typically 46K ± 30 % and must be taken into account at application design. An external 10:1 resistor divider ratio of supply voltage to VINDET pin is required in a typical application. Primary High and Low Side MOSFET Drivers The low-side MOSFET driver is powered directly from VCC of the chip. The high-side MOSFET however requires the gate voltage to be higher than VIN. This is achieved with a charge pump capacitor CBST between BST and LX, and an external diode to charge and bootstrap the initial charge up voltage across CBST to VCC level. On the alternate oscillator cycle the boost diode isolates BST from VIN and hence BST and LX steps up to VIN + VCC and VIN, respectively. This sequencing insures that DL will always turn on before DH during start-up. The boost capacitor value must be chosen to meet the application droop rate requirement. External Frequency Synchronization The oscillator frequency of this IC can be synchronized to an external source with a simple circuit shown in "Circuit for Frequency Synchronization" diagram. The synchronized frequency should not exceed 1.4 times the set frequency, and the synchronized frequency range should not exceed the IC frequency range. TYPICAL CHARACTERISTICS 10.2 7.5 10.0 7.0 9.8 6.5 9.4 IVIN (mA) VREG (V) 9.6 9.2 9.0 VIN = 75 V 6.0 5.5 8.8 8.6 5.0 8.4 8.2 - 40 - 15 10 35 60 85 110 4.5 - 40 135 60 85 Temperature (°C) IVIN vs. Temperature 110 135 110 135 8.0 7.5 VUVH ICC 7.0 ICC, IQ (mA) 3.25 VUV (V) 35 Temperature (°C) 3.30 3.20 3.15 3.10 6.5 VCC = 12 V 6.0 5.5 IQ 5.0 VUVL 3.05 4.5 - 15 10 35 60 85 Temperature (°C) VUV vs. Temperature www.vishay.com 10 10 VREG vs. Temperature 3.35 3.00 - 40 - 15 110 135 4.0 - 40 - 15 10 35 60 85 Temperature (°C) ICC and IQ vs. Temperature Document Number: 69232 S-81795-Rev. C, 04-Aug-08 SiP11206 Vishay Siliconix 800 200 700 180 600 160 ISD (µA) VSD (mV) TYPICAL CHARACTERISTICS VSDH 500 140 120 400 VSDL 100 300 80 - 40 200 - 40 - 15 10 35 60 85 110 135 - 15 10 Temperature (°C) 35 60 85 110 135 Temperature (°C) ISD vs. Temperature VSD vs. Temperature 5.1 10 5.0 9.5 4.9 9.0 VSS (V) UVLO (V) UVLOH 8.5 4.8 4.7 4.6 8.0 4.5 UVLOL 7.5 - 40 - 15 10 35 60 85 110 4.4 - 40 135 10 35 60 85 Temperature (°C) UVLO vs. Temperature VSS vs. Temperature 23 - 15 22 - 16 21 110 135 110 135 - 17 20 ISS (µA) IDSS1 (µA) - 15 Temperature (°C) 19 - 18 - 19 18 - 20 17 - 21 16 15 - 40 - 15 10 35 60 85 Temperature (°C) IDSS1 vs. Temperature Document Number: 69232 S-81795-Rev. C, 04-Aug-08 110 135 - 22 - 40 - 15 10 35 60 85 Temperature (°C) ISS vs. Temperature www.vishay.com 11 SiP11206 Vishay Siliconix TYPICAL CHARACTERISTICS 140 0.55 120 0.50 IVINSD (µA) IDSS2 (µA) 100 0.45 0.40 80 60 40 0.35 20 0.30 - 40 - 15 10 35 60 85 110 0 - 40 135 - 15 10 35 60 85 Temperature (°C) Temperature (°C) IDSS2 vs. Temperature IVINSD vs. Temperature 430 110 135 47.4 47.2 420 47.0 DL = 44 V 46.8 DMAX (%) FREQ (kHz) 410 FDL 400 FDH 390 46.6 46.4 46.2 DH = 40 V 46.0 380 45.8 370 - 40 - 15 10 35 60 85 110 45.6 - 40 135 - 15 10 35 60 85 Temperature (°C) Temperature (°C) FDL/FDH vs. Temperature DMAX. vs. Temperature 3.304 110 135 3.20 3.302 3.19 3.300 VCC = 12 V VRDB (V) VREF (V) 3.298 3.296 3.294 3.18 3.17 3.292 3.16 3.290 3.288 - 40 - 15 10 35 60 Temperature (°C) VREF vs. Temperature www.vishay.com 12 85 110 3.15 - 40 - 15 10 35 60 85 110 135 Temperature (°C) VRDB vs. Temperature Document Number: 69232 S-81795-Rev. C, 04-Aug-08 SiP11206 Vishay Siliconix TYPICAL CHARACTERISTICS 4.5 3.5 3.3 4.0 3.1 3.5 2.7 RDSP (Ω) RDSN (Ω) 2.9 2.5 2.3 3.0 2.5 2.1 1.9 2.0 1.7 1.5 - 40 1.5 - 15 10 35 60 85 110 - 40 135 35 60 85 Temperature (°C) Temperature (°C) DL RDSP vs. Temperature 2.3 3.1 2.1 2.9 110 135 110 135 110 135 1.9 RDSP (Ω) 2.7 RDSN (Ω) 10 DL RDSN vs. Temperature 3.3 2.5 2.3 1.7 1.5 1.3 2.1 1.1 1.9 0.9 1.7 1.5 - 40 - 15 - 15 10 35 60 85 110 0.7 - 40 135 - 15 10 35 60 85 Temperature (°C) Temperature (°C) DH RDSN vs. Temperature DH RDSP vs. Temperature 65 225 60 200 VSOC RVINDET (kΩ) VCS (mV) 55 175 150 45 VMOC 125 100 - 40 50 40 - 15 10 35 60 85 110 135 35 - 40 - 15 10 35 60 85 Temperature (°C) Temperature (°C) VCS vs. Temperature RVINDET vs. Temperature Document Number: 69232 S-81795-Rev. C, 04-Aug-08 www.vishay.com 13 SiP11206 Vishay Siliconix TYPICAL CHARACTERISTICS 96 14 VIN = 42 V VIN = 55 V VIN = 48 V 13 VIN = 55 V Efficiency (%) Output Voltage (V) 92 12 VIN = 48 V 11 VIN = 42 V 88 10 84 9 8 80 0 3 6 9 12 15 0 3 6 9 Load Current (A) Load Current (A) Line and Load Regulation Efficiency vs. Current 12 15 TYPICAL WAVEFORMS System Startup Primary Driving Signals DL and DH System Shutdown Hiccup Mode when Output Shorted Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?69232. www.vishay.com 14 Document Number: 69232 S-81795-Rev. C, 04-Aug-08 Package Information Vishay Siliconix POWER IC THERMALLY ENHANCED PowerPAKR TSSOP: 14/16-LEAD 3 8 D CL 6 N e −B− 7 R 4 E1 CL 8 GAUGE PLANE −H− 0.25 E SEATING PLANE q1 0.7500 R1 L L1 DETAIL A 1 0.7500 2 3 Ğ 0.07600 0.025−0.075 DP PIN 1 INDICATOR POLISH e TOP VIEW 7 −A− CL CL DETAIL A ccc S A2 aaa C A −C− B SEATING PLANE 9 B A1 b bbb M C B S A S Y c1 CL 5 (b) X c b1 DETAIL B-B BOTTOM VIEW EXPOSED PAD Document Number: 72778 31-Mar-05 www.vishay.com 1 of 2 Package Information Vishay Siliconix POWER IC THERMALLY ENHANCED PowerPAKR TSSOP: 14/16-LEAD MILLIMETERS Dim A A1 A2 b b1 c c1 D e E E1 L L1 R R1 q1 N (14) N (16) X Y (14) Y (16) aaa bbb ccc ddd INCHES* Min Nom Max Min Nom Max − − 1.20 − − 0.0472 0.025 − 0.100 0.001 − 0.0039 0.80 0.90 1.05 0.0315 0.0354 0.0413 0.19 − 0.30 0.0075 − 0.0118 0.19 0.22 0.25 0.0075 0.0087 0.0098 0.09 − 0.20 0.0035 − 0.0079 0.09 − 0.16 0.0035 − 0.0063 4.9 5.0 5.1 0.1929 0.1968 0.2008 0.65 BSC 0.0256 BSC 6.2 6.4 6.6 0.2441 0.2520 0.2598 4.3 4.4 4.5 0.1693 0.1732 0.1772 0.45 0.60 0.75 0.0177 0.0236 0.0295 1.0 REF 0.0394 REF 0.09 − − 0.0035 − − 0.09 − − 0.0035 − − 0 − 0 0 − 0 14 14 16 16 2.95 3.0 3.05 0.116 0.118 0.120 3.15 3.2 3.25 0.124 0.126 0.128 3.0 3.05 0.116 0.118 0.120 2.95 0.10 0.0039 0.10 0.0039 0.05 0.0020 0.20 0.0079 ECN: S-50568—Rev. B, 04-Apr-05 DWG: 5913 *Dimensions are in mm converted to inches. NOTES: 1. All dimensions are in millimeters (angles in degrees). 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. 4. Dimension “E1” does not include internal flash or protrusion. 5. Dimension “b” does not include Dambar protrusion. 6. “N” is the maximum number of lead terminal positions for the specified package length. 7. Datums −A− and −B− to be determined at datum plane −H− . 8. Dimensions “D” and “E1” are to be determined at datum plane −H− . 9. Cross section B-B to be determined at 0.10 to 0.25 mm from the lead tip. 10. Refer to JEDEC MO-153, Issue C., Variation ABT. 11. Exposed pad will depend on the pad size of the L/F. www.vishay.com 2 of 2 Document Number: 72778 31-Mar-05 Package Information Vishay Siliconix PowerPAKr MLP44-16 (POWER IC ONLY) JEDEC Part Number: MO-220 D -B- ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ Index Area (Dń2 Eń2) 4 D/2 AA E/2 BB E -A- aaa C 2 X Detail A Top View // ccc C Nx 9 CC DD aaa C 2 X Seating Plane 0.08 C -C- Side View A A1 A3 D2 N L Detail B D2/2 Datum A or B N r E2/2 6 (NE-1) x e E2 2 Terminal Tip 1 Exposed Pad N b N N-1 Detail A e/2 5 Terminal Tip 5 e Even Terminal/Side 8 e 5 bbb M C A B (ND-1) x e 8 Odd Terminal/Side Detail B Bottom View Document Number: 72802 16-May-05 www.vishay.com 1 Package Information Vishay Siliconix PowerPAKr MLP44-16 (Power IC Only) JEDEC Part Number: MO-220 MILLIMETERS* Dim Min Nom A 0.80 0.90 A1 0 0.02 A3 − 0.20 Ref AA − 0.345 aaa − 0.15 BB − 0.345 b 0.25 0.30 bbb − 0.10 CC − 0.18 ccc − 0.10 D 4.00 BSC D2 2.55 2.7 DD − 0.18 E 4.00 BSC E2 2.55 2.7 e 0.65 BSC L 0.3 0.4 N 16 ND − 4 NE − 4 r b(min)/2 − * Use millimeters as the primary measurement. INCHES Max Min Nom Max 1.00 0.05 − − − − 0.35 − − − 0.0315 0 − − − − 0.0098 − − − 0.0394 0.0020 − − − − 0.138 − − − 2.8 − 0.1004 − 2.8 0.1004 0.5 0.0118 − − − − − b(min)/2 0.0354 0.0008 0.0079 0.0136 0.0059 0.0136 0.0118 0.0039 0.0071 0.0039 0.1575 BSC 0.1063 0.0071 0.1575 BSC 0.1063 0.0256 BSC 0.0157 16 4 4 − Notes 5 0.1102 − 0.1102 0.0197 − − − 3, 7 6 6 ECN: S-50794—Rev. B, 16-May-05 DWG: 5905 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5M-1994. 2. All dimensions are in millimeters. All angels are in degrees. 3. N is the total number of terminals. 4. The terminal #1 identifier and terminal numbering convention shall conform to JESD 95-1 SPP-012. Details of terminal #1 identifier are optional, but must be located within the zone indicated. The terminal #1 identifier may be either a molded or marked feature. The X and Y dimension will vary according to lead counts. 5. Dimension b applies to metallized terminal and is measured between 0.25 mm and 0.30 mm from the terminal tip. 6. ND and NE refer to the number of terminals on the D and E side respectively. 7. Depopulation is possible in a symmetrical fashion. 8. Variation HHD is shown for illustration only. 9. Coplanarity applies to the exposed heat sink slug as well as the terminals. www.vishay.com 2 Document Number: 72802 16-May-05 Legal Disclaimer Notice Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. 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It is the customer’s responsibility to validate that a particular product with the properties described in the product specification is suitable for use in a particular application. Parameters provided in datasheets and/or specifications may vary in different applications and performance may vary over time. All operating parameters, including typical parameters, must be validated for each customer application by the customer’s technical experts. Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein. Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the Vishay product could result in personal injury or death. Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk and agree to fully indemnify and hold Vishay and its distributors harmless from and against any and all claims, liabilities, expenses and damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that Vishay or its distributor was negligent regarding the design or manufacture of the part. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners. Document Number: 91000 Revision: 11-Mar-11 www.vishay.com 1