eZ80F915050MOD eZ80F91 Module Product Specification PS019310-0904 PRELIMINARY ZiLOG Worldwide Headquarters • 532 Race Street • San Jose, CA 95126 Telephone: 408.558.8500 • Fax: 408.558.8300 • www.ZiLOG.com This publication is subject to replacement by a later edition. To determine whether a later edition exists, or to request copies of publications, contact: ZiLOG Worldwide Headquarters 532 Race Street San Jose, CA 95126 Telephone: 408.558.8500 Fax: 408.558.8300 www.ZiLOG.com ZiLOG is a registered trademark of ZiLOG Inc. in the United States and in other countries. All other products and/or service names mentioned herein may be trademarks of the companies with which they are associated. Document Disclaimer © 2004 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Except with the express written approval ZiLOG, use of information, devices, or technology as critical components of life support systems is not authorized. No licenses or other rights are conveyed, implicitly or otherwise, by this document under any intellectual property rights. PS019310-0904 PRELIMINARY eZ80F915050MOD eZ80F91 Module Product Specification iii Revision History Each instance in Table 1 reflects a change to this document from its previous revision. To see more detail, click the appropriate link in the table. Table 1. Revision History of this Document Date Revision Level Section July 2004 PS019310-0904 10 Page # Description Formatted to current publication standards All Ethernet PHY and RJ45 Connector section Part number change to AMD MII. 12 Bill of Materials for the eZ80F91 Module Part number change to internal crystal at jumper location Y3. 22 PRELIMINARY Revision History eZ80F915050MOD eZ80F91 Module Product Specification iv Table of Contents Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi The eZ80F91 Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Module Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 eZ80F91 Controller Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Peripheral Bus Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 I/O Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Onboard Component Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Logic-Level I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Onboard Battery Backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Ethernet PHY and RJ45 Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Ethernet LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Fast Buffer (U10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 IrDA Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Reset Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Serial Interface Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Document Number Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Change Log . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Module Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Customer Feedback Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 PS019310-0304 PRELIMINARY Table of Contents eZ80F915050MOD eZ80F91 Module Product Specification v List of Figures Figure 1. eZ80F91 Module Functional Block Diagram . . . . . . . . . . . . . . . . . . . 3 Figure 2. eZ80F91 Module Peripheral Bus Connector Pin Configuration—JP1 4 Figure 3. eZ80F91 Module I/O Connector Pin Configuration—JP2 . . . . . . . . . 8 Figure 4. Bus Contention Without the eZ80F91 Module Fast Buffer Feature . 15 Figure 5. Physical Dimensions of the eZ80F91 Module . . . . . . . . . . . . . . . . . 18 Figure 6. eZ80F91 Module—Top Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 7. eZ80F91 Module—Bottom Layer . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 8. eZ80F91 Module Schematic Diagram, #1 of 3—Connectors and Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 9. eZ80F91 Module Schematic Diagram, #2 of 3—CPU and PHY . . . 26 Figure 10. eZ80F91 Module Schematic Diagram, #3 of 3—Module Memory . . 27 PS019310-0304 PRELIMINARY List of Figures eZ80F915050MOD eZ80F91 Module Product Specification vi List of Tables Table 1. Revision History of this Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii Table 2. eZ80F91 Module Peripheral Bus Connector Pin Identification* . . . . . . . 5 Table 3. eZ80F91 Module I/O Connector Pin Identification* . . . . . . . . . . . . . . . . 8 Table 4. eZ80F91 Ethernet Module MII Resistor Configuration . . . . . . . . . . . . . 12 Table 5. Flash Memory Programming Signals and Jumpers . . . . . . . . . . . . . . . 16 Table 6. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 7. Bill of Materials for the eZ80F91 Module . . . . . . . . . . . . . . . . . . . . . . . 22 PS019310-0304 PRELIMINARY List of Tables eZ80F915050MOD eZ80F91 Module Product Specification 1 The eZ80F91 Module The eZ80F91 Module is a compact, high-performance Ethernet module specially designed for the rapid development and deployment of embedded systems requiring control and Internet/Intranet connectivity. This expandable module is powered by ZiLOG’s latest power-efficient, highspeed, optimized pipeline architecture eZ80F91 microcontroller, a member of ZILOG’s family of eZ80Acclaim! Flash Microcontrollers. The eZ80F91 is a high-speed single-cycle instruction-fetch microcontroller, which can operate with a clock speed of 50 MHz. It can operate in Z80-compatible addressing mode (64 KB) or full 24-bit addressing mode (16 MB). The rich peripheral set of the eZ80F91 Module makes it suitable for a variety of applications, including industrial control, IrDA connectivity, communication, security, automation, point-of-sale terminals, and embedded networking applications. Module Features PS019310-0904 • • • • • • • • • Factory-default operating clock frequency at 50 MHz • • • • Low-cost connection to carrier board via two 2x30pin headers 10/100 Base-T Ethernet PHY with RJ45 connector 512 KB fast SRAM 256 KB on-chip Flash memory 1 MB off-chip NOR Flash memory Battery-backed Real-Time Clock I/O connector provides 32 general-purpose 5 V-tolerant I/O pinouts ZiLOG’s industry-leading IrDA transceiver—ZiLOG ZHX1810 Onboard connector provides I/O bus for external peripheral connections (IRQ, CS, 24 address, 8 data) Small footprint 63.5mm x 78.7mm 3.3 V power supply Standard operating temperature range: 0ºC to +70ºC PRELIMINARY The eZ80F91 Module eZ80F915050MOD eZ80F91 Module Product Specification 2 eZ80F91 Controller Features • • • • The eZ80F91 device contains 256 KB of Flash memory and 8 KB of SRAM • Two UARTs with independent baud rate generators and support for 9-bit operation • • • • • SPI with independent clock generator • Flexible-priority vectored interrupts (both internal and external) and interrupt controller • Real-time clock with on-chip 32KHz oscillator, selectable 50/60Hz input, and separate VDD pin for battery backup • • • • • • • Four 16-bit Counter/Timers with prescalers and direct input/output drive Single-cycle instruction fetch, high-performance, pipelined eZ80® CPU core 10/100 Mbps Ethernet MAC with 8KB frame buffer Low power features including SLEEP mode, HALT mode, and selective peripheral power-down control I2C with independent clock generator Infrared Data Association (IrDA)-compliant infrared encoder/decoder New DMA-like eZ80® instructions for efficient block data transfer External interface with 4 chip selects, individual wait state generators, and an external WAIT input pin — supports Intel- and Motorola-style buses Watch-Dog Timer 32 bits of general-purpose I/O JTAG and ZDI debug interfaces 144-pin LQFP package 3.0–3.6 V supply voltage with 5V tolerant inputs Standard operating temperature range: 0ºC to +70ºC Block Diagram Figure 1 provides a block diagram of the eZ80F91 Module. PS019310-0904 PRELIMINARY The eZ80F91 Module eZ80F915050MOD eZ80F91 Module Product Specification 3 Figure 1. eZ80F91 Module Functional Block Diagram PS019310-0904 PRELIMINARY The eZ80F91 Module eZ80F915050MOD eZ80F91 Module Product Specification 4 Pin Description Peripheral Bus Connector Figure 2 illustrates the pin layout of the 60-pin Peripheral Bus Connector (JP1) of the eZ80F91 Module. The eZ80® Development Platform, however, features a 50pin connector. The eZ80F91 Module is designed to interface pin 60 of its JP1 connector to pin 50 of the eZ80® Development Platform’s JP1 connector so that pins 1–10 of the eZ80F91 Module overlap the edge of the eZ80® Development Platform. Table 2 identifies the pins and their functions. Figure 2. eZ80F91 Module Peripheral Bus Connector Pin Configuration—JP1 PS019310-0904 PRELIMINARY Pin Description eZ80F915050MOD eZ80F91 Module Product Specification 5 Note: All signals with an overline are active Low. For example, B/W, for which WORD is active Low, and B/W, for which BYTE is active Low. Table 2. eZ80F91 Module Peripheral Bus Connector Pin Identification* Pull Up/Down* Pin # Symbol 1 Reserved 2 Reserved 3 Reserved 4 Reserved 5 TRSTN 6 Reserved 7 F91_WE 8 Reserved 9 GND VSS/Ground (0 V). 10 VCC 3.3 V supply input pin. 11 A6 Bidirectional 12 A0 Bidirectional 13 A10 Bidirectional 14 A3 Bidirectional 15 GND VSS/Ground (0 V). 16 VCC 3.3 V supply input pin. 17 A8 Bidirectional 18 A7 Bidirectional 19 A13 Bidirectional 20 A9 Bidirectional 21 A15 Bidirectional PU 10 KΩ Signal Direction Comments Input Reset for On-Chip Instrumentation (OCI). Input A Low enables a Write to on-chip Flash memory. If this pin is unconnected, on-chip Flash memory is write-protected. Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10 pF to satisfy timing requirements for the CPU. All unused inputs should be pulled to either VDD or GND, depending on their inactive levels, to reduce power consumption and to reduce noise sensitivity. All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted. PS019310-0904 PRELIMINARY Pin Description eZ80F915050MOD eZ80F91 Module Product Specification 6 Table 2. eZ80F91 Module Peripheral Bus Connector Pin Identification* (Continued) Pull Up/Down* Pin # Symbol Signal Direction Comments 22 A14 Bidirectional 23 A18 Bidirectional 24 A16 Bidirectional 25 A19 Bidirectional 26 GND 27 A2 Bidirectional 28 A1 Bidirectional 29 A11 Bidirectional 30 A12 Bidirectional 31 A4 Bidirectional 32 A20 Bidirectional 33 A5 Bidirectional 34 A17 Bidirectional 35 Reserved 36 DIS_Flash 37 A21 38 VCC 39 A22 Bidirectional 40 A23 Bidirectional 41 CS0 Output 42 CS1 Output 43 CS2 Output 44 D0 PU 4kΩ Bidirectional 45 D1 PU 4kΩ Bidirectional VSS/Ground (0 V). PU 10 KΩ Input A Low disables onboard Flash memory. Flash is enabled if DIS_Flash is not connected; CMOS Input 3.3 V (5 V tolerant). Bidirectional 3.3 V supply input pin. Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10 pF to satisfy timing requirements for the CPU. All unused inputs should be pulled to either VDD or GND, depending on their inactive levels, to reduce power consumption and to reduce noise sensitivity. All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted. PS019310-0904 PRELIMINARY Pin Description eZ80F915050MOD eZ80F91 Module Product Specification 7 Table 2. eZ80F91 Module Peripheral Bus Connector Pin Identification* (Continued) Pin # Symbol Pull Up/Down* Signal Direction Comments 46 D2 PU 4kΩ Bidirectional 47 D3 PU 4kΩ Bidirectional 48 D4 PU 4kΩ Bidirectional 49 D5 PU 4kΩ Bidirectional 50 GND 51 D7 52 D6 Bidirectional 53 MREQ Bidirectional 54 IORQ Bidirectional 55 GND 56 RD Bidirectional 57 WR Bidirectional 58 INSTRD Output 59 BUSACK Output 60 BUSREQ VSS/Ground (0 V). PU 4kΩ Bidirectional VSS/Ground (0 V). PU 2kΩ Input Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10 pF to satisfy timing requirements for the CPU. All unused inputs should be pulled to either VDD or GND, depending on their inactive levels, to reduce power consumption and to reduce noise sensitivity. All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted. I/O Connector Figure 3 illustrates the pin layout of the 60-pin I/O Connector (JP2) of the eZ80F91 Module. The eZ80® Development Platform, however, features a 50-pin connector. The eZ80F91 Module is designed to interface pin 60 of its JP2 connector to pin 50 of the eZ80® Development Platform’s JP2 connector so that pins 1–10 of the eZ80F91 Module overlap the edge of the eZ80® Development Platform. Table 3 identifies the pins and their functions. PS019310-0904 PRELIMINARY Pin Description eZ80F915050MOD eZ80F91 Module Product Specification 8 Figure 3. eZ80F91 Module I/O Connector Pin Configuration—JP2 Table 3. eZ80F91 Module I/O Connector Pin Identification* Pull Up/Down Signal Direction Pin # Symbol 1 PA7 Bidirectional 2 PA6 Bidirectional 3 PA5 Bidirectional 4 PA4 Bidirectional Comments Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10 pF to satisfy timing requirements for the CPU. All unused inputs should be pulled to either VDD or GND, depending on their inactive levels, to reduce power consumption and to reduce noise sensitivity. All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted. PS019310-0904 PRELIMINARY Pin Description eZ80F915050MOD eZ80F91 Module Product Specification 9 Table 3. eZ80F91 Module I/O Connector Pin Identification* (Continued) Pull Up/Down Signal Direction Pin # Symbol Comments 5 PA3 Bidirectional 6 PA2 Bidirectional 7 PA1 Bidirectional 8 PA0 Bidirectional 9 VCC 3.3 V supply input pin. 10 GND VSS/Ground (0 V). 11 PB7 Bidirectional 12 PB6 Bidirectional 13 PB5 Bidirectional 14 PB4 Bidirectional 15 PB3 Bidirectional 16 PB2 Bidirectional 17 PB1 Bidirectional 18 PB0 Bidirectional 19 GND 20 PC7 Bidirectional 21 PC6 Bidirectional 22 PC5 Bidirectional 23 PC4 Bidirectional 24 PC3 Bidirectional 25 PC2 Bidirectional 26 PC1 Bidirectional 27 PC0 Bidirectional 28 PD7 Bidirectional 29 PD6 Bidirectional VSS/Ground (0 V). Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10 pF to satisfy timing requirements for the CPU. All unused inputs should be pulled to either VDD or GND, depending on their inactive levels, to reduce power consumption and to reduce noise sensitivity. All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted. PS019310-0904 PRELIMINARY Pin Description eZ80F915050MOD eZ80F91 Module Product Specification 10 Table 3. eZ80F91 Module I/O Connector Pin Identification* (Continued) Pull Up/Down Signal Direction Pin # Symbol Comments 30 GND 31 PD5 32 PD4 33 PD3 Bidirectional 34 PD2 Bidirectional 35 PD1 Bidirectional 36 PD0 Bidirectional 37 TDO Output JTAG Data Output pin. 38 TDI/ZDA Input JTAG Data Input pin. 39 GND 40 TRIGOUT 41 TCK/ZCL PU 10 KΩ Input JTAG Input. High on reset enables ZDI mode; Low on reset enables OCI debug. 42 TMS PU 10 KΩ Input JTAG Test Mode Select Input. 43 RTC_VDD 44 EZ80CLK 45 I2CSCL 46 GND 47 I2CSDA 48 GND 49 FlashWE 50 GND VSS/Ground (0 V). Bidirectional PD 4kΩ Bidirectional VSS/Ground (0 V). Output Active High trigger event indicator. RTC supply. For proper operation of the eZ80F91 Module, this pin must be connected to the same power source that powers the module (as is done on the ZiLOG development platform). PU 4kΩ Output Synchronous CPU clock output. Bidirectional I2C Bus Clock. VSS/Ground (0 V). PU 4kΩ Bidirectional I2C Data Clock. Power VSS/Ground (0 V). PU 10 KΩ Input A Low enables a Write to external Flash memory boot block area. If this pin is unconnected, the Flash memory boot block area is write-protected. VSS/Ground (0 V). Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10 pF to satisfy timing requirements for the CPU. All unused inputs should be pulled to either VDD or GND, depending on their inactive levels, to reduce power consumption and to reduce noise sensitivity. All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted. PS019310-0904 PRELIMINARY Pin Description eZ80F915050MOD eZ80F91 Module Product Specification 11 Table 3. eZ80F91 Module I/O Connector Pin Identification* (Continued) Pull Up/Down Signal Direction Pin # Symbol 51 CS3 52 DIS_IRDA PU 10 KΩ Input A Low disables the onboard IRDA transceiver to use PC0/PC1 UART pins externally. 53 RESET PU 2kΩ Bidirectional Reset Output from module or push-button reset. 54 WAIT PU 2kΩ Input Driving the WAIT pin Low forces the CPU to provide additional clock cycles for an external peripheral or external memory to complete its Read or Write operation. 55 VCC 3.3 V supply input pin. 56 GND VSS/Ground (0 V). 57 HALT_SLP 58 NMI PU 10 KΩ Schmitt Trigger The NMI input is a higher priority input than the Input, Active maskable interrupts. It is always recognized at the Low end of an instruction, regardless of the state of the interrupt enable control bits. This input includes a Schmitt trigger to allow RC rise times. This external NMI signal is combined with an internal NMI signal generated from the WDT block before being connected to the NMI input of the CPU. 59 VCC 3.3 V supply input pin. 60 Reserved Output Comments Used on the eZ80190, eZ80L92, eZ80F92, eZ80F93 devices and connected to the CS8900 EMAC. Output, Active A Low on this pin indicates that the CPU enters either Low HALT or SLEEP mode because of execution of either a HALT or SLP instruction. NC Reserved—No Connection. Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10 pF to satisfy timing requirements for the CPU. All unused inputs should be pulled to either VDD or GND, depending on their inactive levels, to reduce power consumption and to reduce noise sensitivity. All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted. PS019310-0904 PRELIMINARY Pin Description eZ80F915050MOD eZ80F91 Module Product Specification 12 Onboard Component Description Logic-Level I/Os The I/O connector features 32 general-purpose 3.3 V CMOS I/O pins that can be used as outputs or inputs interfacing to external logic. All I/Os are 5 V tolerant. Some of the General-Purpose I/O pins support dual mode functions (SPI, Timer I/O, UARTs and bit I/O with edge- or level-triggered interrupt functions on each pin). For more information on eZ80F91 dual modes, please refer to the eZ80F91 Product Specification (PS0192). Onboard Battery Backup An onboard Panasonic VL-1220-1VC 3V Lithium battery powers the 32kHz RealTime Clock when external power is removed. The battery is charged through diode CR1 and resistor R28 when external power is applied to the board. Ethernet PHY and RJ45 Connector The eZ80F91 Ethernet Module contains Advanced Micro Devices’ Am79C874 Media-Independent Interface (MII) and a HALO RJ45 with integrated magnetics (transformer and common-mode chokes) and two LED indicators. The MII enables different modes of Ethernet communication, configurable by resistors R19, R21, R23, and R24. The eZ80F91 Ethernet Module is shipped with all four resistors installed. Table 4, which lists the available resistor settings, is excerpted from the Am79C874 data sheet published by AMD. Table 4. eZ80F91 Ethernet Module MII Resistor Configuration R24 ANEG R19 R23 R21 (Tech[2]) (Tech[1]) (Tech[0]) Speed FullDuplex ANEG-EN Capabilities ANEG IN IN IN IN Yes1 Yes1 No All Disabled IN IN IN OUT No No No 10HD Disabled IN IN OUT IN No No No 100HD Disabled Notes: 1. MII Register 0 (Speed and Duplex Bits) must be set by a MAC to achieve a link. 2. When autonegotiation is enabled, these bits can be written but will be ignored by PHY. 3. The advertised abilities of MII Register 4 cannot exceed the abilities of MII Register 1. Autonegotiation should always be enabled. PS019310-0904 PRELIMINARY Onboard Component Description eZ80F915050MOD eZ80F91 Module Product Specification 13 Table 4. eZ80F91 Ethernet Module MII Resistor Configuration (Continued) R24 ANEG R19 R23 R21 (Tech[2]) (Tech[1]) (Tech[0]) Speed IN IN OUT FullDuplex ANEG-EN Capabilities ANEG OUT No No No 100HD Disabled Yes1 No All Disabled IN OUT IN IN Yes1 IN OUT IN OUT No No No 10FD Disabled IN OUT OUT IN No No No 100FD Disabled IN OUT OUT OUT No No No 100FD Disabled IN Yes2 Yes2 Yes3 None Enabled OUT Yes2 Yes2 Yes3 10HD Enabled Yes2 Yes3 100HD Enabled OUT IN OUT IN IN IN OUT IN OUT IN Yes2 OUT IN OUT OUT Yes2 Yes2 Yes3 100HD, 10HD Enabled IN Yes2 Yes2 Yes3 None Enabled OUT Yes2 Yes2 Yes3 10FD/HD Enabled Yes2 Yes3 100FD/HD Enabled Yes2 Yes3 All Enabled OUT OUT OUT OUT IN IN OUT OUT OUT IN Yes2 OUT OUT OUT OUT Yes3 Notes: 1. MII Register 0 (Speed and Duplex Bits) must be set by a MAC to achieve a link. 2. When autonegotiation is enabled, these bits can be written but will be ignored by PHY. 3. The advertised abilities of MII Register 4 cannot exceed the abilities of MII Register 1. Autonegotiation should always be enabled. Ethernet LEDs The Ethernet connection is provided by the HALO RJ45 connector. It contains two green LEDs that are located next to each other on the eZ80F91 Module. When PHY is receiving data, the left LED is on. When the PHY is transmitting data, the right LED is on. Fast Buffer (U10) The eZ80F91 Module’s fast buffer (see Figure 1 on page 3) exists to prevent bus contention that will occur because of slow turn-off time of the module’s external Flash and the fast bus turn-around time of the eZ80F91 (generic feature of the eZ80® family when it is used in native mode). Below is a short explanation of the problem related to bus contention when using eZ80 family of the microprocessors in native eZ80® mode. Refer to Figure 4 on PS019310-0904 PRELIMINARY Onboard Component Description eZ80F915050MOD eZ80F91 Module Product Specification 14 page 15 while reading the following discussion. Also see the eZ80F91 Product Specification (PS0192) for further details. Bus contention occurs when two or more devices drive a common bus. The eZ80F91's CS0 drives the Flash CE. After the access to Flash, CS0 is driven High a maximum of 8.8 ns after the next rising edge of the Clock (T6, Figure 4). The Flash turn-off time (TOD) is 25 ns, which is the time from OE or CE going High to the Flash output drivers going into High-Z mode. In other words, after the end of the eZ80F91 Read access to Flash, it takes 8.8 ns+25 ns = 33.8 ns before Flash stops driving the data bus. At this point, the eZ80F91 device is already well into the next bus cycle. Assume that the next cycle is Memory Write. During the Memory Write cycle, Data (output) from the eZ80F91 device is valid not later than T3 = 7.5 ns, and the Write pulse is asserted not later than 4.5 ns after the falling edge of the Clock (14.5 ns from the Rising edge if Clock is 50 MHz). It means that during TCON = (33.8 ns – 7.5 ns) = 26.3 ns; two devices drive the common Data Bus—the eZ80F91 device and Flash. In turn, data that is being written during the Write operation might be corrupted. The part used to isolate a slow Flash data bus from a fast eZ80F91 bus has 5.5 ns turn-off time, which reduces 25 ns part of the TCON to 5.5 ns. As a result, bus contention still occurs, but its duration is not 26.3 ns, as the following equation shows: Time of contention = (8.8 ns - 7.5 ns + 5.5 ns) = 6.8 ns Data being written is not corrupted because the Write pulse is not yet asserted. PS019310-0904 PRELIMINARY Onboard Component Description eZ80F915050MOD eZ80F91 Module Product Specification 15 Figure 4. Bus Contention Without the eZ80F91 Module Fast Buffer Feature Memory The eZ80F91 Module contains external Flash memory, and the eZ80F91 MCU contains internal Flash memory. To allow Read/Write access to Flash memory on the eZ80F91 Module, there are two signals provided, on connectors JP1 and JP2. A jumper JP3 on the module enables programming of on-chip Flash. There is also a signal that duplicates the function of this jumper. Table 5 describes the states of the signals and the status of the jumper for different modes. PS019310-0904 PRELIMINARY Onboard Component Description eZ80F915050MOD eZ80F91 Module Product Specification 16 Table 5. Flash Memory Programming Signals and Jumpers Signal/Jumper Function State/Status DIS_FLASH Controls Read/Write access to eZ80F91 Module external Flash When Low, access memory is enabled FlashWE Controls Write operations to the boot block of eZ80F91 Module When Low, Write is external Flash memory enabled JP3 Controls Write access to eZ80F91 MCU on-chip Flash memory When IN, Write is enabled F91_WE Controls Write access to eZ80F91 MCU on-chip Flash memory When Low, Write is enabled The eZ80F91 Module’s external Flash memory has an access time of 100 ns. At least five wait states must be added to the cycle when accessing external Flash at the 50MHz clock speed. eZ80F91 MCU on-chip Flash is faster; its minimum access time is 60 ns, which requires only three wait states at 50 MHz. There is 512 KB of fast SRAM on the eZ80F91 Module. Access time is 12 ns, which requires one wait-state access. The eZ80F91 on-chip SRAM can be used with zero wait states. IrDA Transceiver An onboard IrDA transceiver (ZiLOG ZHX1810) is connected to PD0 (TX), PD1 (RX), and PD2 (Shutdown, R_SD). The IrDA transceiver is of the LED type 870 nm Class 1. The receiver supply current is 90–150 µA and the transmitter supply current is 260 mA when the LED is active.The IrDA transceiver is accessible via the IrDA controller attached to UART0 on the eZ80F91 device. The UART0 console and the IrDA transceiver cannot be used simultaneously. To use the UART0 for console or to save power, the transceiver can be disabled by the software or by an off-board signal when using the proper jumper selection. The transceiver is disabled by setting PD2 (IR_SD) High or by pulling the DIS_IRDA pin on the I/O connector Low. The shutdown is used for power savings. To enable the IrDA transceiver, DIS_IRDA is left floating and PD2 is set to Low. Reset Generator The onboard Reset Generator Chip performs reliable Power-On Reset. The chip generates a reset pulse with a duration of 200 ms if the power supply drops below PS019310-0904 PRELIMINARY Onboard Component Description eZ80F915050MOD eZ80F91 Module Product Specification 17 2.93 V. This reset pulse ensures that the board always starts in a defined condition. The RESET pin on the I/O connector reflects the status of the RESET line. It is a bidirectional pin for resetting external peripheral components or for resetting the eZ80F91 Module with a low-impedance output (e.g. a 100-Ohm pushbutton). Serial Interface Ports The CPU contains two UARTs with programmable baud rate generators. UART0 is connected to GPIO PD[0:7] on the I/O connector. UART1 is connected to GPIO PC[0:7] on the I/O connector. Note: Do not connect an RS-232 interface without level shifters. There are no RS232-level shifters on the eZ80F91 Module. Physical Dimensions The footprint of the eZ80F91 Module PCB is 63.5 mm x 78.7 cm. With an RJ-45 Ethernet connector, the overall height is 25 mm. See Figure 5. PS019310-0904 PRELIMINARY Onboard Component Description eZ80F915050MOD eZ80F91 Module Product Specification 18 16.5 mm 56.0 mm eZ80F91 MODULE JP1 JP2 1 2 R15 R23 R16 R24 R25 Y1 1 R14 R21 R13 R19 R28 ZiLOG PCA: 99C0879-001 COPYRIGHT ZiLOG XTOOLS 2002 U6 + P2 JP3 ISO R17 R18 R36 R22 R20 CR1 VL1 U8 78.7 mm C21 C20 C19 C18 Y2 C40 U5 C22 Y3 U4 C12 C11 U1 R37 R3 C3 R10 R4 R6 C42 U2 C1 R29 U3 31.8 mm 63.5 mm Figure 5. Physical Dimensions of the eZ80F91 Module PS019310-0904 PRELIMINARY Onboard Component Description eZ80F915050MOD eZ80F91 Module Product Specification 19 Figure 6 illustrates the top layer silkscreen of the eZ80F91 Module. eZ80F91 MODULE JP1 JP2 1 2 Y1 1 R15 R14 R23 R21 R16 R13 R24 R19 R25 R28 U6 R17 JP3 ZiLOG PCA: 99C0879-001 P2 CR1 R18 R36 ISO R22 VL1 R20 U8 COPYRIGHT ZiLOG XTOOLS 2002 + C21 C20 C19 C18 Y2 C40 U5 C22 Y3 U4 U1 R37 C12 C11 R3 C3 R4 R6 C42 R10 U2 C1 R29 U3 Figure 6. eZ80F91 Module—Top Layer PS019310-0904 PRELIMINARY Onboard Component Description eZ80F915050MOD eZ80F91 Module Product Specification 20 Figure 7 illustrates the bottom layer silkscreen of the eZ80F91 Module. JP2 R35 DJP 2002 JP1 R34 1 2 C4 C7 C16 C13 C14 C50 C49 C48 C47 C53 C51 C52 C39 R11 R33 R31 R32 C17 C15 C44 C45 C46 C34 C35 C33 C26 C29 C25 C36 L1 C27 U9 C32 C9 C28 C31 C30 C10 C8 R9 R27 C24 C38 C5 R26 C23 R8 C37 C43 R2 C6 U10 R7 R1 R30 R12 C41 R5 C2 MADE IN U.S.A. ZiLOG FAB: 98C0879-001 REV A Figure 7. eZ80F91 Module—Bottom Layer Absolute Maximum Ratings Stresses greater than those listed in Table 6 can cause permanent damage to the device. These ratings are stress ratings only. Operation of the device at any condition outside those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. For improved reliability, unused inputs should be tied to one of the supply voltages (VDD or VSS). Table 6. Absolute Maximum Ratings Parameter Min Max Units 0 +70 ºC Storage temperature –45 +85 ºC Operating Humidity (RH @ 50ºC) 25% 90% — 3.6 Standard operating temperature Operating Voltage PS019310-0904 PRELIMINARY V Onboard Component Description eZ80F915050MOD eZ80F91 Module Product Specification 21 Document Number Description The Document Control Number that appears in the footer of each page of this document contains unique identifying attributes, as indicated in the following table: PS Product Specification 0193 Unique Document Number 10 Revision Number 0904 Month and Year Published Change Log PS019310-0904 Rev Date Purpose 01 December 2002 Original issue 02 January 2003 Minor content revision 03 February 2003 Minor content revision 04 June 2003 Minor content revision 05 June 2003 Minor content revision 06 August 2003 Hyperlink correction 07 December 2003 Typo correction 08 December 2003 Correction to BOM 09 March 2004 Correction to schematic 10 September 2004 Corrections to PHY section PRELIMINARY Document Number Description eZ80F915050MOD eZ80F91 Module Product Specification 22 Module Bill of Materials Table 7 lists the installed components of the eZ80F91 Module. Table 7. Bill of Materials for the eZ80F91 Module Part Name 98C0879-001 Fab, eZ80F91 Module, Rev. B 1 — 35-0180-12 IC, SRAM, 512Kx8, 12ns, 3V, 36-SOJ 1 U8 Alliance Semi. AS7C34096-12JC 35-0016-05 IC, 74LVC04, 3.3V, GATE, 14-SOIC 1 U1 Texas Instruments SN74LVC04AD 35-0720-10 IC, Flash, 1Mx8, 100ns, 3V, 40-TSSOP 1 U9 Micron Technologies MT28F008B3VG-10B 35-0719-00 IC, MAX6328, RESET, SOT-23 1 U3 Maxim Inc. MAX6328UR29-T ZHX1810 IC, IR Transceiver, Low Profile 1 U2 ZiLOG Inc. ZHX1810MV115THTR 35-0062-01 IC, 74LCX32, LV, QUAD OR, 14-TSSOP 1 U4 Fairchild Semi. 74LCX32MTC 35-0022-01 IC, AM7C874, PHY XCVR, 80QFP 1 U6 AMD AM79C874VC eZ80F91 IC, eZ80F91, 50MHZ, 144VQFP 1 U5 ZiLOG Inc. eZ80F91 35-0731-00 IC, 74CBTLV3861PWR, 24-TSSOP 1 U10 Texas Instruments SN74CBTLV3861PWR 48-1013-01 Diode, TVS Array, XCVR Prot, 8-SOIC 1 U9 Semtec LCDA15C-6 17-2005-70 CAP, 1000 pF, 50 V, Ceramic Chip, 0603 15 17-2005-66 CAP, 0.1 µF, 16 V, Ceramic Chip, 0603 28 C2,10, C15-30, C44-53 17-2005-54 CAP, 0.01 µF, 50 V, Ceramic Chip, 0603 1 C3 Panasonic ECJ-1VB1C103K 17-2005-83 CAP, 0.33 µF, 16 V, Ceramic Chip, 0603 1 C1 Panasonic ECJ-1VF1C334Z 17-2005-63 CAP, 560 pF, 50 V, Ceramic Chip, 0603 1 C6 Panasonic ECJ-1VC1H563K PS019310-0904 Qty. Jumper Location Manufacturer Part Number PRELIMINARY Prime Technologies C13, C14, Panasonic C31-43 ECJ-1VC1H561J Kemet Inc. C0603C104K5RAC Document Number Description eZ80F915050MOD eZ80F91 Module Product Specification 23 Table 7. Bill of Materials for the eZ80F91 Module (Continued) Part Name 17-2001-03 CAP, 12 pF, 50 V, Ceramic Chip, 0603 4 17-2001-05 CAP, 22PF, 50V, CER CHIP, 0603 2 C4, C7 PANASONIC ECJ-1VC1H220J 17-2001-20 CAP, 270PF, 50V, CER CHIP, 0603 1 C5 PANASONIC ECJ-1VC1H271J 17-2001-01 CAP, 5PF, 50V, CER CHIP, 0603 1 C8 PANASONIC ECJ-1VC1H050C 48-0051-00 DIODE, 1N5817, RCTFR 1 CR1 16-9005-33 INDUCTOR, 3.3 µH, 20%, 1210 SMD 1 L1 46-3001-03 Resistor, 10 KΩ, 1%, 1/16 W, 0603 SMT 15 46-3000-00 Resistor, 0 Ω, 1%, 1/16 W, 0603 SMT 4 R19, 21, 23, 24 " 46-3000-71 Resistor, 2.21 KΩ, 1%, 1/16W, 0603 SMT 2 R5, R6 " 46-3000-35 Resistor, 68 Ω, 1%, 1/16 W, 0603 SMT 1 R3 " 46-3000-02 RES, 2.2 Ω, 1%, 1/16W, 0603 SMT 1 R4 " 46-3000-32 RES, 49.9 Ω, 1%, 1/16W, 0603 SMT 4 R11, 31, 32, 33 " 46-3000-63 RES, 1 KΩ, 1%, 1/16W, 0603 SMT 1 R22 " 46-3000-56 RES, 499 Ω,1%, 1/16W, 0603 SMT 1 R26 " 46-3001-34 RES, 200 KΩ, 1%, 1/16W, 0603 SMT 1 R27 " 46-3000-47 RES, 221 Ω, 1%, 1/16W, 0603 SMT 1 R28 " 46-3000-51 RES, 332 Ω, 1%, 1/16W, 0603 SMT 2 R34, R35 " 46-3001-75 RES, 10 MΩ, 1%, 1/16W, 0603 SMT 1 R38 " 23-0000-25 XTAL, 25.0000 MHz, SER/RESN, HC49S 1 Y1 CITIZEN HC49US25.000MABJ 23-0000-50 XTAL, 50.0000 MHz, SER/RESN, HC49S 1 Y2 CITIZEN HC49US50.000MABJ PS019310-0904 Qty. Jumper Location Manufacturer Part Number PRELIMINARY C9, C11, Panasonic C12 ECJ-1VC1H120J MOTOROLA 1N5817 PANASONIC ELJ-PA3R3MF R3, 8, 10, Sprague R12-18, 420CK472X2PD R20, 25, 29, 30, 37 Document Number Description eZ80F915050MOD eZ80F91 Module Product Specification 24 Table 7. Bill of Materials for the eZ80F91 Module (Continued) Part Name 23-0006-00 Internal crystal, 32.768 KHz, SER/RESN, TF case 1 Y3 Fox NC-38 21-0907-01 Connector, RJ45, Fast jack,10/100 Base-T 1 P2 Halo Electronics HFJ11-2450E-L11 21-0055-02 Connector, HDR/PIN, .025SQ, double row 2 PS019310-0904 Qty. Jumper Location Manufacturer Part Number PRELIMINARY JP1, JP2 Harwin (backside) M-20-976-3622 Document Number Description eZ80F915050MOD eZ80F91 Module Product Specification Schematics 25 Figures 8 through 10 diagram the layout of the eZ80F91 Module. Ethernet circuiting devices are not loaded on the eZ80F91 Module. However, these devices appear in the following schematics for reference purposes. VCC VCC -CS[0..3] IICSDA IICSCL CLK_OUT -DIS_FLASH D[0..7] R1 -CS[0..3] 4.7K Connector 1 R2 4.7K IICSDA IICSCL 1 3 -TRSTN 5 -F91_WE 7 GND 9 A6 11 A10 13 GND 15 A8 17 A13 19 A15 21 A18 23 A19 25 A2 27 A11 29 A4 31 A5 33 35 A21 37 A22 39 -CS0 41 -CS2 43 D1 45 D3 47 D5 49 D7 51 -MREQ 53 GND 55 -WR 57 -BUSACK 59 IICSDA IICSCL CLK_OUT EZ80CLK -DIS_FLASH JP3 1 2 -FLASHWE RTC_VDD PA[0..7] PB[0..7] PC[0..7] PD[0..7] -RESET -RD -WR -IOREQ -MREQ -INSTRD -WAIT -HALT_SLP -BUSREQ -BUSACK -NMI WR_EN -FLASHWE RTC_VDD PA[0..7] PB[0..7] PC[0..7] PD[0..7] VCC -RESET -RD -WR -IOREQ -MREQ -INSTRD R5 2.2K -WAIT -HALT_SLP -WAIT -BUSREQ -BUSACK -BUSREQ Connector 2 JP1 R6 2.2K 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 PA7 1 PA5 3 PA3 5 PA1 7 VCC 9 PB7 11 PB5 13 PB3 15 PB1 17 GND 19 PC6 21 PC4 23 PC2 25 PC0 27 PD6 29 PD5 31 PD3 33 PD1 35 TDO 37 GND 39 TCK 41 RTC_VDD 43 IICSCL 45 IICSDA 47 -FLASHWE49 -CS3 51 -RESET 53 VCC 55 -HALT_SLP 57 VCC 59 VCC A0 A3 VCC A7 A9 A14 A16 GND A1 A12 A20 A17 -DIS_FLASH VCC A23 -CS1 D0 D2 D4 GND D6 -IOREQ -RD -INSTRD -BUSREQ HEADER 30x2/SM VCC U1A -F91_WE JP2 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 PA6 PA4 PA2 PA0 GND PB6 PB4 PB2 PB0 PC7 PC5 PC3 PC1 PD7 GND PD4 PD2 PD0 TDI TRIGOUT TMS EZ80CLK 1 2 -F91_WP -F91_WP 74LCX04 TSSOP14 R37 10K VCC R3 R4 C1 68R 330nF U2 2R7 (MMA 02 04) 5 VCC 1 LEDA PD0 2 TXD IRDA_SD 4 SD PD1 3 RXD 6 GND GND -DIS_IRDA -WAIT GND -NMI T D[0..7] A[0..23] ZHX1810 0 A[0..23] HEADER 30x2/SM VCC -NMI R7 R8 10K VCC U1B TDI TDO TRIGOUT TCK TMS -TRSTN U4A 1 R20 10K 3 4 3 2 74LCX04 TSSOP14 U1F 74LCX32 TSSOP14 U4D 12 R9 4.7K 13 12 VCC 11 13 VCC 74LCX04 TSSOP14 GND 74LCX32 TSSOP14 GND VCC U1C 5 6 DISABLE_IRDA PD2 = IR_SD 74LCX04 TSSOP14 U4B 4 6 C2 0.1µF IRDA_SD 5 74LCX32 TSSOP14 VCC 2 -RESET open-drain MAX6328UR29 SOT-23-L3 C3 0.01µF alternative: Maxim MAX6802UR29D3 VCC VCC GND RESET 1 -DIS_IRDA R10 10K U3 3 R12 10K VDD TDI TDO TRIGOUT TCK TMS -TRSTN GND 10K GND GND Figure 8. eZ80F91 Module Schematic Diagram, #1 of 3—Connectors and Miscellaneous PS019310-0904 PRELIMINARY Schematics eZ80F915050MOD eZ80F91 Module Product Specification 26 54 WAIT -BUSREQ -BUSREQ 57 BUSREQ -NMI 56 NMI 66 67 69 71 TMS TCK TDI TRSTN 55 RESET -NMI TMS TCK TDI -TRSTN -RESET -F91_WP TMS TCK TDI -TRSTN -RESET -F91_WP 144 WP CRS COL RXER RXDV RXD3 RXD2 RXD1 RXD0 RXCLK TXCLK 124 125 135 137 141 140 139 138 136 131 MII_CRS MII_COL MII_RXER MII_RXDV MII_RXD3 MII_RXD2 MII_RXD1 MII_RXD0 MII_RXCLK MII_TXCLK C6 GND 0.056µF R26 499 C5 220pF Y2 50MHz 83 FILT_IN 85 XOUT 86 XIN R27 L1 200K C8 C9 3.3µH 5pF 10pF C10 0.1µF VCC 6 14 22 31 47 59 81 87 88 98 112 122 133 VDD VDD VDD VDD VDD VDD VDD PLL_VDD VDD VDD VDD VDD VDD RTC_VDD RTC_VDD VCC 2 7 15 23 32 38 48 60 64 72 82 84 89 99 108 113 123 134 CR1 1 1N5817 R28 220 Y3 32.768KHz VL1 R38 C11 12pF 10M 63 62 61 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS PLL_VSS VSS VSS VSS VSS VSS VSS RTC_VDD RTC_XOUT RTC_XIN MII_TXD3 MII_TXD2 MII_TXD1 MII_TXD0 MII_TXEN MII_TXER MII_MDC MII_MDIO 126 127 128 129 130 132 142 143 IORQ MRQ RD WR BUSACK CS0 CS1 CS2 CS3 49 50 51 52 58 33 34 35 36 GND A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 U6 -CS0 -CS1 -CS2 -CS3 SCL SDA 1 2 3 5 7 8 9 14 15 16 17 18 19 20 PCSB ISODEF ISO REFCLK BURN_IN RST PWRDN PHYAD4_0RXDPHYAD3_10RXD+ PHYAD2_10TXD++ PHYAD1_10TXDPHYAD0_10TXD-GPIO0_10TXD-GPIO1_TP125 MDI0 MDC RXCLK 21 22 30 MDIO MDC RXCLK RXD3 RXD2 RXD1 RXD0 23 24 25 26 RXD3 RXD2 RXD1 RXD0 RXDV RXER TXCLK 29 31 33 RXDV RXER_RXD4 TXCLK_PCSBPCLK TXD3 TXD2 TXD1 TXD0 40 39 38 37 TXD3 TXD2 TXD1 TXD0 TXEN TXER COL CRS 34 32 41 42 TXEN TXER_TXD4 COL CRS -RESET R22 1K GND TXD3 TXD2 TXD1 TXD0 TXEN TXER MDC MDI0 -IORQ -MREQ -RD -WR R13 10K R18 10K -IORQ -MREQ -RD -WR -BUSACK -CS0 -CS1 -CS2 -CS3 110 109 PA7_PWM3 PA6_PWM2_EC1 PA5_PWM1_TOUT1 PA4_PWM0_TOUT0 PA3_PWM3_OC3 PA2_PWM2_OC2 PA1_PWM1_OC1 PA0_PWM0_OC0 121 120 119 118 117 116 115 114 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 107 106 105 104 103 102 101 100 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PA[0:7] PB7_MOSI PB6_MISO PB4_ICB3 PB4_ICA3 PB3_SCK PB2_SS PB0_IC1 PB0_IC0_EC0 97 96 95 94 93 92 91 90 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PB[0:7] PC7_RI1 PC6_DCD1 PC5_DSR1 PC4_DTR1 PC3_CTS1 PC2_RTS1 PC1_RXD1 PC0_TXD1 80 79 78 77 76 75 74 73 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC[0:7] PD7_RI0 PD6_DCD0 PD5_DSR0 PD4_DTR0 PD3_CTS0 PD2_RTS0 PD1_RXD0_IRRXD PD0_TXD0_IRTXD 65 111 53 70 68 VCC VCC SCL SDA HALT_SLP PHI INSTRD TDO TRIGOUT C12 12pF 1 2 3 4 5 8 9 10 11 12 13 16 17 18 19 20 21 24 25 26 27 28 29 30 10 13 27 36 49 52 59 60 73 79 80 -WAIT -WAIT A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 AM79C874 IICSCL IICSDA R19 PLLVCC OVDD1 VDD1 VDD2 OVDD2 CRVVCC ADOVCC EQVCC REFVCC TVCC1 TVCC2 D0 D1 D2 D3 D4 D5 D6 D7 INTR TECH_SEL2 TECH_SEL1 TECH_SEL0 ANEGA 43 53 54 55 56 IBREF 72 RPTR 61 LEDSPD0_LEDBTA_FXSEL 44 LECOL_SCRAMEN 45 LEDRX_LEDSEL 46 LEDTX_LEDBTB 47 LEDLNK_LED_10LNK 48 LESPD1_LEDTXA_CLK25EN 57 LEDDPX_LEDTXB 58 TEST3_SDI+ TEST2 TEST1_FXR+ TEST0_FXRFXT+ FXTXTLXTL+ TX+ TX- 62 68 67 66 69 70 74 75 77 78 RX+ RX- 64 63 TGND1 PLLGND OGND1 DGND1 DGND2 OGND2 CRVGND EQGND REFGND TGND2 39 40 41 42 43 44 45 46 GND A[0:23] U5 D0 D1 D2 D3 D4 D5 D6 D7 R23 R21 0 R24 0 R14 10K R15 10K R16 10K 0 0 R25 10K -LEDRX -LEDLNK C4 18pF Y1 25 MHz C7 18pF GND VCC C17 0.1µF P2 R11 49.9 GND VCC C44 0.1µF C45 0.1µF C49 0.1µF C46 0.1µF C50 0.1µF GND C47 0.1µF C51 0.1µF R17 10K 0.1% 4 11 12 28 35 50 51 65 71 76 D[0:7] C52 0.1µF C48 0.1µF VCC R32 49.9 R31 49.9 R34 330 R35 330 C53 0.1µF R33 49.9 C15 0.1µF C16 1 4 2 TX+ TXCT TX- 3 5 6 RX+ RXCT RX- 8 GND 9 10 11 12 AN1 CT1 AN2 CT2 0.1µF Put caps between pairs of U6, 10:11, 51:52, 59:65 and 71:73 as close to the pins as possible -LEDRX HFJ11-2450E-L11 -LEDLNK VCC C31 0.001µF C32 0.001µF C33 0.001µF C34 0.001µF C35 0.001µF C36 0.001µF C37 0.001µF C38 0.001µF C39 0.001µF C40 0.001µF C41 0.001µF C42 0.001µF C18 0.1µF C19 0.1µF C20 0.1µF C21 0.1µF C22 0.1µF C23 0.1µF C24 0.1µF C25 0.1µF C26 0.1µF C27 0.1µF C28 0.1µF C29 0.1µF C43 0.001µF GND C30 0.1µF VCC PD[0:7] -HALT_SLP CLK_OUT -INSTRD TDO TRIGOUT VCC VCC VCC GND GND EZ80F91 GND Figure 9. eZ80F91 Module Schematic Diagram, #2 of 3—CPU and PHY PS019310-0904 PRELIMINARY Schematics eZ80F915050MOD eZ80F91 Module Product Specification 27 U8 A18 A0 A1 A2 A3 -CS1 D0 D1 -CS1 -CS1 VCC VCC D2 D3 -WR A12 A9 A6 A4 A17 C13 0.001uF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 A0 A1 A2 A3 A4 CE I/O0 I/O1 VDD VSS I/O2 I/O3 WE A5 A6 A7 A8 A9 N.C. A18 A17 A16 A15 OE I/O7 I/O6 VSS VDD I/O5 I/O4 A14 A13 A12 A11 A10 N.C. 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 A16 A15 A14 A13 -RD D7 D6 VCC D5 D4 A11 A8 A10 A7 A5 512KB x 8 SRAM SOJ36.400 D[0:7] U9 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 VCC C14 0.001µF 21 20 19 18 17 16 15 14 8 7 36 6 5 4 3 2 1 40 13 37 23 39 VCC A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 VDD VDD A[0..23] VSS VSS A[0..23] A[0:23] 30 31 VCC U10 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 25 26 27 28 32 33 34 35 CE OE WE RP WP 22 24 9 10 12 VPP 11 N.C. N.C. 29 38 -DIS_FLASH -RD -WR -RD 2 5 6 9 10 15 16 19 20 23 -CSFLASH -RD -WR -RESET -WP 1A1 1A2 1A3 1A4 1A5 2A1 2A2 2A3 2A4 2A5 3 4 7 8 11 14 17 18 21 22 1OE 2OE 1 13 D0 D1 D2 D3 D4 D5 D6 D7 -CSFLASH 74CBTLV3384 SO24.300 VCC A21 A20 U4C U1D 9 -CS0 8 9 -FLASH_EN 8 -CSFLASH 10 74LCX32 TSSOP14 74LCX04 TSSOP14 -WR 1B1 1B2 1B3 1B4 1B5 2B1 2B2 2B3 2B4 2B5 Flash 1Mx8 3.3V TSOP40.20MM MT28F008B3VG R29 10K -DIS_FLASH DFLASH0 DFLASH1 DFLASH2 DFLASH3 DFLASH4 DFLASH5 DFLASH6 DFLASH7 VCC -CS0 VCC -CS0 VCC -RESET -RESET R30 10K GND U1E GND -FLASHWE -FLASHWE 11 10 -WP 74LCX04 TSSOP14 Figure 10. eZ80F91 Module Schematic Diagram, #3 of 3—Module Memory PS019310-0904 PRELIMINARY Schematics eZ80F915050MOD eZ80F91 Module Product Specification 28 Customer Feedback Form The eZ80F91 Module Product Specification If you experience any problems while operating this product, or if you note any inaccuracies while reading this Product Specification, please copy and complete this form, then mail or fax it to ZiLOG (see Return Information, below). We also welcome your suggestions! Customer Information Name Country Company Phone Address Fax City/State/Zip Email Product Information Serial # or Board Fab #/Rev. # Software Version Document Number Host Computer Description/Type Return Information ZiLOG System Test/Customer Support 532 Race Street San Jose, CA 95126 Phone: (408) 558-8500 Fax: (408) 558-8536 ZiLOG Customer Support Problem Description or Suggestion Provide a complete description of the problem or your suggestion. If you are reporting a specific problem, include all steps leading up to the occurrence of the problem. Attach additional pages as necessary. _____________________________________________________________________________________________ _____________________________________________________________________________________________ _____________________________________________________________________________________________ _____________________________________________________________________________________________ _____________________________________________________________________________________________ PS019310-0904 PRELIMINARY Customer Feedback Form