ZILOG EZ80190

eZ801905050MOD
eZ80190 Module
Product Specification
PS019101-1003
PRELIMINARY
ZiLOG Worldwide Headquarters • 532 Race Street • San Jose, CA 95126
Telephone: 408.558.8500 • Fax: 408.558.8300 • www.ZiLOG.com
This publication is subject to replacement by a later edition. To determine whether
a later edition exists, or to request copies of publications, contact:
ZiLOG Worldwide Headquarters
532 Race Street
San Jose, CA 95126
Telephone: 408.558.8500
Fax: 408.558.8300
www.ZiLOG.com
ZiLOG is a registered trademark of ZiLOG Inc. in the United States and in other countries. All other
products and/or service names mentioned herein may be trademarks of the companies with which
they are associated.
Document Disclaimer
© 2003 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices,
applications, or technology described is intended to suggest possible uses and may be superseded.
ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF
ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS
DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY
INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR
TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Except with the express written approval
ZiLOG, use of information, devices, or technology as critical components of life support systems is
not authorized. No licenses or other rights are conveyed, implicitly or otherwise, by this document
under any intellectual property rights.
PS019101-1003
PRELIMINARY
eZ801905050MOD
eZ80190 Module Product Specification
iii
Table of Contents
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v
The eZ80190 Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Module Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
eZ80190 Processor Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
I/O Connector (JP2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Peripheral Bus Connector (JP1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Onboard Component Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Logic-Level I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Onboard Battery Backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Ethernet Media Access Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Ethernet LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Ethernet Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
GPIO Pins for Enabling LAN Activity, Sleep, Interrupt . . . . . . . . . . . . . 13
EMAC Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
EMAC Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Static RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Real-Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Reset Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Serial Interface Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
ESD/EMI Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Document Number Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Change Log . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Schematic Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Customer Feedback Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
PS019101-1003
PRELIMINARY
Table of Contents
eZ801905050MOD
eZ80190 Module Product Specification
iv
List of Figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
PS019101-1003
eZ80190 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 3
eZ80190 Module Peripheral Bus Connector Pin Configuration—JP1 4
eZ80190 Module I/O Connector Pin Configuration—JP2 . . . . . . . . . 8
Physical Dimensions of the eZ80190 Module . . . . . . . . . . . . . . . . . 17
eZ80190 Module—Top Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
eZ80190 Module—Bottom Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Power Supply Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
eZ80190 Module Schematic Diagram, #1 of 9—CPU . . . . . . . . . . . 23
eZ80190 Module Schematic Diagram, #2 of 9—36-Pin SRAM
Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
eZ80190 Module Schematic Diagram, #3 of 9—NOR Flash Device 25
eZ80190 Module Schematic Diagram, #4 of 9—Ethernet Module . 26
eZ80190 Module Schematic Diagram, #5 of 9—Ethernet Module
Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
eZ80190 Module Schematic Diagram, #6 of 9—Ethernet Module
Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
eZ80190 Module Schematic Diagram, #7 of 9—Headers . . . . . . . . 29
eZ80190 Module Schematic Diagram, #8 of 9—Power Supply . . . 30
PRELIMINARY
List of Figures
eZ801905050MOD
eZ80190 Module Product Specification
v
List of Tables
Table 1. eZ80190 Module Peripheral Bus Connector Pin Identification. . . . . . . . 5
Table 2. eZ80190 Module I/O Connector Pin Identification . . . . . . . . . . . . . . . . . 8
Table 3. Ethernet Connector Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 4. Chip Frequency to Wait State Cycle Time Calculation. . . . . . . . . . . . . 14
Table 5. Real-Time Clock Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 6. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
PS019101-1003
PRELIMINARY
List of Tables
eZ801905050MOD
eZ80190 Module Product Specification
1
The eZ80190 Module
The eZ80190 Module is a compact, high-performance Ethernet module specially
designed for the rapid development and deployment of embedded systems
requiring control and Internet/Intranet connectivity. It features the low-cost
eZ80190 microprocessor powered by ZiLOG’s latest power-efficient, high-speed
eZ80® CPU.
The eZ80190 microprocessor is a high-speed single-cycle instruction-fetch microprocessor, which can operate with a clock speed of 50 MHz. It can operate in Z80compatible addressing mode (64 KB) or full 24-bit addressing mode (16 MB).
The rich peripheral set of the eZ80190 makes it suitable for a variety of applications, including industrial control, communication, security, automation, point-ofsale terminals, and embedded networking applications.
Module Features
•
•
•
•
•
•
•
eZ80190 microprocessor operating at 50 MHz
•
•
•
Small footprint 78.7 mm x 63.5 mm; height is 24 mm
Ethernet Media Access Controller+ PHY with RJ45 connector
512 KB zero-wait-state onboard SRAM
1 MB onboard NOR Flash ROM (90–100 ns)
Real-Time Clock with 32.768 kHz Crystal with battery backup
I/O connector provides 32 general-purpose 5 V-tolerant I/O pinouts
Onboard peripheral bus connector provides I/O bus for external peripheral connections (IRQ, CS, 24 address, 8 data)
Module operates from external 3.3 V power supply
Standard operating temperature range: 0ºC to +70ºC
eZ80190 Processor Features
•
•
•
•
PS019101-1003
Single-cycle instruction fetch, high-performance, pipelined eZ80® CPU core
Low power features including SLEEP mode and HALT mode
Two UARTs with independent baud rate generators
Two SPI interfaces with independent clock rate generators
PRELIMINARY
The eZ80190 Module
eZ801905050MOD
eZ80190 Module Product Specification
2
•
•
•
•
Two I2C interfaces with independent clock rate generators
•
Fixed-priority vectored interrupts (both internal and external) and interrupt controller
•
•
•
•
•
•
•
Six 16-bit Counter/Timers with prescalers and direct input/output drive
Fast multiply accumulate unit (MACC)
DMA Controller for fast memory-to-memory transfers
Glueless external memory and I/O interface featuring 4 chip selects with individual
wait state generators
Watch-Dog Timer
32 bits of general-purpose I/O
2-wire ZDI debug interface
100-pin LQFP package
3.3 V ± 0.3 V supply voltage with 5V tolerant inputs
Standard operating temperature range: 0ºC to +70ºC
Note: All signals with an overline are active Low. For example, B/W, for which
WORD is active Low, and B/W, for which BYTE is active Low.
PS019101-1003
PRELIMINARY
eZ80190 Processor Features
eZ801905050MOD
eZ80190 Module Product Specification
3
Block Diagram
Figure 1 illustrates a block diagram of the eZ80190 microprocessor.
Power-On
Reset
eZ80 CPU
6 x 16-Bit
Timer
GPIO
UART
SPI
I2C
PB
GPIO
60-Pin Bus Connector
PC
GPIO
UART
SPI
I2C
32-Bit GPIO
60-Pin I/O Connector
PD
50MHz
Oscillator
ZDI
ZDI
Watch-Dog
Timer
MACC
PA
GPIO
DMA
2
IC
Gold
Cap
RTC
32 kHz XTAL
Bus Controller
8-Bit Data
24-Bit Address
1 MB
Flash/ROM
512 KB SRAM
EMAC
RJ45
LEDs
Figure 1. eZ80190 Functional Block Diagram
PS019101-1003
PRELIMINARY
eZ80190 Processor Features
eZ801905050MOD
eZ80190 Module Product Specification
4
Pin Description
I/O Connector (JP2)
Figure 2 illustrates the pin layout of the 60-pin Peripheral Bus Connector (JP1) of
the eZ80190 Module. The eZ80® Development Platform, however, features a 50pin connector. The eZ80190 Module is designed to interface pin 60 of its JP1 connector to pin 50 of the eZ80® Development Platform’s JP1 connector so that pins
1–10 of the eZ80190 Module overlap the edge of the eZ80® Development Platform. Table 1 identifies the pins and their functions.
Figure 2. eZ80190 Module
Peripheral Bus Connector Pin Configuration—JP1
PS019101-1003
PRELIMINARY
Pin Description
eZ801905050MOD
eZ80190 Module Product Specification
5
Table 1. eZ80190 Module Peripheral Bus Connector Pin Identification*
Pull
Up/Down*
Pin #
Symbol
1
Reserved
2
Reserved
3
Reserved
4
Reserved
5
TRSTN
6
Reserved
7
F91_WE
8
Reserved
9
GND
VSS/Ground (0 V).
10
VCC
3.3 V supply input pin.
11
A6
Bidirectional
12
A0
Bidirectional
13
A10
Bidirectional
14
A3
Bidirectional
15
GND
VSS/Ground (0 V).
16
VCC
3.3 V supply input pin.
17
A8
Bidirectional
18
A7
Bidirectional
19
A13
Bidirectional
20
A9
Bidirectional
21
A15
Bidirectional
22
A14
Bidirectional
PU 10 KΩ
Signal Direction Comments
Input
Reset for On-Chip Instrumentation (OCI);
not used with the eZ80190 Module.
Input
A Low enables a Write to on-chip Flash
memory. If this pin is unconnected, on-chip
Flash memory is write-protected; not used
with the eZ80190 Module.
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10 pF to satisfy
timing requirements for the CPU.
All unused inputs should be pulled to either VDD or GND, depending on their inactive levels, to reduce power
consumption and to reduce noise sensitivity.
To prevent EMI, the EZ80CLK output can be deactivated via software in the eZ80190 Peripheral Power-Down
Register.
All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted.
PS019101-1003
PRELIMINARY
I/O Connector (JP2)
eZ801905050MOD
eZ80190 Module Product Specification
6
Table 1. eZ80190 Module Peripheral Bus Connector Pin Identification* (Continued)
Pull
Up/Down*
Pin #
Symbol
Signal Direction Comments
23
A18
Bidirectional
24
A16
Bidirectional
25
A19
Bidirectional
26
GND
27
A2
Bidirectional
28
A1
Bidirectional
29
A11
Bidirectional
30
A12
Bidirectional
31
A4
Bidirectional
32
A20
Bidirectional
33
A5
Bidirectional
34
A17
Bidirectional
35
Reserved
36
DIS_Flash
37
A21
38
VCC
39
A22
Bidirectional
40
A23
Bidirectional
41
CS0
Output
42
CS1
Output
43
CS2
Output
44
D0
PU 4k7Ω
Bidirectional
45
D1
PU 4k7Ω
Bidirectional
VSS/Ground (0 V).
PU 10 KΩ
Input
A Low disables onboard Flash memory.
Flash is enabled if DIS_Flash is not
connected; CMOS Input 3.3 V (5 V tolerant).
Bidirectional
3.3 V supply input pin.
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10 pF to satisfy
timing requirements for the CPU.
All unused inputs should be pulled to either VDD or GND, depending on their inactive levels, to reduce power
consumption and to reduce noise sensitivity.
To prevent EMI, the EZ80CLK output can be deactivated via software in the eZ80190 Peripheral Power-Down
Register.
All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted.
PS019101-1003
PRELIMINARY
I/O Connector (JP2)
eZ801905050MOD
eZ80190 Module Product Specification
7
Table 1. eZ80190 Module Peripheral Bus Connector Pin Identification* (Continued)
Pin #
Symbol
Pull
Up/Down*
Signal Direction Comments
46
D2
PU 4k7Ω
Bidirectional
47
D3
PU 4k7Ω
Bidirectional
48
D4
PU 4k7Ω
Bidirectional
49
D5
PU 4k7Ω
Bidirectional
50
GND
51
D7
52
D6
Bidirectional
53
MREQ
Bidirectional
54
IORQ
Bidirectional
55
GND
56
RD
Bidirectional
57
WR
Bidirectional
58
INSTRD
Output
59
BUSACK
Output
60
BUSREQ
VSS/Ground (0 V).
PU 4k7Ω
Bidirectional
VSS/Ground (0 V).
PU 2k2Ω
Input
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10 pF to satisfy
timing requirements for the CPU.
All unused inputs should be pulled to either VDD or GND, depending on their inactive levels, to reduce power
consumption and to reduce noise sensitivity.
To prevent EMI, the EZ80CLK output can be deactivated via software in the eZ80190 Peripheral Power-Down
Register.
All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted.
Peripheral Bus Connector (JP1)
Figure 3 illustrates the pin layout of the 60-pin I/O Connector (JP2) of the eZ80190
Module. The eZ80® Development Platform, however, features a 50-pin connector.
The eZ80190 Module is designed to interface pin 60 of its JP2 connector to pin 50
of the eZ80® Development Platform’s JP2 connector so that pins 1–10 of the
eZ80190 Module overlap the edge of the eZ80® Development Platform. Table 2
identifies the pins and their functions.
PS019101-1003
PRELIMINARY
Peripheral Bus Connector (JP1)
eZ801905050MOD
eZ80190 Module Product Specification
8
Figure 3. eZ80190 Module
I/O Connector Pin Configuration—JP2
Table 2. eZ80190 Module I/O Connector Pin Identification*
Pull
Up/Down
Signal
Direction
Pin #
Symbol
1
PA7
Bidirectional
2
PA6
Bidirectional
3
PA5
Bidirectional
Comments
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10 pF to satisfy
timing requirements for the CPU.
All unused inputs should be pulled to either VDD or GND, depending on their inactive levels, to reduce power
consumption and to reduce noise sensitivity.
To prevent EMI, the EZ80CLK output can be deactivated via software in the eZ80190 Peripheral Power-Down
Register.
All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted.
PS019101-1003
PRELIMINARY
Peripheral Bus Connector (JP1)
eZ801905050MOD
eZ80190 Module Product Specification
9
Table 2. eZ80190 Module I/O Connector Pin Identification* (Continued)
Pull
Up/Down
Signal
Direction
Pin #
Symbol
Comments
4
PA4
Bidirectional
5
PA3
Bidirectional
6
PA2
Bidirectional
7
PA1
Bidirectional
8
PA0
Bidirectional
9
VCC
3.3 V supply input pin.
10
GND
VSS/Ground (0 V).
11
PB7
Bidirectional
12
PB6
Bidirectional
13
PB5
Bidirectional
14
PB4
Bidirectional
15
PB3
Bidirectional
16
PB2
Bidirectional
17
PB1
Bidirectional
18
PB0
Bidirectional
19
GND
20
PC7
Bidirectional
21
PC6
Bidirectional
22
PC5
Bidirectional
23
PC4
Bidirectional
24
PC3
Bidirectional
25
PC2
Bidirectional
26
PC1
Bidirectional
27
PC0
Bidirectional
VSS/Ground (0 V).
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10 pF to satisfy
timing requirements for the CPU.
All unused inputs should be pulled to either VDD or GND, depending on their inactive levels, to reduce power
consumption and to reduce noise sensitivity.
To prevent EMI, the EZ80CLK output can be deactivated via software in the eZ80190 Peripheral Power-Down
Register.
All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted.
PS019101-1003
PRELIMINARY
Peripheral Bus Connector (JP1)
eZ801905050MOD
eZ80190 Module Product Specification
10
Table 2. eZ80190 Module I/O Connector Pin Identification* (Continued)
Pull
Up/Down
Signal
Direction
Pin #
Symbol
Comments
28
PD7
Bidirectional
29
PD6
Bidirectional
30
GND
31
PD5
32
PD4
33
PD3
Bidirectional
34
PD2
Bidirectional
35
PD1
Bidirectional
36
PD0
Bidirectional
37
TDO
Output
ZDI Data Output pin; not used with the eZ80190
Module.
38
TDI
Input
ZDI Data Input pin.
39
GND
40
TRIGOUT
41
TCK
42
TMS
43
RTC_VDD
44
EZ80CLK
45
I2CSCL
46
GND
47
I2CSDA
48
GND
VSS/Ground (0 V).
Bidirectional
PD 4k7
Bidirectional
VSS/Ground (0 V).
Output
Active High trigger event indicator; not used with the
eZ80190 Module.
PU 10 KΩ
Input
ZDI Clock. High on reset enables ZDI mode; Low on
reset enables OCI debug.
PU 10 KΩ
Input
JTAG Test Mode Select Input; not used with the
eZ80190 Module.
RTC supply from GoldCap (or external battery).
PU 4k7
Output
Synchronous CPU clock output.
Bidirectional
I2C Bus Clock.
VSS/Ground (0 V).
PU 4k7
Bidirectional
I2C Data Clock.
Power
VSS/Ground (0 V).
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10 pF to satisfy
timing requirements for the CPU.
All unused inputs should be pulled to either VDD or GND, depending on their inactive levels, to reduce power
consumption and to reduce noise sensitivity.
To prevent EMI, the EZ80CLK output can be deactivated via software in the eZ80190 Peripheral Power-Down
Register.
All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted.
PS019101-1003
PRELIMINARY
Peripheral Bus Connector (JP1)
eZ801905050MOD
eZ80190 Module Product Specification
11
Table 2. eZ80190 Module I/O Connector Pin Identification* (Continued)
Pin #
Symbol
Pull
Up/Down
Signal
Direction
49
FlashWE
PU 10 KΩ
Input
50
GND
51
CS3
52
DIS_IRDA
53
Comments
A Low enables a Write to external Flash memory
boot block area. If this pin is unconnected, the Flash
memory boot block area is write-protected.
VSS/Ground (0 V).
Output
Connected to the CS8900 EMAC.
PU 10 KΩ
Input
A Low disables the onboard IRDA transceiver to use
PC0/PC1 UART pins externally; not used with the
eZ80190 Module.
RESET
PU 2k2
Bidirectional
Reset Output from module or push-button reset.
54
WAIT
PU 2k2
Input
Driving the WAIT pin Low forces the CPU to provide
additional clock cycles for an external peripheral or
external memory to complete its Read or Write operation; not used with the eZ80190 Module.
55
VCC
3.3 V supply input pin.
56
GND
VSS/Ground (0 V).
57
HALT_SLP
58
NMI
59
VCC
60
Reserved
Output, Active A Low on this pin indicates that the CPU enters
Low
either HALT or SLEEP mode because of execution
of either a HALT or SLP instruction.
PU 10 KΩ
Schmitt Trigger Input,
Active Low
The NMI input is a higher priority input than the
maskable interrupts. It is always recognized at the
end of an instruction, regardless of the state of the
interrupt enable control bits. This input includes a
Schmitt trigger to allow RC rise times. This external
NMI signal is combined with an internal NMI signal
generated from the WDT block before being connected to the NMI input of the CPU.
3.3 V supply input pin.
NC
Reserved—No Connection.
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10 pF to satisfy
timing requirements for the CPU.
All unused inputs should be pulled to either VDD or GND, depending on their inactive levels, to reduce power
consumption and to reduce noise sensitivity.
To prevent EMI, the EZ80CLK output can be deactivated via software in the eZ80190 Peripheral Power-Down
Register.
All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted.
PS019101-1003
PRELIMINARY
Peripheral Bus Connector (JP1)
eZ801905050MOD
eZ80190 Module Product Specification
12
Onboard Component Description
Logic-Level I/Os
The I/O connector features 32 general-purpose 3.3 V CMOS I/O pins that can be
used as outputs or inputs interfacing to external logic. All I/Os are 5 V tolerant.
Some of the General-Purpose I/O pins support dual mode functions (SPI, I2C,
UARTs, and bit I/O with edge- or level-triggered interrupt functions on each pin).
For more information on eZ80190 dual modes, please refer to the eZ80190 Product Specification (PS0066).
Onboard Battery Backup
An onboard 0.1 F capacitor (GoldCap) is used to bridge power outages of 2–4
hours if the power supply to the module is disconnected. The capacitor is charged
to 3.1 V during normal operation and is discharged through the on-chip Real Time
Clock. The VRTC pin is available on the I/O connector of the module to connect
external components to a power supply or to a larger GoldCap.
Caution: Do not connect a Lithium Battery to the GoldCap capacitor, because
onboard charging circuitry for the capacitor can destroy the lithium
battery.
Ethernet Media Access Controller
The eZ80190 contains a CS8900A EMAC which is attached to the data/address
bus of the processor. This chip is connected to the processor’s CS3 Chip Select,
A0–A3, D0–D7, RD, WR, and PD4 pins for interrupt purposes. Connection of pins
PD6 and PD7 for LANACT (wake-up from sleep) and SLEEP is optional and resistor-selectable onboard.
Ethernet LEDs
There are two green LEDs, a Link LED and a LAN LED, that are located adjacent
to each other on the eZ80190 Module. A steady LAN LED (top) indicates received
link pulses from the Ethernet. A flashing Link LED (bottom) indicates Traffic (RX or
TX) on the LAN.
PS019101-1003
PRELIMINARY
Onboard Component Description
eZ801905050MOD
eZ80190 Module Product Specification
13
An RJ45 loopback connector can be used to verify the correct operation of the
Receiver and the Transmitter. The green LED should be on if RX+ is connected
with TX+ and RX– is connected with TX–.
Ethernet Connector
The eZ80190 is equipped with an RJ45 connector that features integrated magnetics (transformer, common mode chokes). The remaining pins on the onboard
RJ45 connector are not connected.
Node assignments for the RJ45 Ethernet connector are shown in Table 3.
Table 3. Ethernet Connector Pin Assignments
Pin
Function
1
TX+
2
TX–
3
RX+
6
RX–
Node assignment, in contrast to hub assignment, means that a straight-through
cable (equivalent pin numbers on both sides of the cable are connected to each
other) is used to attach the board to an Ethernet hub or switch. To connect the
eZ80190 Module directly to another node (e.g., a personal computer), a crossover
cable must be used.
The EMAC can be additionally protected by placing a U9 ESD protection array on
the module. This array can be either of the LCDA15C-6 (Semtech) or ESDA25B1
(ST Microelectronics) devices.
GPIO Pins for Enabling LAN Activity, Sleep, Interrupt
GPIO input bit PD4 serves as an active High interrupt input for the EMAC’s
INTRQ0 output.
GPIO output bit PD7 can be used to place the EMAC into SLEEP mode. In
SLEEP mode, the CS8900 draws less current, because only the receiver is operating. A zero-Ohm resistor at position R14 on the eZ80190 is required for this
function. In this case, the PD6 pin is not available for GPIO on the I/O connector.
If LAN activity is detected, the LANACT signal is pulled Low. The LANACT is connected to GPIO input PD6 and can be used in interrupt edge-detection mode to
wake up and reinitialize the Ethernet chip. A zero-Ohm resistor at position R15 on
PS019101-1003
PRELIMINARY
Ethernet Media Access Controller
eZ801905050MOD
eZ80190 Module Product Specification
14
the module is required for this function. In this case, the PD6 pin is not available
for GPIO on the I/O connector.
EMAC Ports
The I/O base address is user-selectable. The EMAC is connected as an 8-bit
device.
EMAC Access
For 50MHz operation, set CS3_CTL (I/O address 0xB3) to 0xF8 (7 wait states for
I/O). CS3 is used for selecting the Ethernet MAC. By pulling JP1 pin 25 (DIS_Eth)
Low, access to the Ethernet MAC can be disabled on a per-cycle basis.
Memory
The eZ80190 offers SRAM and Flash memories and the wait states that support
memory operations, as described in this section.
Wait States
To ensure that valid data is read from or written to slower memories, a number of
wait states must be inserted into the memory or I/O access operations by the processor. The number of wait states that are required should be added by programming the chip select control registers. To calculate the minimum number of wait
states required, refer to Table 4.
Table 4. Chip Frequency to Wait State Cycle Time Calculation
MHz
Cycle Time
20
50.0 ns
24
41.7 ns
40
25.0 ns
50
20.0 ns
Static RAM
The eZ80190 features 512 KB of fast SRAM. Access speed is typically 12 ns or
faster, allowing zero-wait-state operation at 50 MHz. With the CPU at 50 MHz,
PS019101-1003
PRELIMINARY
Memory
eZ801905050MOD
eZ80190 Module Product Specification
15
onboard SRAM can be accessed with zero wait states. The CS1_CTL register can
be set to 08h (no wait states).
Flash Memory
The Flash Boot Loader, application code, and user configuration data are held
permanently in NOR Flash memory. A typical application requires eight times
more ROM for code than RAM. As an example, for 128 KB onboard SRAM, 1 MB
of ROM is required. The eZ80190 allows NOR Flash memories between
4 megabits (512 KB) and 32 megabits (4 MB) to be used. The chips are housed in
wide TSOP40 cases. Typical Flash ROM access time is 100 ns.
For 50 MHz CPU operation, set the Chip Select Control register CS0_CTL (I/O
address 0xAA) to 0xA8. This setting selects 5 wait states. CS0 is used for selecting Flash memory. By pulling JP1 pin 26 (DIS_Flash) Low, access to Flash memory can be disabled on a per-cycle basis.
Real-Time Clock
An onboard real-time-clock operates continually, even if the system power supply
is down. An onboard capacitor (GoldCap) or external accumulator/battery serves
as a standby power supply. The Real-Time-Clock M41T11 contains Binary Coded
Decimal (BCD) counting registers for Seconds, Minutes, Hours, Day, Month, and
Year; a Century bit and 56 bytes of backed-up RAM are also included. The fully
charged 0.1 F GoldCap bridges power outages with a maximum of 4 hours. The
GoldCap, in contrast to a battery or an accumulator, offers the dual advantage of
no service (replacement) requirements and no effects upon memory.
The I2C addresses of the RTC are 0xD0 for WRITE and 0xD1 for READ. The I2C
sequence for writing to the RTC is:
Start → 0xD0 → RegNo → VALUE1 → … → VALUEn → Stop
and the sequence for reading from the RTC is:
Start → 0xD1 → RegNo → VALUE1 → … → VALUEn → Stop
where VALUE1…VALUEn… are sent by the RTC. The processor (I2C Master)
requests another value by sending an ACK. The first register to be read is set by a
preceding WRITE sequence, without sending data values. Clock updates do not
occur while any of the seven clock registers are being read. See Figure 5.
PS019101-1003
PRELIMINARY
Real-Time Clock
eZ801905050MOD
eZ80190 Module Product Specification
16
Table 5. Real-Time Clock Registers
Data
D7
0
ST
10 Seconds
Seconds
Seconds
00–59
1
X
10 Minutes
Minutes
Minutes
00–59
2
CEB*
CB
Hours
Hours
0–1/00–23
3
X
X
Day
01–07
4
X
X
Date
Date
01-31
5
X
X
Month
Month
01–12
Years
Year
00–99
6
7
D6
D5
FT
D3
10 Hours
X
X
X
S
D2
D1
X
10 Date
10 Years
OUT
D4
10 M.
Day
Calibration
D0
Function/Range BCD
Format
Address
Control
Notes: *When CEB is set to 1, CB toggles from 0 to 1 or from 1 to 0 every 100 years, depending upon the initial vale
set. When CEB is set to 0, CB does not toggle.
Keys: S = Sign bit, FT = Frequency Test bit, ST = Stop bit, OUT = Output level, X = Don’t care, CEB = Century
Enable bit, CB = Century Bit.
For further details, please refer to the M41T11 data sheet from SGS-Thomson at
www.st.com.
Reset Generator
The onboard Reset Generator Chip performs reliable Power-On Reset. The chip
generates a reset pulse with a duration of 200 ms if the power supply drops below
2.93 V. This reset pulse ensures that the board always starts in a defined condition. The RESET pin on the I/O connector reflects the status of the RESET line. It
is a bidirectional pin for resetting external peripheral components or for resetting
the eZ80190 with a low-impedance output (e.g. a 100-Ohm pushbutton).
Serial Interface Ports
The processor contains two 16550-style UARTs with programmable baud rate
generators. When the eZ80190 Module is plugged in to the eZ80® Development
Platform, UART0 is connected to a console connector and UART1 is connected to
a modem connector. There are no RS232-level shifters on the eZ80190.
Note: Do not connect an RS-232 interface without level shifters.
PS019101-1003
PRELIMINARY
Reset Generator
eZ801905050MOD
eZ80190 Module Product Specification
17
Physical Dimensions
The footprint of the eZ80190 Module PCB is 63.5 mm x 78.7 mm. With an RJ-45
Ethernet connector, the overall height is 25 mm. See Figure 4.
78.7 mm
63.5 mm
63.5 mm
Figure 4. Physical Dimensions of the eZ80190 Module
PS019101-1003
PRELIMINARY
Serial Interface Ports
eZ801905050MOD
eZ80190 Module Product Specification
18
Figure 5 illustrates the top layer silkscreen of the eZ80190 Module.
Figure 5. eZ80190 Module—Top Layer
PS019101-1003
PRELIMINARY
Serial Interface Ports
eZ801905050MOD
eZ80190 Module Product Specification
19
Figure 6 illustrates the bottom layer silkscreen of the eZ80190 Module.
Figure 6. eZ80190 Module—Bottom Layer
ESD/EMI Protection
Caution: The eZ80190 is a component that is intended to be part of a system
design for end-user devices. Therefore, the user must exercise caution
to use ESD protection on the I/O pins.
The EMAC can be additionally protected by placing an ESD protection array on
the eZ80190 at position U9. Either use ESDA25B1 from ST Microelectronics or
LCDA15C-6 from Semtech. A mounting hole on the board can be used for
grounding the shield of the Ethernet RJ45 jack to prevent surge or ESD currents
from flowing through the digital circuitry.
The RJ45 Ethernet Connector on the eZ80190 contains a transformer and common mode chokes for EMI suppression.
Caution: CMOS I/Os are ESD-sensitive and must be handled with care.
Handling of the module should be performed in ESD-safe
environments (for example with a wrist-wrap attached). When
PS019101-1003
PRELIMINARY
ESD/EMI Protection
eZ801905050MOD
eZ80190 Module Product Specification
20
developing applications, the user must provide for proper ESD
protection on external, user-accessible I/Os (e.g. suppressor arrays for
the I/Os).
The components are mounted on a multilayer PCB to provide a stable ground
plane for onboard components. The module features several GND pins next to
pins with higher switching frequency for short ground returns. If unused, the clock
output can be separated from the module header by removing a series resistor on
the module. Removing the series resistor further reduces electromagnetic emissions.
Absolute Maximum Ratings
Stresses greater than those listed in Table 6 can cause permanent damage to the
device. These ratings are stress ratings only. Operation of the device at any condition outside those indicated in the operational sections of these specifications is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. For improved reliability, unused inputs should be
tied to one of the supply voltages (VDD or VSS).
Table 6. Absolute Maximum Ratings
Parameter
Min
Max
Units
0
+70
ºC
Storage temperature
–45
+85
ºC
Operating Humidity (RH @ 50ºC)
25%
90%
—
3.3
Standard operating temperature
Operating Voltage (±5%)
V
Power Supply
The eZ80™ Webserver-i E-NET Module requires a regulated external 3.3 VDC/
0.5A power supply. You may use a Low Dropout Regulator (LDO) to get 3.3 V from
5 V or use the following switcher circuit to generate 3.3 V from unregulated 10-28V
power supply.
Power connections follow these conventional descriptions:
PS019101-1003
Connection
Circuit
Device
Power
VCC
VDD
Ground
GND
VSS
PRELIMINARY
Power Supply
eZ801905050MOD
eZ80190 Module Product Specification
21
Switcher 10–28V → 3.3V
To Module
U1
LM2575S-ADJ
10–28V
1
V IN
VIN
G
N
D
C2
C1
1000uF
100n
3
FB
OVOUT
N
/
O
F
F
4
2
VDD
3.3V
L1
330uH/1A
R1
5k6
1%
D1
1A/30V
R2
3k3
1%
5
GND
C3
470uF/6.3V
Low ESR
GND
LDO 5V → 3.3V
4-6V
U1
LM3940
VCC
VI
G
N
D
VDD
3.3V
VO
C3
Low ESR
470uF/6.3V
C1
100n
GND
GND
Figure 7. Power Supply Examples
PS019101-1003
PRELIMINARY
Power Supply
eZ801905050MOD
eZ80190 Module Product Specification
22
Document Number Description
The Document Control Number that appears in the footer of each page of this
document contains unique identifying attributes, as indicated in the following
table:
PS
Product Specification
0191
Unique Document Number
01
Revision Number
1003
Month and Year Published
Change Log
Rev
Date
Purpose
By
01
October 2003
Original issue
M. Staubermann
PS019101-1003
PRELIMINARY
Document Number Description
eZ801905050MOD
eZ80190 Module Product Specification
Schematic Diagrams
23
Figures 8 through 15 present the schematics of the eZ80190 Module.
X1
R13
-SLEEP
PA[0..7]
CLK_OUT
-MREQ
-WR
-RD
-CS0
-CS1
-CS2
-CS3
-RD
-CS[0..3]
-CS0 --> FLASH
-CS1 --> RAM
-CS2 --> ext. IO
-CS3 --> ETH
-MREQ
D[0..7]
A[0..23]
A8
A9
A10
A11
A12
A13
-BUSREQ
-BUSACK
-MREQ
don't
stuff
R30
0R
0603
PA[0..7]
MREQ
WR
RD
CS0
CS1
CS2
CS3
VDD
VSS
A0
A1
A2
A3
A4
A5
A6
A7
VDD
VSS
A8
A9
A10
A11
A12
A13
U1
eZ80190
TQFP100
PC[0..7]
TEST
PC7/RI1
PC6/DCD1
PC5/DSR1
PC4/DTR1
PC3/SS1/CTS1
PC2/SCK1/RTS1
PC1/SDA1/MOSI1/RxD1
PC0/SCL1/MISO1/TxD1
VSS
VDD
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
ZDA
ZCL
RESET
IORQ
INSTRD
HALT
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
ZDA
ZCL
-RESET
-IOREQ
-INSTRD
-HALT
PB[0..7]
PC[0..7]
PD[0..7]
ZDA
ZCL
-RESET
-IOREQ
R4
-NMI
R31
0R
0603
-INSTRD
-HALT
1k
0603
PB[0..7]
PC[0..7]
PD[0..7]
ZDA
ZCL
PB[0..7]
CLK_OUT
PC1
CLK_OUT
PA[0..7]
-NMI
-RESET
-IOREQ
-INSTRD
-HALT
-NMI
D0
D1
D2
D3
D4
D5
D6
D7
-BUSACK
50.000MHz, 3.3V
SG-710
A14
A15
VDD
VSS
A16
A17
A18
A19
A20
A21
A22
A23
VDD
VSS
D0
D1
D2
D3
D4
D5
D6
D7
VDD
VSS
NMI
-BUSREQ
PD[0..7]
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
A[0..23]
A0
A1
A2
A3
A4
A5
A6
A7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PC0
D[0..7]
1
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
-WR
A14
A15
-CS[0..3]
OE
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PD6
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
-BUSACK
0R R14
0603
-ACTIVE
OUT
4k7
0603
don't
stuff
-RD
3
PD7
0R R15
0603
-WR
XIN
A16
A17
A18
A19
A20
A21
A22
A23
-ACTIVE
PD4
-BUSREQ
-SLEEP
=
ETHIRQ
PHI
BUSREQ
VSS
VDD
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
BUSACK
EXTAL
XTAL
VSS
VDD
PD7/RI0
PD6/DCD0
PD5/DSR0
PD4/DTR0
PD3/SS0/CTS0
PD2/SCK0/RTS0
PD1/SDA0/MOSI0/RxD0
PD0/SCL0/MISO0/TxD0
ETHIRQ
A[0..23]
D[0..7]
IICSDA
IICSCL
IICSDA
IICSCL
PA7
0R R32
0603
0R R33
0603
PA6
C18
1nF
0603
C19
1nF
0603
C20
1nF
0603
place caps close
to pins 97, 8, 38, 48
Figure 8. eZ80190 Module Schematic Diagram, #1 of 9—CPU
PS019101-1003
PRELIMINARY
Schematic Diagrams
eZ801905050MOD
eZ80190 Module Product Specification
24
U2
D[0..7]
A[0..23]
-CS1
-RD
-WR
D[0..7]
A21/ A22/ A23
not us ed her e
A[0..23]
-CS1
-RD
-WR
=
A18
A0
A1
A2
A3
-CSRAM
D0
D1
-CSRAM
D2
D3
-WR
A12
A9
A6
A4
A17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
A0
A1
A2
A3
A4
CE
I/O0
I/O1
VDD
VSS
I/O2
I/O3
WE
A5
A6
A7
A8
A9
N.C.
A18
A17
A16
A15
OE
I/O7
I/O6
VSS
VDD
I/O5
I/O4
A14
A13
A12
A11
A10
N.C.
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
A20
A16
A15
A14
A13
-RD
D7
D6
D5
D4
A11
A8
A10
A7
A5
A19
D7
D6
D5
D4
D3
D2
D1
D0
10
9
8
7
6
5
4
3
2
RN1
1
9 x 4k7
SIP10
512kx8 fast SRAM
SOJ36.400
AS7C34096-10JC
V3.3
VDD
C1
100nF
0603
VSS
GND
Figure 9. eZ80190 Module Schematic Diagram, #2 of 9—36-Pin SRAM Device
PS019101-1003
PRELIMINARY
Schematic Diagrams
eZ801905050MOD
eZ80190 Module Product Specification
25
21
20
19
18
17
16
15
14
8
7
36
6
5
4
3
2
1
40
13
37
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
Pi n37=N. C.
f or 4Mbi t Fl as hes
D[0..7]
A[0..23]
-RD
-WR
-CS0
-DIS_FLASH
-RESET
VDD
VDD
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
I nt el - Ty pe
U4
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
25
26
27
28
32
33
34
35
DFLASH0
DFLASH1
DFLASH2
DFLASH3
DFLASH4
DFLASH5
DFLASH6
DFLASH7
CE
OE
WE
RP
WP
22
24
9
10
12
-CSFLASH
-RD
-WR
-RESFLASH
-WP
11
VPP
29
38
A21
A20
VPP
VSS
VSS
C2
100nF
0603
U3
23
39
A[0..23]
30
31
D[0..7]
N.C.
N.C.
2
5
6
9
10
15
16
19
20
23
1B1
1B2
1B3
1B4
1B5
2B1
2B2
2B3
2B4
2B5
1A1
1A2
1A3
1A4
1A5
2A1
2A2
2A3
2A4
2A5
3
4
7
8
11
14
17
18
21
22
1OE
2OE
1
13
D0
D1
D2
D3
D4
D5
D6
D7
-CSFLASH
74CBTLV3384
SO24.300
R5
0R 0603
A20/ A21 us ed f or
16/ 32Mbi t - Fl as h
Flash 1Mx8 3.3V
TSOP40.20MM
MT28F008B3VG
D[0..7]
A22/ A23
not us ed her e
A[0..23]
U5A
U6A
-CS0
1
-FLASH_EN
2
-RD
3
-DIS_FLASH
1
2
-CSFLASH
-WR
R6
10k
0603
-CS0
74LCX32
TSSOP14
74LCX04
TSSOP14
V3.3
-DIS_FLASH
VDD
-RESET
R7
10k
0603
= -RESFLASH
VSS
U6B
GND
-FLASHWE
-FLASHWE
-FLASHWE
Note: Must be pulled Low
externally for programming.
3
4
-WP
74LCX04
TSSOP14
Figure 10. eZ80190 Module Schematic Diagram, #3 of 9—NOR Flash Device
PS019101-1003
PRELIMINARY
Schematic Diagrams
eZ801905050MOD
eZ80190 Module Product Specification
26
R8
device addresses:
00300h bis 0030Fh
-ETHRD
-ETHWR
SD[0..7]
SA[0..3]
ETHIRQ
-SLEEP
-ACTIVE
5682F5;5
LED5682F
4k99/1%
0603
ESD protection array
U8
TXDTXD+
R2
RXD-
-ACTIVE
=
through-hole
solder pad
place near
FAST JACK
L1
-LANLED
GND
6
5
LCDA15C-6
SO8.150
CTD
JP4
HEADER 1
SIP1
do not
stuff
RDR3
100
0603
GND
CASE
TD+
8R2
0603
RXD+
VDD
VSS
3
C3
560pF
0603
8R2
0603
SD[0..7]
-SLEEP
7 TD-
TD-
-DIS_ETH
ETHIRQ
2
4
C4
100nF
0603
V3.3
RD-
i nt . Pul l - Up
R1
SA[0..3]
8 TD+
GND
-ETHRD
-ETHWR
SD[0..7]
RD+ 1
-SLEEP
TXD+
-ETHWR
lower LED
R12
TXD-
-ETHRD
R10
100
0603
green
-LINKLED
9
TQFP100
SD0
SD1
SD2
SD3
-DIS_ETH
CS8900A-CQ3
R9
100
0603
upper LED
Y1
20.000 MHz
HC49
RXDRXD+
green
-LANLED
J1
1
2
3
4
CRD 5
6
8
s hi el d
10
-DIS_ETH
U7
-LANLED
-LINKLED
1
SA[0..3]
LD1
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
LANLED
LINKLED/HC0
XTAL2
XTAL1
AVSS
AVDD
AVSS
RES
RXDRXD+
AVDD
AVSS
TXDTXD+
AVSS
AVDD
DODO+
CICI+
DIDI+
BSTATU S/HC1
SLEEP
TEST
SD4
SD5
SD6
SD7
SA0
SA1
SA2
SA3
SD9
SD8
MEMW
MEMR
INTRQ2
INTRQ1
INTRQ0
IOCS16
MEMCS16
INTRQ3
SHBE
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
REFRESH
SA12
SA13
SA14
SA15
SA16
DVSS
DVDD
DVSS
SA17
SA18
SA19
IOR
IOW
AEN (TCK)
IOCHRDY
SD0
SD1
SD2
SD3
DVDD
DVSS
SD4
SD5
SD6
SD7
RESET
ETHIRQ
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
R11
4k7
0603
Dual-LED assembly,
right angle, grn/grn
SD10
SD11
DVSS
DVDD
SD12
SD13
SD14
SD15
CSOUT
DMACK0
DMARQ0
DMACK1
DMARQ1
DMACK2
DMARQ2
DVSS
DVDD
DVSS
CHIPSEL
EEDATAIN
EEDATAOUT (TDO)
EESK
EECS
ELCS
AVSS
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
10k
0603
RD+
C5
100nF
0603
C6
100nF
0603
plane or
big trace
CASE
HFJ11-1041(E)
HALOFASTJACK
TX+
TXRX+
RX-
<- >
<- >
<- >
<- >
1
2
3
6
CASE
ferrite
1210
do not stuff
Figure 11. eZ80190 Module Schematic Diagram, #4 of 9—Ethernet Module
PS019101-1003
PRELIMINARY
Schematic Diagrams
eZ801905050MOD
eZ80190 Module Product Specification
27
U9
D[0..7]
A[0..23]
-RD
-WR
-CS3
CLK_OUT
D[0..7]
D0
D1
D2
D3
D4
D5
D6
D7
A[0..23]
3
4
5
6
7
8
9
10
A0
A1
A2
A3
A4
A5
A6
A7
-RD
D[0..7]
-WR
-CS3
=
-ETHWR
-WR
-CSETH
13
14
11
-RD
2
1
23
-CSETH
-CSETH
22
21
20
19
18
17
16
15
B0
B1
B2
B3
B4
B5
B6
B7
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
SD[0..7]
SA[0..3]
OEAB
LEAB
CEAB
A[0..23]
CSETH_P
SA[0..3]
SD[0..7]
OEBA
LEBA
CEBA
74LCX543
TSSOP24
-ETHRD
U10
-ETHWR
CLK_OUT
A0
A1
A2
A3
SD[0..7]
2
3
4
5
6
7
8
9
D1
D2
D3
D4
D5
D6
D7
D8
11
1
LE
OE
19
18
17
16
15
14
13
12
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
SA0
SA1
SA2
SA3
-ETHRD
-ETHWR
SA[0..3]
74LCX573
TSSOP20
U5B
-RD
-CSETH1D
U6C
4
10
5
-CSETH1D
CLK_OUT
CLK
1
Q
6
74LCX74
TSSOP14
V3.3
12
11
PR
3
Q
D
R16
0R
0603
8
-ETHWR
U5C
-WR
9
U11B
Q
Q
-CSETH2D 10
9
CLK
CL
CLK_OUT
D
U11A
13
2
CL
-CSETH
-ETHRD
74LCX32
TSSOP14
don't
stuff
74LCX04
TSSOP14
6
5
CSETH_P
6
PR
5
4
8
R17
0R
0603
74LCX32
TSSOP14
V3.3
74LCX74
TSSOP14
V3.3
VDD
VSS
GND
Figure 12. eZ80190 Module Schematic Diagram, #5 of 9—Ethernet Module Logic
PS019101-1003
PRELIMINARY
Schematic Diagrams
eZ801905050MOD
eZ80190 Module Product Specification
28
power supervisor
3
V3.3
VDD
GND
RESET
1
C7
100nF
0603
U12
R 18
2k2
0603
-RESET
2
-RESET
open-drain
-RESET
C8
10nF
0603
M AX6328UR29
SO T-23-L3
alternative:
Maxim MAX6802UR29D3
real-time clock
Gold Cap
C9
0,1F
GOLDCAP_SD_V
R19
V3.3
100
0603
D1
TM M BAT 41
M IN IM ELF_AK
C 10
100nF
0603
RTC _VDD
RTC _VDD
R20
RTC _VDD
1
2
Y2
3
V+
GND
VBAT
U 13
8
VBAT
SD A
SCL
O SC I
OS CO
FT/OUT
4
32.7
68kHz
XTAL3
0R
0603
5
6
IIC SD A
II
CS CL
R21
4k7
0603
7
M 41T11M 6
SO 8.150
R 23
4k7
0603
R 22
4k7
0603
V3.3
IIC SD A
II
CS CL
C11
unpl
ace
0603
IIC SD A
II
CS CL
I2C bus address:
VD D
VSS
{D0} H /{D1} H
GND
Figure 13. eZ80190 Module Schematic Diagram, #6 of 9—Ethernet Module Peripherals
PS019101-1003
PRELIMINARY
Schematic Diagrams
eZ801905050MOD
eZ80190 Module Product Specification
29
A[0..23]
D[0..7]
-CS[0..3]
IICSDA
IICSCL
CLK_OUT
-DIS_FLASH
-FLASHWE
RTC_VDD
PB[0..7]
PC[0..7]
PD[0..7]
PA[0..7]
-DIS_ETH
-RESET
-RD
-WR
-IOREQ
-MREQ
-INSTRD
-HALT
-BUSREQ
-BUSACK
-NMI
ZDA
ZCL
A[0..23]
connector 1
connector 2
D[0..7]
JP1
-CS[0..3]
GND_EXT
A6
A10
GND_EXT
A8
A13
A15
A18
A19
A2
A11
A4
A5
-DIS_ETH
A21
A22
-CS0
-CS2
D1
D3
D5
D7
-MREQ
GND_EXT
-WR
-BUSACK
IICSDA
IICSCL
R24
CLK_OUT
33
-DIS_FLASH
EZ80CLK
0603
place near eZ80
output (PHI)
-FLASHWE
RTC_VDD
PB[0..7]
PC[0..7]
PD[0..7]
R25
10k
0603
PA[0..7]
-DIS_ETH
-RESET
-RD
-WR
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
V3.3_EXT
A0
A3
V3.3_EXT
A7
A9
A14
A16
GND_EXT
A1
A12
A20
A17
-DIS_FLASH
V3.3_EXT
A23
-CS1
D0
D2
D4
GND_EXT
D6
-IOREQ
-RD
-INSTRD
-BUSREQ
PA7
PA5
PA3
PA1
V3.3_EXT
PB7
PB5
PB3
PB1
GND_EXT
PC6
PC4
PC2
PC0
PD6
PD5
PD3
PD1
GND_EXT
ZCL
RTC_VDD
IICSCL
IICSDA
-FLASHWE
-CS3
-RESET
V3.3_EXT
-HALT
V3.3_EXT
Header 30x2
-IOREQ
-MREQ
-INSTRD
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
Header 30x2
peripheral bus
connector
R26
2k2
0603
JP2
I/O connector
PA6
PA4
PA2
PA0
GND_EXT
PB6
PB4
PB2
PB0
PC7
PC5
PC3
PC1
PD7
GND_EXT
PD4
PD2
PD0
ZDA
EZ80CLK
GND_EXT
GND_EXT
GND_EXT
NOTUSED1
GND_EXT
-NMI
NC
Pin 50 open,
to be keyed
-HALT
-BUSREQ
-BUSACK
R27
10k
0603
-NMI
R28
10k
0603
R29
10k
0603
ZDA
ZCL
NOTUSED1
( * WAI T * )
V3.3
V3.3_EXT
GND_EXT
GND
Figure 14. eZ80190 Module Schematic Diagram, #7 of 9—Headers
PS019101-1003
PRELIMINARY
Schematic Diagrams
eZ801905050MOD
eZ80190 Module Product Specification
30
common power plane
V3.3
VDD
no power supply on board
Input: VDD ( = V3.3) = 3.3V ±5%
Power: Pmax = tbd
Ptyp = tbd
Current: lmax = tbd
ltyp = tbd
C12
22uF
SMT7343
C13
22uF
SMT7343
C14
1nF
0603
C15
100nF
0603
C16
1nF
0603
GND
C17
100nF
0603
VSS
common ground plane
PCB1
eZ80190 ethernet module board
98Cxxxx-xxx
U6D
U5D
12
9
8
11
13
74LCX32
TSSOP14
74LCX04
TSSOP14
unused gates
U6E
11
10
74LCX04
TSSOP14
U6F
13
12
74LCX04
TSSOP14
Figure 15. eZ80190 Module Schematic Diagram, #8 of 9—Power Supply
PS019101-1003
PRELIMINARY
Schematic Diagrams
eZ801905050MOD
eZ80190 Module Product Specification
31
Customer Feedback Form
The eZ80190 Module Product Specification
If you experience any problems while operating this product, or if you note any inaccuracies
while reading this Product Specification, please copy and complete this form, then mail or fax it to
ZiLOG (see Return Information, below). We also welcome your suggestions!
Customer Information
Name
Country
Company
Phone
Address
Fax
City/State/Zip
Email
Product Information
Serial # or Board Fab #/Rev. #
Software Version
Document Number
Host Computer Description/Type
Return Information
ZiLOG
System Test/Customer Support
532 Race Street
San Jose, CA 95126
Phone: (408) 558-8500
Fax: (408) 558-8536
ZiLOG Customer Support
Problem Description or Suggestion
Provide a complete description of the problem or your suggestion. If you are reporting a specific
problem, include all steps leading up to the occurrence of the problem. Attach additional pages
as necessary.
_____________________________________________________________________________________________
_____________________________________________________________________________________________
_____________________________________________________________________________________________
_____________________________________________________________________________________________
_____________________________________________________________________________________________
PS019101-1003
PRELIMINARY
Customer Feedback Form