PRELIMINARY ML2712 2.4GHz RF Transceiver GENERAL DESCRIPTION FEATURES The ML2712 combined with the ML2713 form a FSK (Frequency Shift Keying) 2.4 GHz radio chipset. The ML2712 contains the RF and PLL circuits for a half duplex radio transceiver solution for IEEE802.11 and other wireless communication protocols using the 2.4 GHz ISM band. The ML2712 is controlled using a three-wire programming interface and three control lines. The transmit circuits feature an RF down converter for a transmit frequency translation loop and a Wideband Phase Detector for a directly modulated VCO transmitter. An RF down converter mixer is provided for receive. All frequency generation circuits are integrated for the RF conversion, the 1LO VCO and PLL plus a 2LO VCO and PLL for use in dual conversion radios. In addition the ML2712 contains an 8 bit D/A & Comparator that may be used together as a tracking A/D for Received Signal Strength Indication measurement (RSSI). ■ 2.4GHz RF Down Converter ■ Programmable 2.2GHz and 236MHz Frequency Synthesizers ■ External VCO tank circuits for flexibility ■ Compatibility with the OKI MSM7730 and similar baseband controllers ■ Transmit Wideband Phase Comparator for closed loop transmitter with >5MHz loop bandwidth ■ PLLs Programmable via 3 wire interface ■ 48 pin TQFP 7mm body ■ 3.0V to 5.5V operation APPLICATIONS ■ 2.4GHz Frequency Shift Key modulated radios ■ PC Card & Flashcard Wireless Transceivers ■ IEEE802.11FHSS Compatible 1 and 2Mbps Standard SIMPLIFIED BLOCK DIAGRAM R. C. Loop Filter ML2731 Bias Controller RSSI Input ML2712 Transmit Power Amplifier WB Charge Pump/WB Phase Comp + – DAC 2LO VCO 2LO Loop Filter & Tank Circuit 3 3 PLL 2 LPF Lock Detect PLL 1 x2 1LO Loop Filter & Tank Circuit 1LO VCO 32MHz Clock MUX ML2713 Tx Regulator Output DATASHEET Reference Frequency Input January, 2000 Baseband Controller (e.g., MSM7730B) PRELIMINARY ML2712 TABLE OF CONTENTS General Description .........................................................................................................................................................1 Simplified Block Diagram ................................................................................................................................................1 Features ...........................................................................................................................................................................1 Applications .....................................................................................................................................................................1 Block Diagram ................................................................................................................................................................. 3 Pin Descriptions ...............................................................................................................................................................4 Pin Configuration .............................................................................................................................................................4 Functional Description ..................................................................................................................................................... 7 Introduction ................................................................................................................................................................7 Modes of Operation .........................................................................................................................................................8 Transmit Mode .............................................................................................................................................................8 Standby Mode .............................................................................................................................................................8 Receive Mode ........................................................................................................................................................... 10 Overview of PLLs ...................................................................................................................................................... 11 Operating Mode Control ............................................................................................................................................ 12 Serial Control Bus ...................................................................................................................................................... 13 Electrical Tables ............................................................................................................................................................... 18 Electrical Characteristics .................................................................................................................................................. 18 Absolute Maximum Ratings .............................................................................................................................................. 18 Operating Conditions ....................................................................................................................................................... 18 Physical Dimensions ........................................................................................................................................................ 24 Ordering Information ........................................................................................................................................................ 24 WARRANTY Micro Linear makes no representations or warranties with respect to the accuracy, utility, or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, express or implied, by estoppel or otherwise, to any patents or other intellectual property rights is granted by this document. The circuits contained in this document are offered as possible applications only. Particular uses or applications may invalidate some of the specifications and/or product descriptions contained herein. The customer is urged to perform its own engineering review before deciding on a particular application. Micro Linear assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of Micro Linear products including liability or warranties relating to merchantability, fitness for a particular purpose, or infringement of any intellectual property right. Micro Linear products are not designed for use in medical, life saving, or life sustaining applications. © Micro Linear 2000. is a registered trademark of Micro Linear Corporation. All other trademarks are the property of their respective owners. Products described herein may be covered by one or more of the following U.S. patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; 5,652,479; 5,661,427; 5,663,874; 5,672,959; 5,689,167; 5,714,897; 5,717,798; 5,742,151; 5,747,977; 5,754,012; 5,757,174; 5,767,653; 5,777,514; 5,793,168; 5,798,635; 5,804,950; 5,808,455; 5,811,999; 5,818,207; 5,818,669; 5,825,165; 5,825,223; 5,838,723; 5.844,378; 5,844,941. Japan: 2,598,946; 2,619,299; 2,704,176; 2,821,714. Other patents are pending. 2 PRELIMINARY DATASHEET January, 2000 PRELIMINARY ML2712 BLOCK DIAGRAM VCC1 RVCC1 VCC2 VCC3 RVCC2 VCC7 VCC4 VCC8 VCC5 VCC6 11 12 15 16 21 23 27 33 34 37 41 2LO 40 2LOB RSSI 45 1 TPL RVCC3 42 T2LO 43 QP2 48 RS 38 CONTROL WB CHARGE PUMP WBCP 35 2LO VCO 46 LOE + 2 RSTH – WBLD WB PHASE COMP 4 47 TS 8 BIT SERIAL DAC 2LO CHANGE PUMP PRESCALER 14/15 8 DACEN PRESCALER CONTROL LPF 2LO PHASE/ FREQUENCY DETECTOR Tx RF MIXER 2LO 5-BIT COUNTER 2LO 4-BIT SWALLOW COUNTER 10 REF 3 LD TRFI 32 REFERENCE DIVIDER GND 31 BG 22 BAND GAP REF 7 CLK ADDRESS DECODE 6 DATA 1IF 25 1LO 6-BIT COUNTER 1LO PHASE/ FREQUENCY DETECTOR MUX 1IFB 26 1LO CHARGE PUMP 5 EN 1LO 6-BIT SWALLOW COUNTER MUX Rx RF MIXER PRESCALER 40/41 PRESCALER CONTROL 13 QP1 X2 RRFI 30 GND CONTROL LOCK DETECT 1LO VCO 29 T1LOB 20 T1LO 19 9 14 17 18 24 28 36 39 44 GND GND GND GND GND GND GND GND GND January, 2000 PRELIMINARY DATASHEET 3 PRELIMINARY ML2712 PIN CONFIGURATION VCC6 QP2 GND 2LOB RVCC3 2LO T2LO GND RSSI LOE TS RS ML2712 48-Pin TQFP (H48-7) 48 47 46 45 44 43 42 41 40 39 38 37 TPL 1 36 GND RSTH 2 35 WBCP LD 3 34 WBLD 4 33 VCC5 VCC8 EN 5 32 TRFI DATA 6 31 GND CLK 7 30 RRFI DACEN 8 29 GND GND 9 28 GND REF 10 27 VCC1 RVCC1 11 26 VCC4 1IFB 25 1IF 12 VCC7 GND RVCC2 BG T1LOB T1LO GND GND VCC2 VCC3 QP1 GND 13 14 15 16 17 18 19 20 21 22 23 24 TOP VIEW PIN DESCRIPTIONS Pin # Signal Name Power and Ground 11 VCC1 4 9 15 GND VCC2 16 VCC3 17 27 GND VCC4 28 34 GND VCC5 36 GND 37 VCC6 39 23 GND VCC7 I/O Type Description Supply Voltage for CMOS Logic. A bypass capacitor connected with minimum trace lengths from VCC1 to PCB ground is recommended Ground for CMOS Logic Supply voltage for Digital/Analog Converter and Comparator. A bypass capacitor connected with minimum trace lengths from VCC2 to PCB ground is recommended Supply Voltage for 1LO Prescaler and Phase Detector. A bypass capacitor connected with minimum trace lengths from VCC3 to PCB ground is recommended Ground for 1LO Prescaler and Phase Detector Supply Voltage for RF Amplifier. A bypass capacitor connected with minimum trace lengths from VCC4 to PCB ground is recommended Ground for RF Low Noise Amplifier Supply Voltage for Wideband Transmit PLL Charge Pump. A bypass capacitor connected with minimum trace lengths from VCC5 to PCB ground is recommended Ground for Wideband Transmit PLL Charge Pump. Minimizing the lead trace length from this GND to PCB ground to reduce inductance and resistance is recommended Supply Voltage for 2LO Charge Pump. A bypass capacitor connected with minimum trace lengths from VCC6 to PCB ground is recommended Ground for 2LO Charge Pump Power Supply for 2LO Prescaler and Phase Detector. A bypass capacitor connected with minimum trace lengths from VCC7 to PCB ground is recommended PRELIMINARY DATASHEET January, 2000 PRELIMINARY ML2712 PIN DESCRIPTIONS (continued) Pin # Signal Name 24 33 I/O Type GND VCC8 Ground for 2LO Prescaler and Phase Detector Supply Voltage for Mixers, 1LO Frequency Doubler, and Transmit PLL. A bypass capacitor connected with minimum trace lengths from VCC8 to PCB ground is recommended Ground for Mixers, 1LO Frequency Doubler, and Transmit PLL 29 GND Regulated Power and Ground 12 RVCC1 14 21 GND RVCC2 18 42 GND RVCC3 44 GND Transmitter Section 32 TRFI Description Regulated Bypass Output Supply Voltage for 1LO PLL Charge Pump. A bypass capacitor connected with minimum trace lengths from RVCC1 to PCB ground is recommended Ground for 1LO PLL Charge Pump Regulated Bypass Output Supply for 1LO Voltage Controlled Oscillator. A bypass capacitor connected with minimum trace lengths from RVCC2 to PCB ground is recommended Ground for 1LO Voltage Controlled Oscillator Regulated Bypass Output Supply for 2LO Voltage Controlled Oscillator. A bypass capacitor connected with minimum trace lengths from RVCC3 to PCB ground is recommended Ground for 2LO Voltage Controlled Oscillator I Transmit RF Input signal. This signal, input to the Transmit Down Converter Mixer should be AC coupled and matched to the nominal 50Winput impedance Transmit Signal Ground. Minimizing the lead trace length from this GND to PCB ground to reduce inductance and resistance is recommended Wideband PLL Charge Pump output 31 GND 35 WBCP O (Analog) 10 REF I Reference frequency input to Phase Locked Loops. Requires square wave input 3 LD O (CMOS) 4 41 WBLD 2LO O (CMOS) O 40 2LOB O 25 1IF I/O Lock Detect output. Low output indicates this pin is in open drain. Two Phase Locked Loops are frequency locked and requires 10kW pull-up Wideband PLL Lock Detect open drain output and requires 10kW pull-up 2LO output. Together with 2LOB provides a balanced 2LO output port for input to Down Converter Mixer on ML2713. Requires 5KW external pull-up resistor to VCC3 if not connected to ML2713 In Standby Mode, 2LOB and 2LO provide a calibration tone used to calibrate the ML2713 IF Transceiver 2LOI output. Together with 2LO provide a balanced 2LO output port for input to Down Converter Mixer on ML2713 Requires 5KW external pull-up resistor to VCC1 if not connected to ML2713 In Standby Mode, 2LO and 2LOB provide a calibration tone used to calibrate the ML2713 IF Transceiver IF Input/Output. In RECEIVE Mode, functions with 1IFB to present a balanced first IF output port with 340W output impedance. Connection must be AC coupled. It is recommended that the signal trace connected to this pin be isolated from other signal or digital control lines to maintain receiver sensitivity In TRANSMIT Mode, functions with 1IFB to present a balanced first IF input port with 340W input impedance. Connection must be AC coupled. It is recommended that the signal trace connected to this pin be isolated from other signal or digital control lines to maintain receiver sensitivity January, 2000 PRELIMINARY DATASHEET 5 PRELIMINARY ML2712 PIN DESCRIPTIONS (continued) Pin # Signal Name 26 I/O Type 1IFB Receiver Section 30 RRFI 6 I/O IF Input/Output Inverted. In RECEIVE Mode, functions with 1IF to present a balanced first IF output port with 340W output impedance. Connection must be AC coupled. It is recommended that the signal trace connected to this pin be isolated from other signal or digital control lines to maintain receiver sensitivity In TRANSMIT Mode, functions with 1IF to present a balanced first IF input port with 340W input impedance. Connection must be AC coupled. It is recommended that the signal trace connected to this pin be isolated from other signal or digital control lines to maintain receiver sensitivity I Receive RF Input signal. It is recommended that the nominal input impedance of 20W on this pin be matched and be AC coupled Received Signal Strength Indicator input Digital to Analog Converter high output voltage defined by contents of Control Register E RSSI Threshold output. High output indicates RSSI input is greater than TPL. Digital to Analog Converter output voltage First Local Oscillator Tank circuit. T1LO and T1LOB provide a balanced pair for connection to an external parallel inductor/capacitor tank circuit that determines the frequency of oscillation Inverted First Local Oscillator Tank circuit. T1LOTB and T1LO provide a balanced pair for connection to an external parallel inductor/capacitor tank circuit that determines the frequency of oscillation Charge Pump output of 1LO Phase Locked Loop. Analog output switches between VCC2 and ground Charge Pump output of 2LO Phase Locked Loop charge pump output. Analog output switches between VCC6 and ground as controlled by the phase detector in the 2LO PLL Second Local Oscillator Tank circuit. T2LO and GND (pin 44) provide an unbalanced pair for a connection to an external parallel inductor/capacitor tank circuit that determines the frequency of oscillation Bandgap voltage output. Connection available for bypass capacitor recommended for noise decoupling from Bandgap voltage reference. Recommended capacitance value is 10nF connected to ground 45 1 RSSI TPL I (Analog) O 2 RSTH O (CMOS) 19 T1LO (Tank Port) 20 T1LOB (Tank Port) 13 QP1 O 38 QP2 O (Analog) 43 T2LO O (Analog) 22 BG I/O (Analog) Mode Control 46 LOE 47 TS 48 RS Serial Interface 5 EN 8 DACEN 6 DATA 7 CLK Description I (CMOS) I (CMOS) I (CMOS) Local Oscillator Enable Transmit Switch Receive Switch I I I I Enable serial data D/A Converter Enable Serial Data Clock input for serial data (CMOS) (CMOS) (CMOS) (CMOS) PRELIMINARY DATASHEET January, 2000 PRELIMINARY ML2712 FUNCTIONAL DESCRIPTION INTRODUCTION The ML2712 2.4GHZ RF Transceiver contains all the RF circuitry, including the phase lock loop (PLL), and the active VCO circuits, for a half duplex transceiver. When combined with the ML2713 it enables the design of a high performance 2.4GHz half duplex radio with a fast switching time between transmit and receive modes. This is ideal for applications such as frequency hopping radio for the IEEE 802.11 FH standard. The ML2712 Transceiver has four modes of operation; 1) Standby 2) Transmit 3) Receive and 4) Sleep. The operating modes of the ML2712 can be programmed through a parallel control interface or through a serial interface. Two serial control interfaces are utilized for programming the PLLs and on chip A/D. In STANDBY mode all the PLL and VCO circuits are enabled while all the transmitter and receiver circuits are disabled. The use of STANDBY mode is recommended when the PLLs are locking, after the PLL frequencies have been reprogrammed, or after the IC has been transferred out of SLEEP mode. The transmit circuits include a 2.4GHz RF down converter for transmit frequency translation and a Wideband Phase Detector that implements a directly modulated VCO transmitter radio architecture. The receive section of the ML2712 inlcudes a 2.4GHz RF mixer that down converts the received RF frequency to the first IF frequency; nominally 260MHz. All required frequency generation circuits are integrated on-chip for the RF conversion including the 1LO VCO and the PLL and 1LO frequency doubler. Additionally, a second VCO and PLL provide a 2LO output useable in IF circuits in a dual conversion radio. An 8 bit D/A & Comparator for an RSSI tracking A/D are also integrated on-chip. The two local oscillator signals generated in the ML2712 are the 1LO with at a typical frequency in the region of 2.2GHz and the 2LO, with a typical frequency of 236MHz. Both signals are phase locked by the independently programmable PLLs to a common external reference frequency. External tank circuits are required for the 1LO and 2LO VCOs to determine the operating frequency ranges. The 1LO signal, generated by doubling the frequency of the 1LO VCO, is used by both the transmit and receive mixer circuits to down convert the 2.4GHz RF signals. The half-frequency 1LO VCO eases tank circuit design and minimizes the VCO pulling when the the radio switches between transmit and receive modes. The differential output from the 2LO VCO is provided for use in radio IF circuits such as the ML2713. A lock detect output indicates when the PLLs are January, 2000 frequency locked. Programming of the PLL frequency is performed via a three wire serial interface. The ML2712 implements a directly modulated VCO transmitter architecture. The elements of this architecture include a Power Amplifier, a transmitter VCO, a transmitter reference generation circuit and a 1IF Wideband PLL which locks the Transmitter VCO to this transmit reference signal. The ML2712 does not integrate the PA but does provide the Wideband PLL and an RF down-convert mixer, enabling the transmit reference signal to be generated at a lower frequency. In TRANSMIT mode the 2.2GHz (nominal) 1LO signal is used to down-convert the 2.4GHz external transmit VCO RF signal. The down converted signal is then phase locked by the on chip wideband phase detector to an externally modulated signal (Transmit reference IF) and output to pins 1IFB and 1IF. The output of the Wideband phase detector controls the transmit VCO frequency (Tx VCO external to IC) via an external loop filter. For a typical application, e.g., IEEE802.11 the symbol rate is 1Msymbol/sec. The lock up time is less than 2msec. enabling a radio designed with the ML2712 to switch between transmit and receive modes in less than 2msec. The ML2712 receiver circuits perform the RF down conversion. A typical receiver design would include the ML2712, an external LNA and RF filter, an IF filter and the ML2713 IF Transceiver. In RECEIVE mode, the ML2712 uses the 1LO signal to down convert the received 2.4 GHz band signal to a nominal 260 MHz IF. The received IF signal is output on 1IF and 1IFO pins. By multiplexing both the transmit and receive signals on one set of pins, only a single Surface Acoustic Wave (SAW) IF channel filter is required in the radio design. A SAW filter with a nominal Gaussian impulse response can be used to provide modulation filtering of the transmit reference IF signal. When in receive mode the A/D and Comparator provide the analog circuits for a tracking A/D converter, intended for RSSI digitization or clear channel assessment for "listen before talk" radios. In SLEEP mode all circuits, except for the central interface and programming registers, are powered down to minimize power consumption. PRELIMINARY DATASHEET 7 PRELIMINARY ML2712 MODES OF OPERATION Control Interface RSSI STANDBY MODE In STANDBY mode all the PLL and VCO circuits are enabled while all the transmitter and receiver circuits are disabled. (see Figigure 1) The use of STANDBY mode is recommended when the PLLs are locking, after the PLL frequencies have been reprogrammed, or after the IC has been transferred out of SLEEP mode. The VCO and PLL circuits are enabled and reach a locked state in 150 usec indicated by an active Lock Detect (LD) signal.The frequency divide ratio settings defined by Control Word C and D (see Table 4 ) define the frequencies of the 1LO PLL and 2LO PLL. Tx VCO Tuning Voltage WB Charge Pump The ML2712 uses a directly modulated VCO running at the transmitter frequency to generate the transmited signal. The VCO is then free of unwanted spurious signals and has the advantage of requiring no bandpass filtering for the transmitter signal prior to or after the Power Amplifier. The transmitter VCO is phase locked to the center frequency with the transmitter modulation applied. The modulated signal is applied directly to the VCO inside the loop bandwidth of a phase locked loop. To allow modulation rates in excess of 1Mbps requires a very wideband phase detector, capable of operating with loop bandwidths in excess of 5MHz. In this circuit the noise floor is set by the transmit VCO rather than by upconvert mixers. The circuits active in TRANSMIT Mode are shown in Figure 2. WB Phase Comp 2LO Output To IF Transceiver 2LO VCO The ML2712 transmitter architecture is shown Figure 3. A tuning voltage applied to the transmit VCO, operating at the final transmission frequency, ensures the correct center frequency before modulation is applied. This closed loop system, uses a PLL with the Transmit VCO phase locked to a modulated reference signal (SMOD). The modulated reference signal is generated at 260MHz. The signal from the Transmit VCO is down converted with the 1LO signal, then filtered through a bandpass filter. The output of the filter is fed to the very high-speed phase/ frequency detector Wideband PLL. This compares the down-converted transmit signal with the modulated reference signal SMOD. Any frequency or phase error between SMOD and the down-converted signal is corrected by changing the tuning voltage of the transmit VCO. The down-conversion with the F1LO translates the reference signal SMOD to the final transmitter frequency. 8 PRELIMINARY DATASHEET 2LO Loop Filter & Tank Circuit PLL 2 LPF Lock Detect Lock Detect Ref Frequency Input Rx RF Input PLL 1 Rx RF Input 1LO Loop Filter & Tank Circuit 1LO VCO 1IF Input Output MUX ML2712 Active Disabled Figure 1. Standby Mode Active Circuits Control Interface Tx VCO Tuning Voltage RSSI WB Charge Pump RSSI A/D Comparator Output + Control DAC WB Phase Comp – 2LO Output To IF Transceiver 2LO VCO 2LO Loop Filter & Tank Circuit PLL 2 LPF DIRECTLY MODULATED TRANSMIT VCO The transmitter is designed to enable a significant amount of power to be generated at the required frequency using a VCO, and is a technique for generating low noise, phase/frequency modulated transmitters without the need for bandpass filtering. – DAC x2 TRANSMIT MODE RSSI A/D Comparator Output + Control Lock Detect Lock Detect Ref Frequency Input Tx RF Input PLL 1 1LO Loop Filter & Tank Circuit x2 Rx RF Input 1LO VCO 1IF Input/ Output MUX ML2712 Active Disabled Figure 2. Transmit Mode Active Circuits TRANSMIT SIGNAL (SMOD + F1LO) RF DOWN CONVERTER LOW PASS FILTER FREQUENCY = F1LO ERROR CORRECTION LOOP FILTER SMOD + ERROR SIGNAL PLL SMOD = CARRIER FREQUENCY + MODULATION Figure 3. Directly Modulated VCO Transmitter January, 2000 SMOD PRELIMINARY ML2712 MODES OF OPERATION (CONTINUED) Any modulation on SMOD is duplicated at the final frequency, provided is it inside the control loop bandwidth. The spectrum of SMOD and the final output frequency are shown in Figure 4. SMOD TRANSMIT SIGNAL PSD produce a 260MHz (nominal) signal. This signal is fed via a low pass filter to the Wideband Phase Comparator where is it compared to the Transmit IF reference signal, supplied by the ML2713. The Wideband Phase Comparator output controls the transmit VCO via an external loop filter. The bandwidth of the Wideband Phase Comparator is high enough to enable a relatively low tolerance Transmit VCO to be used. F1LO 1IF The Transmit RF input is a single ended design with a nominal 50 ohms input impedance. The Transmit RF downconverter and Wideband PLL are only enabled in TRANSMIT Mode. 1IF FREQUENCY Figure 4. Simplified Spectrum of Directly Modulated VCO Transmitter The PLL loop bandwidth is at least four times that of the modulation rate. Meeting the IEEE802.11 FHSS specification for 1Msymbol/sec requires a PLL control loop bandwidth greater than 4MHz. To achieve the Wideband PLL dynamics and the RF channel spacing requirements, the Transmit VCO is down converted with the 1LO signal (at Frequency F1LO). The RF channel spacing can be achieved by stepping the 1LO VCO. This allows the same VCOs and PLLs to be used in both Transmit and Receive Modes. For typical WLAN operation the receive frequency and transmit frequency are the same (between frequency hops). Therefore the 1LO (and 2LO) frequencies do not require re-tuning when switching from transmit to receive. As a result the transmit to receive turnround time is very rapid. It is determined by the power on, settling, and lock up times of the Wideband PLL. For 802.11 FH systems the requirement is less than 2msec. TRANSMITTER PLL The transmitter wideband PLL is shown in Figure 5. An external VCO provides a nominal 2.45GHz signal which is coupled to the Transmit RF mixer using a directional coupler or similar external circuit. The transmiter RF mixer is used to down-convert the transmiter VCO signal using the frequency doubled 1LO VCO to VCO AND LOOP FILTER TO TX POWER AMPLIFIER SAW IF TX RF MIXER DIGITALLY GENERATED MODULATED TONE COUPLER RX 1LO VCO AND PLL Design of the ML2712 enables the large pull-in frequency in the Wideband PLL. When TS (Pin 47)is asserted the Wideband charge pump output is first clamped to midrail. A PFD detector is then used to ensure frequency lock. Finally the output switches to an XOR detector for accurate phase tracking. After TS is asserted WBCP is clamped to a nominal voltage of mid rail of VQWB (the charge pump supply voltage) for 0.25msec for 16MHz and 32MHz at the reference input, or 0.2msec for 20MHz or 40MHz. This pulls the VCO to mid range. When the clamp is disabled a phase frequency detector (PFD) pulls the VCO to frequency lock for 1msec with 16 MHz and 32MHz reference input, or 0.8msec with 20MHz or 40MHz reference input. This rapidly pulls the VCO to frequency lock. If the Wideband bit (Control Word B b11) is set low, the PFD is then disabled and an XOR phase detector is used until the TS signal is de-asserted. A factor of four difference between the PFD and XOR charge pump currents keeps KD, the phase detector gain, constant. The PFD charge pump current is nominally 2mA and the XOR charge pump current is nominally 0.25mA. ANTI ALIAS FILTER TANK A lock detect output from the Wideband PLL indicates Frequency Lock. An indication of the transmitter not locked is required by some regulatory authorities. TANK 2LO VCO AND PLL The Wideband PLL is designed to ensure the Transmit VCO is within the pull-in range of the Wideband PLL (so it will lock when transmitting), to achieve required lock up time, and to set the loop bandwidth. The Wideband PLL loop bandwidth requirement is 4 times the symbol rate at a minimum. The ML2712 is capable of loop bandwidth greater than 5MHz. Since the bandwidth of the Wideband PLL can be >4MHz, the lock up time for 802.11 applications is typically less than 2msec. The maximum frequency pull-in range for the transmit VCO is 500MHz to ensure that the down-converted signal passes through the low pass filter. ML2712 ML2713 Figure 5. Wideband Phase Locked January, 2000 PRELIMINARY DATASHEET 9 PRELIMINARY ML2712 MODES OF OPERATION (CONTINUED) RECEIVE MODE 1LO VCO The circuits active in RECEIVE Mode are shown in Figure 6. All the transmitter circuits are normally disabled Control in this mode. RSSI Interface The 1LO VCO operates at approximately 1.1GHz, and is doubled to a final frequency of 2.2GHz. The 1GHZ VCO signal is connected to the 1LO PLL circuits. The VCO requires an external differential tank circuit design to reduce the effects of frequency pulling due to signal coupling. The tank circuit is tuned by the charge pump output QP1(Pin 13) using a passive external loop filter. WB Charge Pump RSSI A/D Comparator Output + Control DAC WB Phase Comp – 2LO Output To IF Transceiver 2LO VCO 2LO Loop Filter & Tank Circuit PLL 2 LPF Lock Detect Lock Detect Ref Frequency Input The active circuitry for the 1LO VCO is a differential cross-coupled pair providing a negative resistance across the tank circuit to maintain oscillation. The tank circuit must provide a DC path to RVCC2 (Pin 21). The layout of this circuit must be kept symmetric to minimize interference or coupling from other circuits in the radio. PLL 1 1LO Loop Filter & Tank Circuit x2 Rx RF Input 1IF Input/ Output MUX ML2712 Active 2LO VCO 1LO VCO Disabled Figure 6. Receive Mode Active Circuits RECEIVE RF DOWN-CONVERTER The Receive RF input amplifier converts the single ended RF input to a differential signal which is then fed to a mixer. The amplifier and mixer combination down-converts the received RF signal to the receiver 1LO IF (1IF), which is optimized for 260MHz. The output of the down-converter is differential with 340W of output impedance suitable for low loss matching to an external SAW IF filter. The 1IF output ports are bidirectional and are multiplexed with the transmit reference IF input. PLL & VCO CIRCUITS Two independently programmable PLL circuits control the 1LO and 2LO VCO frequencies. These are programmed via the Serial Control Bus (DATA, CLK, and ENABLE). Program words are clocked into divider or control circuits when ENABLE is asserted. The programming is operational whether the ML2712 is in SLEEP, STANDBY, RECEIVE or TRANSMIT Mode. The 2LO VCO requires an external tank circuit and loop filter. The 2LO VCO is phase locked to provide a fixed frequency, nominally 236MHz. The differential pair 2LO (Pin41) and 2LOB (Pin 40) providedrive to the ML2713. The 2LO differential outputs are from the collectors of a differential pair that require a pullup to a nominal 2.3V, normally provided by the ML2713. A calibration tone added to the 2LO output in STANDBY Mode is intended for aligning filters and discriminators in the IF circuits of the ML2713. The calibration tone is an 8MHz square wave with a 16MHz or 32MHz reference input, or a 10MHz square wave with af 20MHz or 40MHz reference input. The 2LO VCO is a cross-coupled pair, with one base connected to RVCC3 (Pin 42) (2LO supply voltage). The other base is connected to an external tank circuit through T2LO (Pin 43). This design presents a negative impedance across the tank circuit. Since a dominant oscillation, due to bond wire inductance and parasitic capacitance on the PCB, can lead to high frequency oscillation (of the order of 1GHz), the circuit must be carefully laid out. The 2LO tank circuit must provide a DC path from T2LO to RVCC3 (Pin 42). The reference signal, REF (Pin 10) typically from an external crystal oscillator, is fed to a programmable reference divider with programmable division ratios of 40, 32, 20 and 16. The reference divider output is fed to both the 2LO and the 1LO phase/frequency detectors. The polarity of the charge pump output current pulse is programmable to give a positive or negative frequency/ voltage control. The value of the current pulses is programmable via the Serial Control Bus. (See Table 7 and 10) 10 PRELIMINARY DATASHEET January, 2000 PRELIMINARY ML2712 MODES OF OPERATION (CONTINUED) OVERVIEW OF PLLS Control words programmed via the Serial Control Bus set the ML2712 PLL reference frequency divider,and the 2LO PLL and 1LO PLL signal dividers division ratios. For illustration a simple PLL is shown in Figure 7. TUNING VOLTAGE CONTROL VCO RF OUT DIVIDE PLL DIVIDER BY P LOOP FILTER f = (N ´ ND + NS) ´ (fR/M). Note that since both PLL signal divider and reference divider are subject to an extra divide by two stage, they may be neglected in the equations. However, it is important to note that the comparison frequency in MHz in both the 1LO and the 2LO PLL is given by fC = fR/2M. DAC AND RSSI COMPARATOR PHASE DETECTOR REFERENCE DIVIDER φ I The output of the signal divider is compared with the 500 kHz comparison frequency from the reference divider in the phase detector. In the PLL (Fig. 8) the tuning voltage to the VCO is adjusted until phase locking occurs. At this point the VCO frequency in MHz will be given by the equation: DIVIDE BY M CRYSTAL OSCILLATOR REFERENCE CHARGE PUMP Figure 7. Simple PLL The DAC can be used to generate a voltage output to control the transmit power in an external power amplifier (PA). The DAC and Comparator can also be used to form an RSSI threshold circuit or an RSSI tracking A/D in conjunction with external baseband circuits. The DAC is programmed via the Serial Control Bus using either the DACEN or the EN control line. The DAC may be programmed at serial clock rates up to 16MHz. SLEEP MODE The simplified signal divide by P ( Figure 7) uses a dual modulus (or swallow pulse) prescaler system. Figure 8 shows a dual modulus signal divider. This type of PLL is able to divide by two integers, N and N+1. ND & NS, are clocked in parallel by pulses from the prescaler, which is initially set to N+1. The ND & NS registers are programmed via the Serial Control Bus. The signal divider ratio achieved by this system is given by the equation: In SLEEP Mode only the control circuits are active. These circuits are static CMOS and consume minimal current when there is no interface activity. RSD = N ´ ND + NS. ND must be greater than NS. PRESCALER FROM VCO CLK N/N+1 IF NS≠0 THEN N+1 ELSE N NS COUNTER ND COUNTER NS COUNTER MODULUS ND COUNTER MODULUS TO PHASE DETECTOR Figure 8. Dual Modulus Signal Divider January, 2000 PRELIMINARY DATASHEET 11 PRELIMINARY ML2712 CONTROL INTERFACES OPERATING MODE CONTROL A parallel control interface dynamically controls the four different Modes of operation. The control lines TS (Pin 47), RS (Pin 48) and LOE (Pin 46) enable the PLLs, VCOs, transmitter and receiver circuits. The relationship between this control interface, the Modes of operation and the functioning of the circuits are described in Table 1. The function of this control interface can be duplicated via the Serial Control Bus, and the circuits enabled in STANDBY, RECEIVE and TRANSMIT can be programmed via the Serial Control Bus. RS High TS High LOE High Mode IC Status SLEEP All radio circuits are off. Static CMOS control circuits are active, consuming minimal current but permitting the register settings to be changed via the baseband controller IC. Registers store power-up default or previously programmed values on serial control lines. The baseband IC may configure the radio, while the radio is neither transmitting nor receiving data, but the ML2712 will maintain the last programmed values. Note that in SLEEP Mode the operating Mode control may be overridden by the Serial Control Bus if parallel control interface is not required. High High Low STANDBY Only the VCO and PLL circuits are enabled in this mode and will be locked within 150msec. This will be flagged by an LD (lock detect) signal. The frequency divide ratio settings will cause the two PLLs to lock to the desired frequencies. In this mode the 2nd LO output signal can have a calibration signal added to the 2LO VCO signal. This calibration signal is used for discriminator alignment on the ML2713. The 8 bit DAC and associated comparator circuit are enabled. Low High Low RECEIVE The Receive RF down-converter, 1LO PLL & VCO, 2LO PLL & VCO, RSSI DAC, and RSSI comparator are all enabled, although for maximum flexibility any of these circuits could be disabled via the Serial Control Bus. High Low Low TRANSMIT The Transmit RF down-converter, Wideband PLL, 1LO PLL & VCO, 2LO PLL & VCO, and RSSI D/A are all enabled, although for maximum flexibility any of these circuits could be disabled via the Serial Control Bus Table 1. Operating Mode ControlStates 12 PRELIMINARY DATASHEET January, 2000 PRELIMINARY ML2712 CONTROL INTERFACES (CONTINUED) SERIAL CONTROL BUS pulses are active and either may be used to latch control words, although not simultaneously. In this mode DACEN will write data to the 8-bit DAC regardless of the address data. The EN pulse will continue to operate as described for DCE set to 0. The ML2712 contains two 3-wire serial control interfaces. They have common clock and data, but separate latch enable controls (EN & DACEN). The EN signal programs the registers that determine the operation of the PLLs, VCOs and DAC, and determines which circuits are active in STANDBY, RECEIVE and TRANSMIT Modes. The DACEN signal is dedicated to DAC programming only. Serial bus control is active in all operating Modes. The serial control interface overrides the parallel mode control interface. See Table 2 and Figure 9. The ML2712 default power up condition is designed for normal operation. At power up the registers are programmed as in Table 4. The user may adjust the mode of operation for specific tasks by programming the control register settings immediately after power up, or at an appropriate time during operation. Note that address field 000 is reserved for test modes and should not be programmed in normal operation. All DATA bits are clocked into the ML2712 while EN or DACEN is low and loaded into the addressed latch on the low to high trailing edge of the EN or DACEN pulse. The serial bus control register only retains the last 16 bits of data that follow either the EN or DACEN pulse. The data latches are fully static CMOS and use minimal power when the Serial Control Bus is inactive. tS tR tH tCK tF tL CLK tSE DATA All Serial Control Bus words are entered data MSB first. The word is made up of data and address fields. The data field is the leading 13 bits and the last 3 bits are the address field (see Table 3). The address field determines the destination register for the data field. There are 5 control registers (CONTROL WORDs A, B, C, D, and E) defined in Table 4. When data is latched by a DACEN pulse the address field is ignored and the data field is always used to program the 8-bit DAC. In Tables 3 and 4 the left-most bit isalways the MSB. MSB tEW EN & DACEN Figure 9. Control Bus Timing Parameter Min Typ Max Units 15 ns CLK EN or DACEN are enabled to latch data into the DAC register as determined by the DCE control bit, b4 in Control Word B. When DCE is set to 0, the default power up state, the EN latch enable pulse is active and the DACEN pulse is disabled. In this state a rising edge on EN will write data to the 8-bit DAC when the address field is correct. Other control words may be written using different address fields as shown in Table 4. When DCE is set to 1 both DACEN and EN tR Rise time tF Fall time tCK Period 50 15 ns ns tEW Pulse width 2 ns tL Falling edge delay 15 ns tSE Rising edge setup 15 ns tS Data-to-Clock Setup 15 ns tH Data-to-Clock Hold 15 ns EN & DACEN DATA Table 2. Three Wire Bus Interface Timing Characteristics Field bit DATA ADDRESS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Data Data Data Data Data Data Data Data Data Data Data Data Data Add Add Add 12 11 10 9 8 7 6 5 4 3 2 1 0 3 2 1 Function Table 3. Format of Serial Control Bus data January, 2000 PRELIMINARY DATASHEET 13 PRELIMINARY ML2712 CONTROL INTERFACES (CONTINUED) Data Control Word A Power Up Default Control Word B Power Up Default b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 VC1 VC2 PLL1 PLL2 CP1 CP2 PP1 PP2 LD1 LD2 PPW PB x 1 1 1 1 1 1 1 1 1 1 1 1 x TX RX LBC DAC DCE COM CI1 CI2 CI3 CI4 CAL WB x 0 0 0 1 0 1 1 1 1 1 1 1 x MSB 1LO ND1 Counter LSB Control Word C Power Up Default 1 1 MSB Control Word D 0 1 1 MSB 1LO NS1 Swallow Counter LSB 0 2LO ND2 Counter 0 1 0 1 2LO NS2 Counter MSB Power Up Default 1 0 0 0 0 Control Word E x x x x MSB Power Up Default x x x x 0 0 b13 b14 b15 0 0 1 0 1 0 x 0 Address x Reference Div. 0 x 1 1 Address LSB 1 1 0 0 0 0 8-bit DAC Voltage 0 0 0 0 0 0 1 x LSB x 0 x 1 0 0 Address 1 0 1 Table 4. Control Word Settings on the Serial Control Bus Control Bit in CONTROL WORD A ML2712 Circuits Enabled 1LO Charge Pump 2LO Charge Pump x x x x x x x x ON x x x x x x ON x x x x x x x ON x x 1 x x x x x ON 1 1 V C1 VC2 PLL1 PLL2 CP1 CP2 1LO VCO 2LO VCO 1LO PLL 0 0 0 0 0 0 1 x x x x x ON x x x 1 x x x x x ON x x 1 x x x x x x x 1 x x x x x x 1 x x x x 1 1 1 1 2LO PLL ALL OFF ALL ON (DEFAULT POWER UP CONDITION) Table 5. VCO, PLL and Charge Pump Power Control Modes CONTROL WORD A Control Word A enables the VCOs, PLL dividers, PLL charge pumps and voltage reference circuits; programs the polarity of PLL charge pumps; and programs the function of the Lock Detect (LD) output. oscillators to down convert the 2450 MHz ISM Band RF signal. (Table 5). All these circuit components are enabled individually using CONTROL WORD A as defined in Table 4. For the PLLs to operate, all control bits must be set to 1. Control Bits VC1, VC2, PLL1, PLL2, CP1, CP2 Two frequency synthesizers, 1LO and 2LO, each contain a VCO and a PLL. This dual conversion superheterodyne receiver uses the two local 14 PRELIMINARY DATASHEET January, 2000 PRELIMINARY ML2712 CONTROL INTERFACES (CONTINUED) Control Bits LD1 & LD2 Control Bit PB The PLLs indicate their lock status using the Lock Detect output (LD Pin 3). Control bits LD1 & LD2 program the indication of frequency lock on 1LO, 2LO, or both 1LO and 2LO, as shown in Table 6. A band-gap voltage reference is used to control bias levels. Control Bit PB in CONTROL WORD A controls this internal voltage reference. For any circuits to operate, other than the control interfaces, this bit must equal 1. Control Mode LO Status LD1 LD2 1LO CONTROL WORD B 2LO LD Pin output Mode of Operation Output disabled 0 0 x x 1 0 1 unlocked unlocked 0 0 1 locked 1 unlocked locked locked locked unlocked 0 0 1 1 0 unlocked unlocked 0 1 0 locked unlocked 0 1 1 0 0 unlocked locked locked locked 1 1 1 1 unlocked unlocked 0 1 1 locked unlocked 0 1 1 1 1 unlocked locked locked locked 0 1 1LO lock indication Control Bits TX, RX & LBC 2LO lock indication 2LO & 1LO lock indication Table 6. Lock Detect Mode Control Bits PP1, PP2 & PPW In each PLL a charge pump or switched current source either sinks or sources a current pulse depending on the error signal at the phase detector. Iif the divided VCO frequency at the phase detector is greater than the reference frequency, the charge pump will source a current pulse. The current pulse is fed to an external loop filter serving as an integrator or current reservoir. The result is the voltage across the loop filter and the tuning voltage to the VCO increasing or decreasing depending on the loop filter being referenced to ground or the power supply. The polarity of charge pumps within the PLL and transmit wideband PLL (WBPLL) may be programmed using CONTROL WORD A as shown in Table 7. The charge pump current settings in Table 10 assume that the external loop filter is reference to ground. Control Bit in CONTROL WORD A PP1 PP2 PPW Control Word B changes the control mode in which ML2712 operates. CONTROL WORD B may also be used to program charge pump current level and enable the DAC, Comparator & calibration circuits. The Mode of operation can be controlled via the serial interface (which disables the parallel operating mode interface). This option reduces the pin count requirement for a baseband controller. Individual circuit blocks may all be toggled on or off using control words. Extra control mode bits, TX & RX in CONTROL WORD B, are provided to enable transmit and receive switching via the Serial Control Bus interface. These control bits are enabled by the LBC control bit as shown in Table 8. Individual circuit blocks may be controlled by the Serial Control Bus control interface during LBC = 1 mode. When LBC = 1 the control lines TS (pin 47) and RS (pin 48), are ignored and the Mode of operation is determined by the TX and RX bit in Control Word D. Control Bit in CONTROL WORD B Control Status TX RX LBC X X 0 Parallel Control Interface (Default Power on condition) 0 0 1 Serial control - Tx & Rx circuits off 0 1 1 Serial control - Rx circuits on 1 0 1 Serial control - Tx circuits on 1 1 1 Serial control - Tx & Rx circuits off Table 8. Parallel Control Over-Ride Using LBC Bit ML2712 Charge Pump Polarity 1LO Charge pump polarity Frequency signal > Frequency ref. Pump high Frequency signal > Frequency ref. Pump low 1 x x 0 x x x 1 x x x 0 x x 2LO Charge pump polarity WBPLL Charge pump polarity x x x x Frequency signal > Frequency ref. Pump high Frequency signal > Frequency ref. Pump low x x 1 x x x x 0 x x x x Frequency signal > Frequency ref. Pump high Frequency signal > Frequency ref. Pump low Table 7. Charge Pump Polarity January, 2000 PRELIMINARY DATASHEET 15 PRELIMINARY ML2712 CONTROL INTERFACES (CONTINUED) Control Bits DAC, COM & DCE Control Bits CI1, CI2, CI3, CI4 The DAC and comparator may be used as a tracking ADC circuit. In normal operation these circuits are available in TRANSMIT, RECEIVE & STANDBY operating Modes. However, independent control of the comparator and DAC is available via control bits as shown in Table 9. There are two other modes available to program the DAC. When DCE in CONTROL WORD B is set to 0, EN is active and DACEN is disabled. With DCE at 1 both the DACEN and EN pins are active. DACEN and EN cannot be simultaneously low. With DCE at 1 a rising edge on DACEN will write data to the 8-bit DAC regardless of the address data. The PLLs each contain a charge pump. The magnitude of the current in these pumps may be controlled as defined in Table 10. The recommended values for best phase detector performance are [CI1,CI2]=[1,0] or [1,1] and [CI3,CI4] = [1,0] or [1,1]. Control Bit in CONTROL WORD B Circuits Enabled DAC COM 1 1 DAC & Comparator on (Default power up state) 0 1 DAC off, Comparator on 1 0 DAC on, Comparator off 0 0 DAC & Comparator off Control Bit CAL The ML2713 companion to the ML2712 contains selfaligning filter and discriminator circuits. The alignment of these circuits is designed to take place when the ML2712/ ML2713 chipset is in STANDBY Mode ( Table 1). Under power up default conditions in STANDBY Mode the ML2712 provides an 8 MHz calibration tone to the ML2713 via the 2LO output (pins 2LO & 2LOB). This will happen while the 1LO and 2LO local oscillators are phase locking. However, the CAL tone may be disabled using CONTROL WORD B (See Table 11). Table 9. Control of ML2712 DAC & Comparator Control Bit in CONTROL WORD B Charge Pump Setting CI1 CI2 CI3 CI4 1LO Charge pump current (mA) 2LO Charge pump current (mA) 0 0 x x 0.25 x 0 1 x x 0. 5 x 1 0 x x 1 x 1 1 x x 2 x x x 0 0 x 0.25 x x 0 1 x 0.5 x x 1 0 x 1 x x 1 1 x 2 Table 10. Charge Pump Currents CAL bit in CONTROL WORD B Calibration Mode WB bit in CONTROL WORD B Calibration Mode 0 Calibration output to 2LO disabled 1 Wideband PLL phase Dual PFD & XOR mode 1 Calibration tone to 2LO port enabled (Default power up mode) 0 Wideband PLL phase In XOR only mode Table 11. Control of Calibration Tone Generation 16 PRELIMINARY DATASHEET Table 12. Control of CalibrationTone Generation January, 2000 PRELIMINARY ML2712 CONTROL INTERFACES (CONTINUED) CONTROL WORD C RSSI INPUT VOLTAGE 2LO ND & NS counters are denoted as ND2 & NS2. The binary weighted modulus values are loaded using CONTROL WORD C as shown in Table 13. The prescaler used in the 2LO PLL is a 14/15 dual modulus type giving the 2LO frequency in MHz as f2LO = (14 ´ ND2 + NS2) ´ (fREF /M). + BASEBAND IC TPL OUTPUT VOLTAGE 8 SCALING AMPLIFIER The reference divider ratio M is also set in CONTROL WORD C (Table 4) Control Bit CONTROL WORD C Reference Division Ratio M b9 b10 b11 0 0 0 16 0 0 1 32 (Power up Default) 0 1 0 20 0 1 1 40 Alternatively, the DAC may be programmed with a threshold value that when exceeded triggers the baseband IC into receive mode. In this mode the DAC and Comparator are used to provide the necessary circuits for Clear Channel Assessment (CCA) as defined in IEEE 802.11. Figure 11 shows the relationship between RSSI DAC code (in decimal) programmed into ML2712 via CONTROL WORD E and the DAC RSSI voltage threshold. 250 VCCD = 5.0V VCCA = 3.3V 200 DAC CODE The 1LO PLL is a dual modulus type as described above. 1LO ND & NS counters are denoted in ML2712 as ND1 & NS1. Modulus values are binary weighted and are loaded using CONTROL WORD D as shown in Table 4. The prescaler used in the 1LO PLL is a 40/41 dual modulus type giving the 1LO frequency in MHz as CONTROL WORD D [B4...B11] 8 BIT D/A Figure 10. Charge Pump Polarity Table 13. Reference Division Ratio CONTROL WORD D RSTH – 150 100 50 0 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 RSSI THRESHOLD VOLTAGE (V) Figure 11. Parallel Control Over-Ride Using LBC Bit CONTROL WORD E The 8-bit DAC and Comparator form a tracking Analog-to-Digital converter (ADC) intended to connect to the RSSI (Receive Signal Strength Indicator) on the ML2713. The tracking ADC is represented in Figure 10. CONTROL WORD E is used to program a voltage into the 8-bit DAC setting up a voltage on the inverting terminal of the Comparator. If the RSSI voltage exceeds that on the DAC then RSSITH signals logic high. Typically, a baseband IC will be used to program RSSI values into the ML2712 corresponding to a known receive signal level. The RSTH value (high/low) is sensed by the baseband IC to determine if the signal strength threshold has been exceeded. By successively programming the 8-bit DAC using CONTROL WORD E the baseband IC can measure the RSSI voltage closely. The DAC also has a general purpose use. The DAC voltage programmed using CONTROL WORD E is fed to scaling circuit before appearing externally at TPL. While the DAC output is suitable for general use, a likely use for the voltage is for transmit power control. In this mode of operation the DAC voltage corresponding to the required transmitter output power can be programmed before transmit operation. The relationship between TPL voltage versus DAC programming is shown in Figure 12. 250 VCCD = 5.0V VCCA = 3.3V LOAD ON TPL = 1MΩ IN PARALLEL WITH 15pF 200 DAC CODE f1LO = (40 ´ ND1 + NS1) ´ (fREF /M). 150 100 50 0 0.5 1.0 1.5 2 2.5 3 TPL VOLTAGE (V) Figure 12. Control of ML2712 DAC Comparator January, 2000 PRELIMINARY DATASHEET 17 PRELIMINARY ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS ML2712 OPERATING CONDITIONS Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. Commercial Temperature Range .................... 0°C to 70°C Extended Temperature Range ..................... -20°C to 70°C VCC1 Range .................................................3.0V to 5.5V VCC2Range ................................................ 3.3V ± TBD% Thermal Resistance (qJA) (Note 2) ...................... 100°C/W VCC1 ........................................................................................... 6.0V VCC2, RVCC1, VCC3, RVCC2, VCC4, VCC8 , VCC5 , VCC6 , RVCC3 ........................................ -0.3V to VCC1 + 0.3V Storage Temperature Range ..................... –65°C to 150°C Lead Temperature (Soldering, 10s) .......................... 260°C ELECTRICAL TABLES Unless otherwise specified, VCC1 = 5V, VCC2, RVCC1, VCC3, RVCC2, VCC4, VCC8, VCC5, VCC6, RVCC3 = 3.3V, TA = Operating Temperature Range. (Note 1) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS POWER CONSUMPTION TRANSMIT AND RECEIVE RF All Circuits, Sleep Mode DC Connected 10 µA Supply Current, Standby Mode 61 mA Supply Current, Receive Mode 66 mA Supply Current, Transmit Mode 94 mA Input High V CCD V Output Low 0 V INTERFACE LOGIC LEVELS Input Bias Current All States ±5 µA Input Capacitance (Not Tested) 4 pF Lock Detect Output Low ISINK = 0.5mA 0.4 V Time, Sleep to Standby, PLLs Locked (Note 3) From LOE Asserted to 1LO and 2LO Within 20KHz of Final Frequency 150 µs PLL Lockup Time, Standy & Receive (Note 3) From EN Asserted to 1LO and 2LO Within 20KHz of Final Frequency 150 µs Time, Standby to Receive Time from RS Asserted to Receive RF Down Converter Enabled 1 µs Time, Standby to Transmit Time from TS Asserted to Transmit RF Down Converter and Wideband PLL Enabled 1 µs Time, Receive to Transmit From RS de-asserted, TS asserted and Wideband PLL & Transmit Down Converter Ready 1 µs MODE CONTROL PINS ELECTRICAL TABLES (CONTINUED) 18 PRELIMINARY DATASHEET January, 2000 PRELIMINARY ML2712 ELECTRICAL TABLES (CONTINUED) SYMBOL PARAMETER CONDITIONS Time, Transmit to Receive MIN From TS de-asserted, RS asserted to Receive RF Mixer Ready TYP MAX UNITS 1 µs –1.5 dB 15 dB –9.5 dBm 0 dBm RECEIVE RF MIXER Receive RF Mixer Gain Receive RF Mixer Noise Figure Receive RF Mixer Input 1dB Gain Compression Point In-band Tone Receive RF Mixer Input IP3 Receive RF Input Impedance Nominal, single ended into RRFI, 1.5 pF shunt capacitor external matching 50 W Receive RF Output Impedance Differential 340 W Receive RF Mixer Turn on Time. 1 µs Receive RF Mixer Turn off Time. 1 µs RECEIVE 1LO VCO AND 1LO PLL 1LO Output Frequency 1060 MHz Minimum Q for Performance Required of 1LO Unloaded Q of Tank Circuits. 10 1LO, Integrated Noise, out of Receive 1MHz –45 dBc Band in 1MHz Band at Offsets from 2MHz –50 dBc Carrier. Integrated +/-500kHz about 3MHz –55 dBc Comparison Frequency >3MHz –55 dBc 500 kHz 1LO PLL Reference Frequency at Phase Detector 1LO Division Range REF 1130 2000 2260 Integer 1LO Lock up Time for any Valid Frequency From LE asserted. Maximum charge Change pump current 150 µs 1LO Lock up Time from Sleep (Note 3) PLL Dividers Programmed, Maximum Charge Pump Current 150 µs Reference Signal Input Level Single Ended, Square Wave, Peak V CCA mV 236 MHz 10 kHz –50 dBc 2LO VCO AND PLL 2LO frequency Frequency Pulling Switching among Transmit, Receive and Standby. Phase Noise Double Sideband, Integrated from 5kHz to 600kHz (Note 4) 2LO, Integrated Noise, out of Receive 1MHz –55 dBc Band in 1MHz Band at Offsets from 2MHz –60 dBc Carrier. Integrated ±500kHz about 3MHz –65 dBc Frequency >3MHz –65 dBc January, 2000 XX/XX/99 Printed in U.S.A. PRELIMINARY DATASHEET 19 PRELIMINARY ML2712 ELECTRICAL TABLES (CONTINUED) ELECTRICAL TABLES (CONTINUED) SYMBOL PARAMETER Output Signal level, Differential CONDITIONS MIN 200W Balanced Load Reference Frequency 2LO PLL Reference Frequency at Phase Detector 2LO Division Ratio Assumes 1MHz Comparison Frequency for 2LO 2LO Lock up Time (Note 4) From Enable 2LO to Within 10kHz of Final Frequency TYP MAX UNITS 30 mV 32 or 16 MHz 500 kHz 216 256 Integer 100 µs 8 bits ±0.5 LSB ±1 LSB Temperature coefficient 3 PPM/ºC Offset error ±3 LSB DAC Resolution Relative accuracy Differential Non-linearity Monotonic under all Conditions RSSI Voltage Conversion Range Sensed by RSTH Comparator, DAC Code 0 to Code 255 2.0 3.2 V TPL Output Voltage Range Load = 1MW, DAC Code 0 to Code 255 0.7 2.8 V 5 mA 0.15 V/µs 500 ns 50 dB Output High V CCD V Output Low 0.0 ±0.3 V Output Sink/Source Capability 4 mA Input Offset Error 2 mV 500 ns Input Voltage Range 2 V RSSI Input Bias Current 20 µA –10 dBm 1 µs Maximum Difference Frequency Between 1LO ´ 2 and Transmit VCO (Note 5) 500 MHz Minimum Difference Frequency Between 1LO ´ 2 and Transmit VCO (Note 5) 100 MHz Short Circuit Current Output slew rate Output Settling Time To within ½ LSB Signal to Noise and Distortion COMPARATOR Input to Output Propagation Delay Input to Output High and Input to Output Low TRANSMIT RF MIXER AND WIDEBAND PHASE COMPARATOR Transmit RF Input Signal Power Transmit RF Mixer and Wideband Phase Comparator Turn on Time 20 PRELIMINARY DATASHEET January, 2000 PRELIMINARY ML2712 ELECTRICAL TABLES (CONTINUED) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Frequency of Reference Signal Modulation on Reference 240 260 280 MHz Transmitter Phase Noise (Note 6) External Transmit VCO Locked to the ILO –126 dBc/Hz Transmitter Phase Noise in 1MHz 1MHz –50 dBc Band at Offsets from Carrier. Integrated 2MHz –66 dBc ±500kHz about Frequency. 3MHz –66 dBc >3MHz –66 dBc 2 µs 3 kHz Lock up Time, from any Starting Transmit 1LO and Receive 1LO Frequency to <20kHz (Note 6) Modulation Error (Note 7) 1MSymbol/s 2GFSK or 4GFSK to Ideal GFSK Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst case test conditions. Note 2: qJA is measured with the component mounted on the Evaluation PCB in free air. Note 3: Phase noise and lock up time tested with 1LO VCO Q = 10, kVCO = 100MHz/V. Phase noise measured at IF output by down converting a 2450MHz signal to a 260MHz IF. Input signal at –20dBm. Charge pump current set to default. Note 4: Measurements taken with 236MHz 2LO. Tank circuit of 2LO VCO Q = 8, kVCO = 40MHz/V.Charge pump current set to maximum. Note 5: This is proven by design, it is not tested in production. Note 6: Measured with an external Transmit VCO, with Q = 15, kVCO = 120MHz/V, output power 0dBm, –10dBm input to TS272. Reference signal is a 260MHz sine wave. Note 7: Measured with an external Transmit VCO, with Q = 15, kVCO = 120MHz/V, output power 0dBm, –10dBm input to TS272. Reference is a 260MHz center frequency signal, modulated with 4GFSK. Error is measured relative to the reference signal at the center of the data symbol. January, 2000 PRELIMINARY DATASHEET 21 PRELIMINARY ML2712 PHYSICAL DIMENSIONS Package: H48-7 48-Pin (7 x 7 x 1mm) TQFP 0.354 BSC (9.00 BSC) 0.276 BSC (7.00 BSC) 0º - 8º 0.003 - 0.008 (0.09 - 0.20) 37 1 PIN 1 ID 0.276 BSC (7.00 BSC) 0.354 BSC (9.00 BSC) 0.018 - 0.030 (0.45 - 0.75) 25 13 0.020 BSC (0.50 BSC) 0.048 MAX (1.20 MAX) 0.007 - 0.011 (0.17 - 0.27) SEATING PLANE 0.037 - 0.041 (0.95 - 1.05) ORDERING INFORMATION PART NUMBER TEMPERATURE RANGE PACKAGE ML2712CH 0°C to 70°C 48 Pin TQFP 7mm body ML2712EH -20°C to 70°C 48 Pin TQFP 7mm body Micro Linear Corporation 2092 Concourse Drive San Jose, CA 95131 Tel: (408) 433-5200 Fax: (408) 432-0295 www.microlinear.com DS2712-01 22 PRELIMINARY DATASHEET January, 2000