INF8574 GENERAL DESCRIPTION The INF8574 is a silicon CMOS circuit. It provides general purpose remote I/O expansion for most microcontroller families via the two-line bidirectional bus (I2C). The device consists of an 8-bit quasi-bidirectional Port and an I2C interface. The INF8574 has a low current consumption and includes latched outputs with high current drive capability for directly driving LEDs. It also possesses an interrupt line (INT) which can be connected to the interrupt logic of the microcontroller. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via the I2C-bus. This means that the INF8574 can remain a simple slave device. FEATURES Operating supply voltage 2.5 to 6 V Low standby current consumption of 10 A maximum I2C to parallel port expander Open-drain interrupt output 8-bit remote I/O Port for the I2C-bus Compatible with most microcontrollers Latched outputs with high current drive capability for directly driving LEDs Address by 3 hardware address pins for use of up to 8 devices (up to 16 with INF8574A) DIP16, space-saving SO16 or SSOP20 package. BLOCK DIAGRAM 1 INF8574 PINNING SYMBOL A0 A1 A2 P0 P1 P2 P3 V SS P4 P5 P6 P7 INT SCL SDA V DD PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DESCRIPTION address input 0 address input 1 address input 2 quasi-bidirectional I/O Port 0 quasi-bidirectional I/O Port 1 quasi-bidirectional I/O Port 2 quasi-bidirectional I/O Port 3 supply ground quasi-bidirectional I/O Port 4 quasi-bidirectional I/O Port 5 quasi-bidirectional I/O Port 6 quasi-bidirectional I/O Port 7 interrupt output (active LOW) serial clock line serial data line supply voltage CHARACTERISTICS OF THE I2C-BUS The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals Bit transfer. Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop condition (P). Definition of start and stop conditions. 2 INF8574 System configuration A device generating a message is a ‘transmitter’, a device receiving is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’. System configuration. Acknowledge The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse, set-up and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a stop condition. Acknowledgement on the I2C-bus. 3 INF8574 FUNCTIONAL DESCRIPTION Simplified schematic diagram of each Port. Addressing For addressing. INF8574A INF8574 Slave addresses. Each bit of the INF8574 I/O Port can be independently used as an input or output. Input data is transferred from the Port to the microcontroller by the READ mode (see Fig.11). Output data is transmitted to the Port by the WRITE mode (see Fig.10). 4 INF8574 WRITE mode (output Port). 5 INF8574 A LOW-to-HIGH transition of SDA, while SCL is HIGH is defined as the stop condition (P). Transfer of data can be stopped at any moment by a stop condition. When this occurs, data present at the last acknowledge phase is valid (output mode). Input data is lost. READ mode (input Port). 6 INF8574 Interrupt The INF8574 provides an open drain output (INT) which can be fed to a corresponding input of the microcontroller. This gives these chips a type of master function which can initiate an action elsewhere in the system. An interrupt is generated by any rising or falling edge of the Port inputs in the input mode. After time tiv the signal INT is valid. Resetting and reactivating the interrupt circuit is achieved when data on the Port is changed to the original setting or data is read from or written to the Port which has generated the interrupt. Resetting occurs as follows: In the READ mode at the acknowledge bit after the rising edge of the SCL signal. In the WRITE mode at the acknowledge bit after the HIGH-to-LOW transition of the SCL signal. Interrupts which occur during the acknowledge clock pulse may be lost (or very short) due to the resetting of the interrupt during this pulse. Each change of the Ports after the resettings will be detected and after the next rising clock edge, will be transmitted as INT. Reading from or writing to another device does not affect the interrupt circuit. Quasi-bidirectional I/O Ports A quasi-bidirectional Port can be used as an input or output without the use of a control signal for data direction. At power-on the Ports are HIGH. In this mode only a current source to VDD is active. An additional strong pull-up to VDD allows fast rising edges into heavily loaded outputs. These devices turn on when an output is written HIGH, and are switched off by the negative edge of SCL. The Ports should be HIGH before being used as inputs. Application of multiple INF8574s with interrupt. Interrupt generated by a change of input to Port P5. 7 INF8574 Transient pull-up current IOHt while P3 changes from LOW-to-HIGH and back to LOW. 8 INF8574 LIMITING VALUES SYMBOL VDD VI II IO IDD ISS Ptot PO Tstg Tamb PARAMETER supply voltage input voltage DC input current DC output current supply current supply current total power dissipation power dissipation per output storage temperature operating ambient temperature MIN. -0.5 VSS - 0.5 65 40 MAX. +7.0 VDD + 0.5 ±20 ±25 ±100 ±100 400 100 +150 +85 UNIT V V mA mA mA mA mW mW o C o C DC CHARACTERISTICS VDD = 2.5 to 6 V; VSS = 0 V; Tamb =40 to +85 oC; unless otherwise specified. SYMBOL Supply VDD IDD PARAMETER supply voltage supply current Istb standby current VPOR power-on reset voltage Input SCL; input/output SDA VIL LOW level input voltage VIH HIGH level input voltage IOL LOW level output current |IL| leakage current CI input capacitance I/O Ports VIL LOW level input voltage VIH HIGH level input voltage IIHL(max) maximum allowed input current through protection diode IOL LOW level output current IOH HIGH level output current IOHt transient pull-up current CI input capacitance CO output capacitance Port timing CL ≤100 pF tpv output data valid tsu input data set-up time th input data hold time Interrupt INT IOL LOW level output current |IL| leakage current Timing; CL ≤100 pF t iv input data valid time t ir reset delay time Select inputs A0 to A2 VIL LOW level input voltage VIH HIGH level input voltage |ILI| input leakage current CONDITIONS MIN. TYP. MAX. UNIT 40 6.0 100 V µA 2.5 10 µA 1.3 2.4 V +0.3VDD VDD + 0.5 1 7 V V mA µA pF +0.3VDD VDD + 0.5 ±400 V V µA 300 mA µA mA 10 10 pF pF 4 µs µs µs 2.5 operating mode; VDD = 6 V; ; no load; VI = VDD or VSS fSCL = 100 kHz standby mode; VDD = 6 V; no load; VI = VDD or VSS VDD = 6 V; no load; VI = VDD or VSS; note 1 VOL = 0.4 V VI = VDD or VSS V =V I SS -0.5 0.7VDD 3 -0.5 -0.7VDD VI ≥VDD or VI≤ VSS VOL = 1 V; VDD = 5 V VOH = VSS HIGH during acknowledge ; (see Fig.14); VOH = VSS VDD = 2.5 V 10 30 25 1 0 4 V OL = 0.4 V VI = VDD or VSS 1.6 -0.5 0.7VDD pin at VDD or VSS 1 mA µA 4 4 µs µs +0.3VDD VDD + 0.5 250 V V nA Note 2 1. The power-on reset circuit resets the I C-bus logic with VDD < VPOR and sets all Ports to logic 1 (with cur- rent source to VDD). 9 INF8574 I2C-BUS TIMING CHARACTERISTICS SYMBOL 2 I C-BUS TIMING fSCL tSW tBUF tSU;STA tHD;STA tLOW tHIGH tr tf tSU;DAT tHD;DAT tVD;DAT tSU;STO Note 1. PARAMETER MIN. SCL clock frequency tolerable spike width on bus bus free time start condition set-up time start condition hold time SCL LOW time SCL HIGH time SCL and SDA rise time SCL and SDA fall time data set-up time data hold time SCL LOW to data out valid stop condition set-up time TYP. MAX. UNIT 100 100 kHz ns µs µs µs µs µs µs µs ns ns µs µs 4.7 4.7 4.0 4.7 4.0 1.0 0.3 250 0 3.4 4.0 All the timing values are valid within the operating supply voltage and ambient temperature range and refer to VIL and VIH with an input voltage swing of VSS to VDD. I2C-bus timing diagram. 10