FAIRCHILD FAN6206MY

FAN6206
Highly Integrated Dual-Channel Synchronous
Rectification Controller for Dual-Forward Converter
Features
Description
ƒ
ƒ
Highly Integrated Dual-Channel SR Controller
ƒ
Internal Linear-Predict Timing Control for DCM
Operation
The highly integrated FAN6206 is a dual-channel
synchronous rectification (SR) controller. FAN6206
allows design of a cost-effective power supply with
fewer external components, especially suited for dualforward topology used to obtain higher efficiency for
ATX power supplies.
ƒ
Ultra-Low VDD Operating Voltage for Different
Output Voltage of PC Power
ƒ
ƒ
VDD Over-Voltage Protection
Receives Synchronized Driving Signal from the
Primary Side
14V Gate Driver Clamp
Applications
ƒ
ƒ
ƒ
PC Power
Server Power
Open-Frame SMPS
The primary-side control method provides synchronous
rectification control for dual-forward converters that
operate in continuous conduction mode (CCM).
FAN6206 includes a proprietary linear-predict timing
control mechanism for dual-forward converters that
operate in discontinuous conduction mode (DCM) at
fixed or variable frequency. PWM frequency tracking
with secondary-side winding detection is provided by
adding dividing resistors. The primary-side signals are
generated from Fairchild’s FAN6210 (Primary-Side
Synchronous Rectifier Signal Trigger for Dual-Forward
Converter). The primary-side signals are transferred
through a pulse transformer to the secondary-side. The
benefits of this technique include simple control method
and improved power system reliability.
FAN6206 is available in 8-pin SOP package.
Ordering Information
Part Number
Operating
Temperature Range
Package
Packing
Method
FAN6206MY
-40°C to +105°C
8-Pin Small Outline Package (SOP)
Tape & Reel
© 2010 Fairchild Semiconductor Corporation
FAN6206 • Rev. 1.0.2
www.fairchildsemi.com
FAN6206 —Highly Integrated Dual-Channel Synchronous Rectification Controller for Dual-Forward Converter
April 2010
Figure 1. Typical Application
Internal Block Diagram
FAN6206 — Highly Integrated Dual-Channel Synchronous Rectification Controller for Dual-Forward Converter
Application Diagram
Figure 2. Functional Block Diagram
© 2010 Fairchild Semiconductor Corporation
FAN6206 • Rev. 1.0.2
www.fairchildsemi.com
2
F: Fairchild Logo
Z: Plant Code
X: Year Code
Y: Week Code
TT: Package Type
T: M=SOP
P: Y: Green Package
M: Manufacture Flow Code
Figure 3. Top Mark
Pin Configuration
Figure 4. Pin Configuration
Pin Definitions
Pin #
Name
Description
1,2
LPC1,
LPC2
3
SN
Synchronized signal to turn on SR. This pin is used to receive the “XN” signal from the primary
side to turn off the SR gate.
4
SP
Synchronized signal to turn on SR. This pin is used to receive the “XP” signal from the primaryside to turn-on the SR gate.
5
VDD
6
GATE2
7
GND
8
GATE1
Winding detection. This pin is used to detect the voltage on the winding during the on-time
period of the primary GATE. An internal current source, ICHG, is determined according to the
voltage on the DET pin.
Power supply pin. The threshold voltages for startup and turn-off are 8.5V and 7.5V,
respectively.
Driver output for freewheeling synchronous rectifier MOSFET.
Ground
Driver output for rectifying synchronous rectifier MOSFET.
© 2010 Fairchild Semiconductor Corporation
FAN6206 • Rev. 1.0.2
FAN6206 — Highly Integrated Dual-Channel Synchronous Rectification Controller for Dual-Forward Converter
Marking Information
www.fairchildsemi.com
3
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
Max.
Unit
VDD
DC Supply Voltage
30
V
VHV
SP, SN
30
V
VL
LPC
7.0
V
PD
Power Dissipation at TA < 50°C
400
mW
ΘJA
Junction to Ambient Thermal Resistance
130
°C/W
Ψjt
Junction to Top Thermal Characteristics
46
°C/W
TJ
Operating Junction Temperature
-40
+125
°C
Storage Temperature Range
-55
+150
°C
°C
TSTG
TL
ESD
-0.3
Lead Temperature, (Soldering 10 Seconds)
+260
Human Body Model, JESD22-A114
4.00
Charged Device Model, JESD22-C101
1.25
kV
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
2. All voltage values, except differential voltages, are given with respect to GND pin.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
TA
Parameter
Operating Ambient Temperature
© 2010 Fairchild Semiconductor Corporation
FAN6206 • Rev. 1.0.2
Min.
Max.
Unit
-40
+105
°C
FAN6206 — Highly Integrated Dual-Channel Synchronous Rectification Controller for Dual-Forward Converter
Absolute Maximum Ratings
www.fairchildsemi.com
4
VDD=20V, TA=25Ԩ, unless otherwise specified.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
25
V
VDD Section
VOP
VTH-ON1
Continuously Operating Voltage
Turn-On Threshold Voltage
8.0
8.5
9.0
V
VTH-ON2
Turn-On Threshold Voltage
8.0
8.5
9.0
V
VTH-OFF1
Turn-Off Threshold Voltage
7.0
7.5
8.0
V
VTH-OFF2
Turn-Off Threshold Voltage
7.0
7.5
8.0
V
3
5
mA
IDD-OP
Operating Current
VDD=15V, DET=50KHz
IDD-ST
Startup Current
VDD = 7.5V
340
500
μA
VDD-OVP1
VDD Over-Voltage Protection 1
20
21
22
V
VDD-OVP2
VDD Over-Voltage Protection 2
20
21
22
V
VDD-OVP-HYS1
Hysteresis Voltage for VDD OVP 1
1.2
1.7
2.2
V
VDD-OVP-HYS2
Hysteresis Voltage for VDD OVP 2
1.2
1.7
2.2
V
tOVP1
VDD OVP Debounce Time 1
40
60
100
μs
tOVP2
VDD OVP Debounce Time 2
40
60
100
μs
Output Drive for SR MOSFET Section
VZ1
Output Voltage Maximum (Clamp) 1
VDD = 20V
12
14
V
VZ2
Output Voltage Maximum (Clamp) 2
VDD = 20V
12
14
V
VOL1
Output Voltage LOW 1
VDD=12V, IO=50mA
0.5
V
0.5
V
VOL2
Output Voltage LOW 2
VDD=12V, IO=50mA
VOH1
Output Voltage HIGH 1
VDD=12V, IO=50mA
9
V
VOH2
Output Voltage HIGH 2
VDD=12V, IO=50mA
9
V
tR1
Rising Time 1
VDD=12V, CL=7nF,
OUT=2V~9V
30
70
120
ns
tR2
Rising Time 2
VDD=12V, CL=7nF,
OUT=2V~9V
30
70
120
ns
tF1
Falling Time1
VDD=12V, CL=7nF,
OUT=9V~2V
20
50
100
ns
tF2
Falling Time 2
VDD=12V, CL=7nF,
OUT=9V~2V
20
50
100
ns
VZ1
Output Voltage Maximum (Clamp)
VDD = 20V
12
14
V
tR+tPD,
(Trigger by SP),
|SP-SN|=5V
280
350
450
Propagation Delay to OUT HIGH
280
350
450
tR+tPD,
(Trigger by SN),
|SP-SN|=5V
180
250
350
Propagation Delay to OUT LOW
180
250
350
Propagation Delay to OUT LOW
tR+tPD,
(Trigger by LPC)
100
150
200
100
150
200
12
13
14
μs
12
13
14
μs
tPD-HIGH-SP1
tPD-HIGH-SP2
tPD-LOW-SN1
tPD-LOW-SN2
tPD-LOW-LPC1
tPD-LOW-LPC2
tON-MAX1
tON-MAX2
Maximum On Time
ns
ns
ns
FAN6206 — Highly Integrated Dual-Channel Synchronous Rectification Controller for Dual-Forward Converter
Electrical Characteristics
Continued on the following page…
© 2010 Fairchild Semiconductor Corporation
FAN6206 • Rev. 1.0.2
www.fairchildsemi.com
5
VDD=20V, TA=25°C, unless otherwise specified.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Sweep VN-P- from LOW
to HIGH
3
4
5
V
3
4
5
V
SP/SN Section
VN-P(turn off) 1
Threshold Voltage of
VN-VP to Turn-Off SR MOS 1
VN-P(turn off) 2
Threshold Voltage of
VN-VP to Turn-Off SR MOS 2
VP-N(turn on) 1
Threshold Voltage of
VP-VN to Turn-On SR MOS 1
Sweep VP-N- from LOW
to HIGH
3
4
5
V
VP-N(turn on) 2
Threshold Voltage of
VP-VN to Turn-On SR MOS 2
Sweep VP-N- from LOW
to HIGH
3
4
5
V
Ratio_SP-SN
Voltage Difference between
SP and SN
| VSP-VSN | /
MIN(VSP,VSN)
5
%
Ratio_LPC-RES
Charge Divide Discharge Current
Transfer Ratio vs. Input Voltage
Connect a Diode
1N4148 and Divider
(Ratio 12) to LPC,
VDET = 3V, VLPC = 3V
VLPC-EN1
VLPC-EN2
LPC Section
2.79
3.00
3.21
LPC Enable Threshold Voltage 1
1.8
2.0
2.2
V
LPC Enable Threshold Voltage 2
1.8
2.0
2.2
V
VLPC-CLAMP1
Lower Clamp Voltage 1
ILPC = -5μA
0.10
0.25
0.40
V
VLPC-CLAMP2
Lower Clamp Voltage 2
ILPC = -5μA
0.10
0.25
0.40
V
ILPC-SOURCE1
Maximum Source Current 1
VLPC = -0.3V
250
300
μA
ILPC-SOURCE2
Maximum Source Current 2
VLPC = -0.3V
250
300
μA
VLPC-LOW1
Threshold Voltage for Disable
LPC Function
1.3
1.5
1.7
V
VLPC-LOW2
Threshold Voltage for Disable
LPC Function
1.3
1.5
1.7
V
tLPC-LOW1
Debounce Time for Disable LPC
Function
VLPC < VLPC-LOW
70
100
130
μs
tLPC-LOW2
Debounce Time for Disable LPC
Function
VLPC < VLPC-LOW
70
100
130
μs
© 2010 Fairchild Semiconductor Corporation
FAN6206 • Rev. 1.0.2
FAN6206 — Highly Integrated Dual-Channel Synchronous Rectification Controller for Dual-Forward Converter
Electrical Characteristics
www.fairchildsemi.com
6
8.5
8.5
8.4
8.4
VTH-ON2 (V)
VTH-ON1 (V)
These characteristic graphs are normalized at TA = 25°C.
8.3
8.2
8.1
8.2
8.1
8.0
8.0
-40
-25
-10
5
20
35
50
65
80
95
110
125
-40
-25
-10
5
20
35
50
65
80
95
110
125
Temperature℃
Temperature℃
Figure 5. Turn-On Threshold Voltage 1
Figure 6. Turn-On Threshold Voltage 2
7.7
7.7
7.6
7.6
VTH-OFF2 (V)
VTH-OFF1 (V)
8.3
7.5
7.4
7.5
7.4
7.3
7.3
-40
-25
-10
5
20
35
50
65
80
95
110
125
-40
-25
-10
5
20
35
50
65
80
95
110
125
Temperature℃
Temperature℃
Figure 7. Turn-Off Threshold Voltage 1
Figure 8. Turn-Off Threshold Voltage 2
2.9
500
IDD_ST (uA)
IDD_OP (mA)
2.8
2.7
400
300
2.6
2.5
200
-40
-25
-10
5
20
35
50
65
80
95
110
125
-40
-25
-10
5
Temperature℃
35
50
65
80
95
110
125
110
125
Temperature℃
Figure 9. Operating Current
Figure 10.Startup Current
420
420
400
400
tPD-HIGH-SP2 (ns)
tPD-HIGH-SP1 (ns)
20
380
360
340
320
300
380
360
340
320
300
280
280
-40
-25
-10
5
20
35
50
65
80
95
110
125
-40
Temperature℃
-10
5
20
35
50
65
80
95
Temperature℃
Figure 11. Propagation Delay to OUT HIGH 1
(Trigger by SP)
© 2010 Fairchild Semiconductor Corporation
FAN6206 • Rev. 1.0.2
-25
FAN6206 — Highly Integrated Dual-Channel Synchronous Rectification Controller for Dual-Forward Converter
Typical Performance Characteristics
Figure 12.Propagation Delay to OUT HIGH 2
(Trigger by SP)
www.fairchildsemi.com
7
350
350
300
300
tPD-LOW-SN2 (ns)
tPD-LOW-SN1 (ns)
These characteristic graphs are normalized at TA = 25°C.
250
200
150
250
200
150
-40
-25
-10
5
20
35
50
65
80
95
110
125
-40
-25
-10
5
Temperature℃
35
50
65
80
95
110
125
Temperature℃
Figure 13. Propagation Delay to OUT LOW 1
(Trigger by SN)
Figure 14.Propagation Delay to OUT LOW 2
(Trigger by SN)
180
tPD-LOW-LPC2 (ns)
180
tPD-LOW-LPC1 (ns)
20
160
140
120
160
140
120
-40
-25
-10
5
20
35
50
65
80
95
110
125
-40
-25
-10
5
20
35
50
65
80
95
110
125
Temperature℃
Figure 15. Propagation Delay to OUT LOW 1
(Trigger by LPC)
Figure 16.Propagation Delay to OUT LOW 2
(Trigger by LPC)
14.0
14.0
13.5
13.5
tON-MAX2 (us)
tON_MAX1 (us)
Temperature℃
13.0
12.5
13.0
12.5
12.0
12.0
-40
-25
-10
5
20
35
50
65
80
95
110
125
-40
-25
-10
5
Temperature℃
35
50
65
80
95
110
125
Temperature℃
Figure 17. Maximum On Time 1
Figure 18.Maximum On Time 2
5.0
5.0
4.5
4.5
VN-P(turn off) 2 (V)
VN-P(turn off) 1 (V)
20
4.0
3.5
3.0
4.0
3.5
3.0
-40
-25
-10
5
20
35
50
65
80
95
110
125
-40
-25
-10
5
20
35
50
65
80
95
110
125
Temperature℃
Temperature℃
Figure 19. Threshold Voltage of VN-VP
to Turn Off SR MOS 1
Figure 20.Threshold Voltage of VN-VP
to Turn Off SR MOS 2
© 2010 Fairchild Semiconductor Corporation
FAN6206 • Rev. 1.0.2
FAN6206 — Highly Integrated Dual-Channel Synchronous Rectification Controller for Dual-Forward Converter
Typical Performance Characteristics
www.fairchildsemi.com
8
5.0
5.0
4.5
4.5
VP-N(turn on) 2 (ns)
VP-N(turn on) 1 (V)
These characteristic graphs are normalized at TA = 25°C.
4.0
3.5
3.0
3.5
3.0
-40
-25
-10
5
20
35
50
65
80
95
110
125
-40
-25
-10
5
20
35
50
65
80
95
110
125
Temperature℃
Temperature℃
Figure 21. Threshold Voltage of VP-VN
to Turn On SR MOS 1
Figure 22.Threshold Voltage of VP-VN
to Turn On SR MOS 2
2.2
2.2
2.1
2.1
VLPC-EN2 (V)
VLPC-EN1 (V)
4.0
2.0
1.9
2.0
1.9
1.8
1.8
-40
-25
-10
5
20
35
50
65
80
95
110
125
-40
-25
-10
5
20
35
50
65
80
95
110
125
Temperature℃
Temperature℃
Figure 23. LPC Enable Threshold Voltage 1
Figure 24.LPC Enable Threshold Voltage 2
0.4
VLPC-CLAMP2 (V)
VLPC-CLAMP1 (V)
0.4
0.3
0.2
0.1
0.2
0.1
-40
-25
-10
5
20
35
50
65
80
95
110
125
-40
-25
-10
5
20
35
50
65
80
95
110
125
Temperature℃
Temperature℃
Figure 25. Lower Clamp Voltage 1
Figure 26.Lower Clamp Voltage 2
300
300
275
275
ILPC-SOURCE2 (V)
ILPC-SOURCE1 (uA)
0.3
250
225
200
250
225
200
-40
-25
-10
5
20
35
50
65
80
95
110
125
-40
Temperature℃
-10
5
20
35
50
65
80
95
110
125
Temperature℃
Figure 27. Maximum Source Current 1
© 2010 Fairchild Semiconductor Corporation
FAN6206 • Rev. 1.0.2
-25
Figure 28.Maximum Source Current 2
FAN6206 — Highly Integrated Dual-Channel Synchronous Rectification Controller for Dual-Forward Converter
Typical Performance Characteristics
www.fairchildsemi.com
9
Figure 31 shows a typical application circuit. When a
dual-forward converter operates in continuous
conduction mode, the SR gate signals (GATE1 and
GATE2) are mainly controlled by SP and SN signals. SP
and SN signals are transferred through a pulse
transformer from XP and XN signals, which are
generated by FAN6210 (Primary-Side Synchronous
Rectifier Signal Trigger for Dual Forward Converter).
Figure 29 and Figure 30 show the simplified circuit
diagram of a dual-forward converter and its key
waveforms. Switches Q1 and Q2 are turned on and off
together. Once Q1 and Q2 are turned on, input voltage is
applied across the transformer primary side and power
is delivered to the secondary side through the
transformer, powering D1. During this time, the
magnetizing current linearly increases. When Q1 and Q2
are turned off, the magnetizing current of the
transformer forces the reset diodes (DR1 and DR2) and
negative input voltage is applied across the transformer
primary side. During this time, magnetizing current
linearly decreases to zero and the secondary-side
inductor current freewheels through diode D2. When
synchronous rectifier SR1 and SR2 are used instead of
diodes D1 and D2, it is important to have proper timing
between drive signals for SR1 and SR2.
Figure 31. Typical Application Circuit
Figure 32 shows the timing diagram for continuous
conduction mode (CCM). Figure 33 shows the timing
diagram for discontinuous conduction mode (DCM).
The switching operation of SR MOSFETs Q3 and Q4 is
determined by the SN and SP signals. FAN6206 turns
on SR MOSFETs at the rising edge of the SP signal,
while it turns off the SR MOSFETs at the rising edge of
the SN signal. Within one switching cycle, SP and SN
are obtained two times.
Figure 29. Simplified Circuit Diagram of
Dual-Forward Converter
With a voltage divider R1 and R2 connected from LPC1
to secondary winding, R3 and R4 connected from LPC2
to secondary winding, the PWM timing sequences and
frequency can be tracked precisely. The SR MOSFET is
turned on by SP signal only when the voltage level on
LPC1 or LPC2 pin is pulled LOW to GND.
During PWM-on period, the rectifying SR Q3 is turned on
by the rising edge of the SP signal after a propagation
delay (tPD-HIGH-SP1) and Q3 is turned off by the rising edge
of the SN signal after a propagation delay (tPD-LOW-SN1).
During PWM-off period, the freewheeling SR Q4 is
turned on by the rising edge of the SP signal after a
propagation delay (tPD-HIGH-SP2) and Q4 is turned off by
the rising edge of the SN signal after a propagation
delay (tPD-LOW-SN2) in CCM operation.
In DCM operation, the proprietary Linear-Predict Timing
Control (LPC) technique can provide synchronous
rectification control mechanism for freewheeling SR
MOSFET. Since SN signal is sent following with PWM
signal, the freewheeling SR MOSFET cannot be turned
off in time by SN signal before ILo linearly decreases to
zero. Therefore, the LPC mechanism is applied to turn
off Q3 in DCM mode.
Figure 30. Key Waveforms of Dual-Forward
Converter
© 2010 Fairchild Semiconductor Corporation
FAN6206 • Rev. 1.0.2
FAN6206 — Highly Integrated Dual-Channel Synchronous Rectification Controller for Dual-Forward Converter
Function Description
www.fairchildsemi.com
10
FAN6206 — Highly Integrated Dual-Channel Synchronous Rectification Controller for Dual-Forward Converter
Figure 32. SR Gate is Driven by SP & SN Signal in CCM Mode
Figure 33. Freewheeling SR Turned Off by LPC Mechanism in DCM Mode
© 2010 Fairchild Semiconductor Corporation
FAN6206 • Rev. 1.0.2
www.fairchildsemi.com
11
Under-Voltage Lockout (UVLO)
When a dual-forward converter operates in CCM or
DCM; in PWM tON period, the VIN voltage is applied to
the primary winding and the secondary inductor starts to
rise linearly and store energy. The across voltage on
secondary winding is coupled from primary winding and
proportional to VIN. The SR controller can detect this
winding voltage through a voltage divider and acquire
the VIN level. According to this detected VIN level during
PWM turn-on period, SR controller produces a charge
current ICHG to charge internal capacitor, CT, of the SR
controller. On the other hand, at PWM turn-off period,
the energy stored in the secondary inductor is
discharged. The SR controller also detects the output
voltage level to modulate discharge current IDISCHG of
internal capacitor, CT. Once the internal capacitor
voltage reaches zero, SR controller turns off SR MOS
immediately.
The power-on and off thresholds are fixed at 8.5V and
7.5V. The VDD pin is connected to a 12V output voltage
terminal.
VDD Pin Over-Voltage Protection
The over-voltage conditions are usually caused by open
feedback loops. VDD over-voltage protection is built in to
prevent damage if over voltage occurs. When the
voltage on the VDD pin exceeds 21V, the SR controller
turns off all of SR MOS operations.
R4 is connected between the LPC2 pin and the drain
terminal of Q4. During PWM turn-on period, voltage on
the LPC2 pin is pulled HIGH due to the secondary
winding coupled from primary winding. At this moment,
SR MOS is turned off and the internal body diode of SR
MOS is reverse-biased. During PWM turn-off period, the
potential on the primary winding reverses and the
internal body diode starts to conduct output current. The
voltage on the LPC2 pin is also pulled LOW to GND. R2
is recommended as 10kΩ and the divided voltage level
on the LPC1 pin is suggested between 3V~5V. If the
voltage level of VO is 12V, the resistor values are
recommended as 105kΩ for R3 and 10kΩ for R4. The
R4
turn-off timing of Q4 is determined by the ratio
R3 + R 4
as Figure 34 shows. If
R4
decreases, Q4 is turned
R3 + R 4
off earlier.
Figure 34. Turn-Off Timing of Freewheeling SR
© 2010 Fairchild Semiconductor Corporation
FAN6206 • Rev. 1.0.2
FAN6206 — Highly Integrated Dual-Channel Synchronous Rectification Controller for Dual-Forward Converter
Linear-Predict Timing Control
www.fairchildsemi.com
12
Application
Fairchild Devices
Input Voltage Range
Output
90~264VAC
12V/25A
FAN4801
PC Power
FAN6210
FAN6206
Figure 35. Application Circuit
© 2010 Fairchild Semiconductor Corporation
FAN6206 • Rev. 1.0.2
FAN6206 — Highly Integrated Dual-Channel Synchronous Rectification Controller for Dual-Forward Converter
Typical Application Circuit (Dual-Forward Converter with SR)
www.fairchildsemi.com
13
5.00
4.80
A
0.65
3.81
5
8
B
6.20
5.80
PIN ONE
INDICATOR
1.75
4.00
3.80
1
5.60
4
1.27
(0.33)
0.25
M
1.27
C B A
LAND PATTERN RECOMMENDATION
0.25
0.10
SEE DETAIL A
1.75 MAX
0.25
0.19
C
0.10
0.51
0.33
0.50 x 45°
0.25
R0.10
C
OPTION A - BEVEL EDGE
GAGE PLANE
R0.10
OPTION B - NO BEVEL EDGE
0.36
NOTES: UNLESS OTHERWISE SPECIFIED
8°
0°
0.90
0.406
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AA, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) LANDPATTERN STANDARD: SOIC127P600X175-8M.
E) DRAWING FILENAME: M08AREV13
SEATING PLANE
(1.04)
DETAIL A
SCALE: 2:1
Figure 36. 8-Pin Small Outline Package (SOP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2010 Fairchild Semiconductor Corporation
FAN6206 • Rev. 1.0.2
FAN6206 — Highly Integrated Dual-Channel Synchronous Rectification Controller for Dual-Forward Converter
Physical Dimensions
www.fairchildsemi.com
14
FAN6206 — Highly Integrated Dual-Channel Synchronous Rectification Controller for Dual-Forward Converter
15
www.fairchildsemi.com
© 2010 Fairchild Semiconductor Corporation
FAN6206 • Rev. 1.0.2