Preliminary Datasheet R2A20118ASP Critical Conduction Mode Interleaved PFC Control IC R03DS0002EJ0100 Rev.1.00 Jul 14, 2010 Description The R2A20118A controls a boost converter to provide an active power factor correction. The R2A20118A is based on R2A20117, and additional functions are OVP2 and Brownout. The R2A20118A adopts critical conduction mode for power factor correction and realizes high efficiency and a low switching noise by zero current switching. Interleaving function improves ripple current on input or output capacitor by 180 degrees phase shift. The feedback loop short detection, two modes overvoltage protection and OVP2, overcurrent protection, overcurrent timer latch protection, and ZCD open detection are built in the R2A20118A, and can constitute a power supply system of high reliability with few external parts. Features Absolute Maximum Ratings Supply voltage Vcc: 24 V Operating junction temperature Tjopr: –40 to +150°C Electrical Characteristics VREF output voltage VREF: 5.0 V 1.5% UVLO operation start voltage Vuvlh: 10.5 V 0.7 V UVLO operation shutdown voltage Vuvll: 9.3 V 0.5 V UVLO hysteresis voltage Hysuvl: 1.2 V 0.5 V Functions Boost converter control with critical conduction mode Interleaving control Brownout function Two mode overvoltage protection and OVP2 Mode1: Dynamic OVP corresponding to a voltage rise by dynamic load change Mode2: Static OVP corresponding to overvoltage in stable. OVP2: OVP2 sense the PFC output voltage by independenced pin. Feedback loop short detection Slave ZCD signal open detection RAMP charge current selectable function Master and Slave independenced overcurrent protection Overcurrent timer latch protection at abnormal operation 280 s restart timer Soft start function for the reference voltage of Error Amp Package: Pb-free SOP-20 Ordering Information Part No. R2A20118ASPW0 Package Name FP-20DAV R03DS0002EJ0100 Rev.1.00 Jul 14, 2010 Package Code PRSP0020DD-B Package Abbreviation SP Taping Abbreviation (Quantity) W (2,000 pcs/reel) Page 1 of 9 R2A20118ASP Preliminary Pin Arrangement ZCD-M 1 20 VCC ZCD-S 2 19 GD-M BO 3 18 GND VREF 4 17 GD-S SS 5 16 OCP-M NC 6 15 OCP-S RT 7 14 NC RAMP 8 13 TL RAMP-GAIN 9 12 OVP2 10 11 FB COMP (Top view) Pin Functions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pin Name ZCD-M ZCD-S BO VREF SS NC RT RAMP RAMP-GAIN COMP FB OVP2 TL NC OCP-S OCP-M GD-S GND GD-M VCC Input/Output Input Input Input Output Output — Input/Output Input/Output Input Output Input Input Output — Input Input Output — Output Input R03DS0002EJ0100 Rev.1.00 Jul 14, 2010 Function Master converter zero current detection input terminal Slave converter zero current detection input terminal Brownout input terminal Reference voltage output terminal Soft start time setting terminal Open terminal Oscillator frequency setting terminal Ramp waveform setting terminal RAMP charge current selection terminal Error amplifier output terminal Error amplifier input terminal Over voltage detection terminal Timer latch time setting terminal Open terminal Slave converter overcurrent detection terminal Master converter overcurrent detection terminal Slave converter Power MOSFET drive terminal Ground Master converter Power MOSFET drive terminal Supply voltage terminal Page 2 of 9 R2A20118ASP Preliminary Block Diagram 10 μA 10 μA VREF VCC VREF: 5 V ZCD COMP1 ZCD-M –0.1 V ~ 4.5 V Vzcd_lo = 1.3 V 250 mVhys TL ZCD COMP2 –0.1 V ~ 4.5 V 3.2 μA TL COMP + – 3.2 V – GD-S + VREF LATCH Stop GD S Q 6.4 μA GD-M + Clamp VREF ON: 10.5 V OFF: 9.3 V – Clamp ZCD-S UVLO 5 μA OCP COMP1 OCP-M + Logic – R Vcc reset 5 μA OCP-S OCP COMP2 + – Hi: ON OCP-S VREF 0.3 V Stop GD (BOUT) + – 1.4 V BO GD Disable OVP BLOCK Ibo, Iramp Tstart Vac_lo = 3.2 V 390 mVhys SW COMP + FB ErrorAmp + – – + 2.5 V VREF 10 μA RAMP AMP + – VREF 80 μA FB – Hi: ON RT OVP2 OVP2 COMP Discharge 7.5 μA RAMP-GAIN OCP-M VREF 2.275 V (design spec) 0 to 240 μA 10 μA SS UVL BOUT FBLOW Hi: ON RAMP Iramp Hi: ON 0.9 V GND (design spec) COMP 4.3 V R03DS0002EJ0100 Rev.1.00 Jul 14, 2010 Page 3 of 9 R2A20118ASP Preliminary Absolute Maximum Ratings (Ta = 25°C) Item Symbol Supply voltage GD terminal peak current VCC Ipk-gd GD terminal DC current Idc-gd ZCD terminal current Izcd BO terminal current RT terminal current Vref terminal current Vref terminal capacitor Vref terminal voltage OCP terminal voltage Ibom Irt Iref Cref min Cref max Icomp Vt-group1 Vt-group2 Vt-ref Vt-ocp Power dissipation Operating junction temperature Storage temperature Pt Tj-opr Tstg COMP terminal current Terminal voltage Ratings –0.3 to 24 Unit V Notes –300 +1200 mA 3 –15 +60 mA +3 –3 200 –200 –5 1000 1 1 –0.3 to Vcc –0.3 to Vref –0.3 to Vref + 0.3 *–1 to Vref mA 1 –40 to +150 –55 to +150 W °C °C A A mA pF F mA V V V V 4 5 6 7 Notes: 1. 2. 3. 4. Rated voltages are with reference to the GND terminal. For rated currents, inflow to the IC is indicated by (+), and outflow by (–). Shows the transient current when driving a capacitive load. This is the rated voltage for the following pins: NC 5. This is the rated voltage for the following pins: FB, OVP2, RT, TL, RAMP-GAIN, SS, RAMP 6. Minus value is peak voltage. Do not impress the DC voltage of the minus. 7. ja = 120°C/W This value is a thing mounting on 40 40 (thickness: 1.6 mm) [mm2], a glass epoxy board of wiring density 10%. R03DS0002EJ0100 Rev.1.00 Jul 14, 2010 Page 4 of 9 R2A20118ASP Preliminary Electrical Characteristics (Ta = 25°C, VCC = 12 V, RT = 33 k, BO = 5 V, OCP = TL = OVP2 = GND, CRAMP = 820 pF, FB = COMP, RAMP-GAIN = OPEN) Item Supply Brownout VREF Error amplifier Symbol Min Typ Max Unit Test Conditions UVLO turn-on threshold Vuvlh 9.8 10.5 11.2 V UVLO turn-off threshold Vuvll 8.8 9.3 9.8 V UVLO hysteresis Hysuvl 0.7 1.2 1.7 V Standby current Istby — 85 170 A VCC = 8.9 V Operating current Icc — 4.2 6.3 mA FB: Open BO threshold voltage Vbo 1.33 1.40 1.47 V BO pin hysteresis current Ibo 6.7 7.5 8.3 A BO = 1 V Output voltage Vref 4.925 5.00 5.075 V Isource = –1 mA Line regulation Vref-line — 5 20 mV Isource = –1 mA Vcc = 10 V to 24 V Load regulation Vref-load — 5 20 mV Isource = –1 mA to –5 mA Temperature stability dVref — 80 — ppm/°C Feedback voltage Vfb 2.452 2.49 2.528 V FB-COMP short Input bias current Ifb –0.5 –0.3 –0.1 A Measured pin: FB 1 FB = 3 V * Open loop gain Av — 60 — dB * Upper clamp voltage Vclamp-comp 4.0 4.3 — V FB = 2.0 V COMP: Open Low voltage Vl-comp — 0.1 0.3 V FB = 3.0 V Source current Isrc-comp — –120 — A FB = 1.5 V Ta = –40 to 125°C * 1 1 COMP: Open COMP = 2.5 V — 330 — A FB = 3.5 V gm 120 200 290 s FB = 2.45V 2.55 V RAMP charge current 1 Ic-ramp1 72 80 88 A RAMP = 0 V to 3 V RAMP-GAIN = GND RAMP charge current 2 Ic-ramp2 288 320 352 A RAMP = 0 V to 3 V RAMP discharge current Id-ramp 7 15 29 mA FB = 3 V RAMP = 1 V Low voltage Vl-ramp — 17 200 mV FB = 3 V Isink = 100 A RAMP Threshold voltage Vth-ramp_gain 1.5 2.5 3.5 V gain control Input bias current Iramp_gain –14 –10 –6 A RAMP-GAIN = 3.5 V AC detect low threshold voltage Vac-lo 2.9 3.2 3.5 V Measured pin BO AC detect hysteresis Hys-ac 350 390 430 mV Measured pin BO Sink current Isnk-comp Transconductance COMP = 2.5 V COMP = 2.5 V RAMP Note: Measured pin RAMP-GAIN *1 Design spec. R03DS0002EJ0100 Rev.1.00 Jul 14, 2010 Page 5 of 9 R2A20118ASP Preliminary Electrical Characteristics (cont.) (Ta = 25°C, VCC = 12 V, RT = 33 k, BO = 5 V, OCP = TL = OVP2 = GND, CRAMP = 820 pF, FB = COMP, RAMP-GAIN = OPEN) Item Symbol Min Typ Max Unit Test Conditions 1, Slave control Phase delay Phase 160 180 200 deg * * 2 On time ratio Ton-ratio 0 — 5 % * * 1, 2 Gate drive Master gate drive rise time tr-gdm — 20 100 ns CL = 100 pF 90% 10% Slave gate drive rise time tr-gds — 20 100 ns CL = 100 pF tr 90% 10% Master gate drive fall time tf-gdm — 5 30 ns CL = 100 pF tr 90% tf Slave gate drive fall time tf-gds — 5 30 ns CL = 100 pF 90% tf Master gate drive low voltage Vol1-gdm Vol2-gdm Master gate drive high voltage Voh-gdm Slave gate drive low voltage Vol1-gds — Vol2-gds Slave gate drive high voltage Voh-gds OCP threshold voltage Vocp Over Dynamic OVP threshold voltage voltage protection Over — V 10% 10% 0.02 0.1 Isink = 2 mA — 0.01 0.2 V Isink = 1 mA, VCC = 5 V 11.5 11.9 — V Isource = –2 mA * 0.02 0.1 V Isink = 2 mA — 0.01 0.2 V Isink = 1 mA, VCC = 5 V 11.5 11.9 — V Isource = –2 mA * 0.27 0.30 0.33 V Vdovp VFB 1.035 VFB 1.050 VFB 1.065 V COMP = 2.5 V Static OVP threshold voltage Vsovp1 VFB 1.075 VFB 1.090 VFB 1.105 V COMP = 2.5 V Static OVP hysteresis Hys-sovp1 50 100 150 mV COMP = 2.5 V FB Low detect threshold voltage Vfblow 0.45 0.50 0.55 V COMP = 2.5 V FB Low detect hysteresis Hysfblow 0.16 0.20 0.24 V COMP = 2.5 V OVP2 threshold voltage Vovp2 2.670 2.725 2.780 V Measured pin: OVP2 OVP2 pin input bias current Iovp2 –0.5 –0.3 –0.1 A Measured pin: OVP2 1 OVP2 = 3 V * 1 1 current protection Notes: *1 Design spec. *2 Tperiod (25 μs) Ton-m (17 μs) GD-M Tdelay Ton-s GD-S Phase = Tdelay × 360 [deg] Tperiod Ton-ratio = 1 – Ton-s × 100 [%] Ton-m R03DS0002EJ0100 Rev.1.00 Jul 14, 2010 Page 6 of 9 R2A20118ASP Preliminary Electrical Characteristics (cont.) (Ta = 25°C, VCC = 12 V, RT = 33 k, BO = 5 V, OCP = TL = OVP2 = GND, CRAMP = 820 pF, FB = COMP, RAMP-GAIN = OPEN) Item Symbol Min Typ Max Unit Test Conditions Zero Upper clamp voltage Vzcdh 4.0 4.5 5.0 V Isource = –3 mA current detector Lower clamp voltage Vzcdl –0.5 –0.1 0.4 V Isink = 3 mA ZCD low threshold voltage Vzcd-lo 0.9 1.3 1.6 V * 1 ZCD hysteresis Hyszcd 130 250 360 mV * 1 Input bias current Izcd –14 –10 –6 A 1.2 V < Vzcd < 2.5 V Slave ZCD open detect delay time tzcds — 100 — ms ZCD-S: Open 1 Gate drive 10 kHz * ZCD open detector Soft start Charge current Ic-ss –14 –10 –6 A SS = 2 V Timer latch Charge current Ic-tl –4.8 –3.2 –1.2 A for overcurrent TL = 2 V OCP-M = 0.5 V Discharge current Id-tl 1.2 3.2 4.8 A TL = 2 V Threshold voltage Vtl 2.88 3.2 3.52 V Restart time delay Tstart 210 280 350 s Restart ZCD-M = 10 k ZCD-S = 10 k * 2 Notes: *1 Design spec. *2 Tstart (280 μs) [A period without ZCD-M trigger] ZCD-M Vzcd-lo (1.3 V: provide 250 mV hysteresis) GD-M Restart pulse width: 1 μs (Design spec) R03DS0002EJ0100 Rev.1.00 Jul 14, 2010 Page 7 of 9 R2A20118ASP Preliminary System Diagram T1 230 μ 2μ D1 PFC OUT (390 Vdc, 300 W) 470 μ (450 V) Q1 From GD-M T2 230 μ 3M 3M VRB1 VRB2 + 0.04 GND D2 Q2 From GD-S 47 k 0.04 47 k AUX VCC 1μ ZCD-M GD-M To Q1 gate ZCD-S GD-S TL To Q2 gate OCP-M 0.1 μ 200 1000 p OCP-S 200 1000 p VREF 3M OVP2 0.1 μ BO 2.2 μ R2A20118ASP 68 k RT FB 33 k RAMP-GAIN SS RAMP 1μ GND 470 p COMP 1μ 820 k 0.1 μ 51 k R03DS0002EJ0100 Rev.1.00 Jul 14, 2010 Page 8 of 9 R2A20118ASP Preliminary Package Dimensions JEITA Package Code P-SOP20-5.5x12.6-1.27 RENESAS Code PRSP0020DD-B *1 Previous Code FP-20DAV MASS[Typ.] 0.31g D NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. F 20 11 c HE *2 E bp Index mark Terminal cross section ( Ni/Pd/Au plating ) 10 1 Z e *3 bp x Reference Dimension in Millimeters Symbol M A L1 A1 θ y L Detail F R03DS0002EJ0100 Rev.1.00 Jul 14, 2010 D E A2 A1 A bp b1 c c1 θ HE e x y Z L L1 Min Nom Max 12.60 13.0 5.50 0.00 0.10 0.20 2.20 0.34 0.40 0.46 0.15 0.20 0.25 0° 8° 7.50 7.80 8.00 1.27 0.12 0.15 0.80 0.50 0.70 0.90 1.15 Page 9 of 9 Notice 1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. 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