ICS87973I-147 LOW SKEW, 1-TO-12 LVCMOS/LVTTL CLOCK MULTIPLIER/ ZERO DELAY BUFFER General Description The ICS87973I-147 is a highly flexible device. The three selectable inputs (1 differential and 2 single ended inputs) are often used in systems requiring redundant clock sources. Up to three different output frequencies can be generated among the three output banks. The three output banks and feedback output each have their own output dividers which allows the device to generate a multitude of different bank frequency ratios and output-to-input frequency ratios. In addition, 2 outputs in Bank C (QC2, QC3) can be selected to be inverting or non-inverting. The output frequency range is 10MHz to 150MHz. The input frequency range is 6MHz to 120MHz. The ICS87973I-147 also has a QSYNC output which can be used for system synchronization purposes. It monitors Bank A and Bank C outputs and goes low one period prior to coincident rising edges of Bank A and Bank C clocks. QSYNC then goes high again when the coincident rising edges of Bank A and Bank C occur. This feature is used primarily in applications where Bank A and Bank C are running at different frequencies, and is particularly useful when they are running at non-integer multiples of one another. • • Fully integrated PLL • Selectable differential CLK, nCLK inputs or LVCMOS/LVTTL reference clock inputs • CLK0, CLK1 can accept the following input levels: LVCMOS or LVTTL • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • • • • • • • • Output frequency range: 10MHz to 150MHz Fourteen LVCMOS/LVTTL outputs to include: twelve clocks, one feedback, one sync VCO range: 240MHz to 500MHz Output skew: 200ps (maximum) Cycle-to-cycle jitter, (all banks ÷4): 55ps (maximum) Full 3.3V supply voltage -40°C to 85°C ambient operating temperature Compatible with PowerPC™and Pentium™Microprocessors Available in both standard (RoHS 5) and lead-free (RoHS 6) packages Example Applications: 1.System Clock generator: Use a 16.66MHz reference clock to generate eight 33.33MHz copies for PCI and four 100MHz copies for the CPU or PCI-X. FSEL_FB0 GNDO QB0 VDDO QB1 GNDO QB2 VDDO QB3 EXT_FB GNDO QFB VDD Pin Assignment 39 38 37 36 35 34 33 32 31 30 29 28 27 FSEL_A1 FSEL_A0 QA3 VDDO QA2 GNDO QA1 VDDO QA0 42 43 44 45 46 47 48 49 50 GNDO VCO_SEL 51 52 26 25 24 23 22 21 20 19 18 17 16 15 14 1 2 3 4 5 6 7 8 9 10 11 12 13 FSEL_FB1 QSYNC GNDO QC0 VDDO QC1 FSEL_C0 FSEL_C1 QC2 VDDO QC3 GNDO INV_CLK VDDA 3.Zero Delay buffer for Synchronous memory: Fanout up to twelve 100MHz copies from a memory controller reference clock to the memory chips on a memory module with zero delay. 40 41 FRZ_DATA FSEL_FB2 PLL_SEL REF_SEL CLK_SEL CLK0 CLK1 CLK nCLK 2.Line Card Multiplier: Multiply differential 62.5MHz from a back plane to single-ended 125MHz for the line Card ASICs and Gigabit Ethernet Serdes. FSEL_B1 FSEL_B0 GNDI HiPerClockS™ The ICS87973I-147 is a LVCMOS/LVTTL clock generator and a member of the HiPerClockS™family of High Performance Clock Solutions from IDT. The ICS87973I-147 has three selectable inputs and provides 14 LVCMOS/LVTTL outputs. nMR/OE FRZ_CLK ICS Features ICS87973I-147 52-Lead LQFP 10mm x 10mm x 1.4mm package body Y Package Top View IDT™ / ICS™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER 1 ICS87973DYI-147 REV. A DECEMBER 9, 2008 ICS87973I-147 LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER Block Diagram VCO_SEL Pullup PLL_SEL Pullup REF_SEL Pullup CLK Pullup nCLK SYNC FRZ QA0 CLK1 Pullup SYNC FRZ QA1 CLK_SEL Pullup SYNC FRZ QA2 EXT_FB Pullup SYNC FRZ QA3 SYNC FRZ QB0 SYNC FRZ QB1 SYNC FRZ QB2 SYNC FRZ QB3 CLK0 Pullup FSEL_FB2 nMR/OE Pullup QC0 FSEL_A[0:1] Pullup 2 Pullup 2 FSEL_C[0:1] Pullup 2 FSEL_FB[0:2] Pullup 3 FSEL_B[0:1] SYNC FRZ QC1 SYNC FRZ QC2 SYNC FRZ QC3 QFB SYNC FRZ QSYNC FRZ_CLK Pullup FRZ_DATA Pullup INV_CLK Pullup IDT™ / ICS™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER 2 ICS87973DYI-147 REV. A DECEMBER 9, 2008 ICS87973I-147 LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER Simplified Block Diagram nMR/OE CLK Pullup nCLK CLK0 Pullup CLK1 Pullup CLK_SEL Pullup REF_SEL Pullup EXT_FB Pullup FSEL_A[0:1] 1 0 0 2 FSEL_ A1 A0 0 0 0 1 1 0 1 1 PLL 1 VCO RANGE 240MHz - 500MHz 0 ÷2 0 1 ÷1 QAx ÷4 ÷6 ÷8 ÷12 SYNC FRZ QA0 SYNC FRZ QA1 SYNC FRZ QA2 SYNC FRZ QA3 SYNC FRZ QB0 SYNC FRZ QB1 SYNC FRZ QB2 SYNC FRZ QB3 FSEL_B[0:1] 2 1 FSEL_ B1 B0 0 0 0 1 1 0 1 1 VCO_SEL Pullup PLL_SEL Pullup QBx ÷4 ÷6 ÷8 ÷10 FSEL_C[0:1] 2 FSEL_ C1 C0 0 0 0 1 1 0 1 1 QC0 QCx ÷2 ÷4 ÷6 ÷8 0 1 INV_CLK SYNC FRZ QC1 SYNC FRZ QC2 SYNC FRZ QC3 Pullup FSEL_FB[0:2] 3 FSEL_ FB2 FB1 FB0 QFB 0 0 0 ÷4 0 0 1 ÷6 0 1 0 ÷8 0 1 1 ÷10 1 0 0 ÷8 1 0 1 ÷12 1 1 0 ÷16 1 1 1 ÷20 FRZ_CLK Pullup FRZ_DATA Pullup IDT™ / ICS™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER 3 OUTPUT DISABLE CIRCUITRY QFB SYNC FRZ QSYNC ICS87973DYI-147 REV. A DECEMBER 9, 2008 ICS87973I-147 LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER Table 1. Pin Descriptions Number Name Type Description 1 GNDI Power 2 nMR/OE Input Pullup Master reset and output enable. When HIGH, enables the outputs. When LOW, resets the outputs in a high-impedance state and resets output divide circuitry. Enables and disables all outputs. LVCMOS / LVTTL interface levels. 3 FRZ_CLK Input Pullup Clock input for freeze circuitry. LVCMOS / LVTTL interface levels. Power supply ground. 4 FRZ_DATA Input Pullup Configuration data input for freeze circuitry. LVCMOS / LVTTL interface levels. 5, 26, 27 FSEL_FB2, FSEL_FB1, FSEL_FB0 Input Pullup Select pins control Feedback Divide value. LVCMOS / LVTTL interface levels. See Table 3B. 6 PLL_SEL Input Pullup Selects between the PLL and reference clocks as the input to the output dividers. When HIGH, selects PLL. When LOW, bypasses the PLL and reference clocks. LVCMOS / LVTTL interface levels. 7 REF_SEL Input Pullup Selects between CLK0 or CLK1 and CLK, nCLK inputs. When LOW, selects CLK0 or CLK1. When HIGH, CLK, nCLK inputs. LVCMOS / LVTTL interface levels. 8 CLK_SEL Input Pullup Clock select input. When LOW, selects CLK0. When HIGH, selects CLK1. LVCMOS / LVTTL interface levels. 9, 10 CLK0, CLK1 Input Pullup Single-ended reference clock inputs. LVCMOS/LVTTL interface levels. 11 CLK Input Pullup Non-inverting differential clock input. 12 nCLK Input Inverting differential clock input. VDD/2 default when left floating. 13 VDDA Power Analog supply pin. 14 INV_CLK Input 15, 24, 30, 35, 39, 47, 51 GNDO Power Power supply ground. 16, 18, 21, 23 QC3, QC2, QC1, QC0 Output Single-ended Bank C clock outputs. LVCMOS/ LVTTL interface levels. 17, 22, 33, 37, 45, 49 VDDO Power Output power supply pins. 19, 20 FSEL_C1, FSEL_C0 Input 25 QYSNC Output Synchronization output for Bank A and Bank C. Refer to Figure 1, Timing Diagrams. LVCMOS / LVTTL interface levels. 28 VDD Power Power supply pin. 29 QFB Output 31 EXT_FB Input 32, 34, 36, 38 QB3, QB2, QB1, QB0 Output 40, 41 FSEL_B1, FSEL_B0 Input Pullup Select pins for Bank B outputs. LVCMOS / LVTTL interface levels. See Table 3A. 42, 43 FSEL_A1, FSEL_A0 Input Pullup Select pins for Bank A outputs. LVCMOS / LVTTL interface levels. See Table 3A. 44, 46 48, 50 QA3, QA2, QA1, QA0 Output 52 VCO_SEL Input Pullup Pullup Inverted clock select for QC2 and QC3 outputs. LVCMOS / LVTTL interface levels. Select pins for Bank C outputs. LVCMOS / LVTTL interface levels. See Table 3A. Single-ended feedback clock output. LVCMOS / LVTTL interface levels. Pullup External feedback. LVCMOS / LVTTL interface levels. Single-ended Bank B clock outputs. LVCMOS/ LVTTL interface levels. Single-ended Bank A clock outputs. LVCMOS/ LVTTL interface levels. Pullup Selects VCO. When HIGH, selects VCO ÷ 1. When LOW, selects VCO ÷ 2. LVCMOS / LVTTL interface levels. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. IDT™ / ICS™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER 4 ICS87973DYI-147 REV. A DECEMBER 9, 2008 ICS87973I-147 LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ CPD Power Dissipation Capacitance (per output) ROUT Output Impedance VDD, VDDA, VDDO = 3.465V 5 7 Units 18 pF 12 Ω Function Tables Table 3A. Output Bank Configuration Select Function Table Inputs Outputs Inputs Outputs Inputs Outputs FSEL_A1 FSEL_A0 QA FSEL_B1 FSEL_B0 QB FSEL_C1 FSEL_C0 QC 0 0 ÷4 0 0 ÷4 0 0 ÷2 0 1 ÷6 0 1 ÷6 0 1 ÷4 1 0 ÷8 1 0 ÷8 1 0 ÷6 1 1 ÷12 1 1 ÷10 1 1 ÷8 Table 3B. Feedback Configuration Select Function Table Inputs Outputs FSEL_FB2 FSEL_FB1 FSEL_FB0 QFB 0 0 0 ÷4 0 0 1 ÷6 0 1 0 ÷8 0 1 1 ÷10 1 0 0 ÷8 1 0 1 ÷12 1 1 0 ÷16 1 1 1 ÷20 Table 3C. Control Input Select Function Table Control Pin Logic 0 Logic 1 VCO_SEL VCO/2 VCO REF_SEL CLK0 or CLK1 XTAL CLK_SEL CLK0 CLK1 PLL_SEL BYPASS PLL Enable PLL nMR/OE Master Reset/Output High-Impedance Enable Outputs INV_CLK Non-Inverted QC2, QC3 Inverted QC2, QC3 IDT™ / ICS™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER 5 ICS87973DYI-147 REV. A DECEMBER 9, 2008 ICS87973I-147 LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER fVCO 1:1 Mode QA QC QSYNC 2:1 Mode QA QC QSYNC 3:1 Mode QC(÷2) QA(÷4) QSYNC 3:2 Mode QC(÷2) QA(÷8) QSYNC 4:1 Mode QC(÷2) QA(÷8) QSYNC 4:3 Mode QA(÷6) QC(÷8) QSYNC 6:1 Mode QA(÷12) QC(÷2) QSYNC Figure 1. Timing Diagrams IDT™ / ICS™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER 6 ICS87973DYI-147 REV. A DECEMBER 9, 2008 ICS87973I-147 LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, θJA 42.3°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VDD = VDDA = VDDO = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter VDD Test Conditions Minimum Typical Maximum Units Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 225 mA IDDA Analog Supply Current 20 mA Table 4B. DC Characteristics, VDD = VDDA = VDDO = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter Test Conditions VIH Input High Voltage VIL Input Low Voltage IIN Input Current VOH Output High Voltage; NOTE 1 IOH = -20mA VOL Output Low Voltage; NOTE 1 IOL = 20mA VPP Peak-to-Peak Input Voltage; NOTE 2, 3 CLK, nCLK VCMRP Common Mode Input Voltage; NOTE 2, 3 CLK, nCLK Minimum Typical Maximum Units 2 VDD + 0.3 V -0.3 0.8 V ±120 µA 2.4 V 0.5 V 0.3 1 V VDD - 2 VDD - 0.6 V NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information section. Load Test Circuit diagram. NOTE 2: VIL should not be less than -0.3V. NOTE 3: Common mode input voltage is defined as VIH. IDT™ / ICS™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER 7 ICS87973DYI-147 REV. A DECEMBER 9, 2008 ICS87973I-147 LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER Table 5. Input Frequency Characteristics, VDD = VDDA = VDDO = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter FIN Input Frequency Test Conditions Minimum Typical Maximum Units CLK0, CLK1; NOTE 1 120 MHz FRZ_CLK 20 MHz NOTE 1: Input frequency depends on the feedback divide ratio to ensure "clock * feedback divide" is in the VCO range of 240MHz to 500MHz. AC Electrical Characteristics Table 6. AC Characteristics, VDD = VDDA = VDDO = 3.3V ± 5%, TA = -40°C to 85°C Symbol fMAX Parameter Test Conditions Output Frequency Maximum Units ÷2 150 MHz ÷4 125 MHz ÷6 83.33 MHz ÷8 62.5 MHz CLK0 t(Ø) Static Phase Offset; NOTE 1 tsk(o) Output Skew; NOTE 2, 3 tjit(cc) Cycle-to-Cycle Jitter; NOTE 3 fVCO PLL VCO Lock Range CLK1 QFB ÷ 8, In Frequency = 50MHz CLK, nCLK Minimum Typical -10 145 300 ps -65 90 245 ps -130 18 165 ps 200 ps 55 ps 240 500 MHz 10 ms 150 700 ps 45 55 % All Banks ÷ 4 tLOCK PLL Lock Time; NOTE 4 tR / tF Output Rise/Fall Time odc Output Duty Cycle tPZL, tPZH Output Enable Time; NOTE 4 10 ns tPLZL, tPHZ Output Disable Time; NOTE 4 8 ns 0.8V to 2V NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Defined as the time difference between the input reference clock and the average feedback input signal when the PLL is locked and the input reference frequency is stable. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: These parameters are guaranteed by characterization. Not tested in production. IDT™ / ICS™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER 8 ICS87973DYI-147 REV. A DECEMBER 9, 2008 ICS87973I-147 LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER Parameter Measurement Information 1.65V±5% VDD SCOPE VDD, VDDA, VDDO nCLK Qx V Cross Points PP LVCMOS V CMR CLK GND GND -1.65V±5% LVCMOS Output Load AC Test Circuit V V DDO V DDO 2 DDO 2 ➤ tcycle n ➤ QA[0:3], QB[0:3], QC[0:3], QSYNC, QFB Differential Input Level ➤ 2 tcycle n+1 Qx ➤ tjit(cc) = |tcycle n – tcycle n+1| 1000 Cycles Qy tsk(o) Cycle-to-Cycle Jitter Output Skew nCLK VDD CLK0, CLK1 VDD 2 2 nCLK VDD VDD 2 ➤ ➤ t(Ø) 2 EXT_FB ➤ t(Ø) t(Ø) mean = Static Phase Offset t(Ø) mean = Static Phase Offset Where t(Ø) is any random sample, and t(Ø) mean is the average of the sampled cycles measured on controlled edges Where t(Ø) is any random sample, and t(Ø) mean is the average of the sampled cycles measured on controlled edges LVCMOS Static Phase Offset IDT™ / ICS™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER ➤ EXT_FB Differential Static Phase Offset 9 ICS87973DYI-147 REV. A DECEMBER 9, 2008 ICS87973I-147 LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER Parameter Measurement Information, continued V DDO QA[0:3], QB[0:3], QC[0:3], QSYNC, QFB 2 QA[0:3], QB[0:3], QC[0:3], QSYNC, QFB t PW t odc = PERIOD t PW 2V 2V 0.8V 0.8V tR tF x 100% t PERIOD Output Duty Cycle/Pulse Width Period Output Rise/Fall Time Application Information Recommendations for Unused Input and Output Pins Inputs: Outputs: CLK/nCLK Inputs LVCMOS Outputs For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from CLK to ground. All unused LVCMOS output can be left floating. There should be no trace attached. CLK Inputs For applications not requiring the use of the clock input, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the CLK to ground. LVCMOS Control Pins All control pins have internal pull-ups; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. IDT™ / ICS™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER 10 ICS87973DYI-147 REV. A DECEMBER 9, 2008 ICS87973I-147 LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS87973I-147 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA and VDDO should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 2 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10Ω resistor along with a 10µF bypass capacitor be connected to the VDDA pin. 3.3V VDD .01µF 10Ω .01µF 10µF VDDA Figure 2. Power Supply Filtering Wiring the Differential Input to Accept Single Ended Levels Figure 3 shows how the differential input can be wired to accept single ended levels. The reference voltage V_BIAS = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_BIAS in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_BIAS should be 1.25V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input CLK V_Bias nCLK C1 0.1u R2 1K Figure 3. Single-Ended Signal Driving Differential Input IDT™ / ICS™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER 11 ICS87973DYI-147 REV. A DECEMBER 9, 2008 ICS87973I-147 LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER Differential Clock Input Interface The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both signals must meet the VPP and VCMR input requirements. Figures 4A to 4E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example, in Figure 4A, the input termination applies for IDT HiPerClockS open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50Ω Zo = 50Ω CLK CLK Zo = 50Ω nCLK Zo = 50Ω nCLK HiPerClockS Input LVHSTL R1 50 IDT HiPerClockS LVHSTL Driver HiPerClockS Input LVPECL R2 50 R1 50 R2 50 R2 50 Figure 4B. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVPECL Driver Figure 4A. HiPerClockS CLK/nCLK Input Driven by an IDT Open Emitter HiPerClockS LVHSTL Driver 3.3V 3.3V 3.3V R3 125 3.3V R4 125 3.3V Zo = 50Ω Zo = 50Ω CLK CLK R1 100 Zo = 50Ω nCLK HiPerClockS Input LVPECL R1 84 R2 84 Zo = 50Ω Figure 4D. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVDS Driver Figure 4C. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVPECL Driver 2.5V nCLK Receiver LVDS 3.3V *R3 33 Zo = 50Ω CLK Zo = 50Ω nCLK HCSL *R4 33 R1 50 R2 50 HiPerClockS Input *Optional – R3 and R4 can be 0Ω Figure 4E. HiPerClockS CLK/nCLK Input Driven by a 3.3V HCSL Driver IDT™ / ICS™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER 12 ICS87973DYI-147 REV. A DECEMBER 9, 2008 ICS87973I-147 LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER Using the Output Freeze Circuitry OVERVIEW each FRZ_DATA bit with the rising edge of the FRZ_CLK signal. To place an output in the freeze state, a logic “0” must be written to the respective freeze enable bit in the shift register. To unfreeze an output, a logic “1” must be written to the respective freeze enable bit. Outputs will not become enabled/disabled until all 12 data bits are shifted into the shift register. When all 12 data bits are shifted in the register, the next rising edge of FRZ_CLK will enable or disable the outputs. If the bit that is following the 12th bit in the register is a logic “0”, it is used for the start bit of the next cycle; otherwise, the device will wait and won’t start the next cycle until it sees a logic “0” bit. Freezing and unfreezing of the output clock is synchronous (see the timing diagram below). When going into a frozen state, the output clock will go LOW at the time it would normally go LOW, and the freeze logic will keep the output low until unfrozen. Likewise, when coming out of the frozen state, the output will go HIGH only when it would normally go HIGH. This logic, therefore, prevents runt pulses when going into and out of the frozen state. To enable low power states within a system, each output of ICS87973I-147 (Except QC0 and QFB) can be individually frozen (stopped in the logic “0” state) using a simple serial interface to a 12 bit shift register. A serial interface was chosen to eliminate the need for each output to have its own Output Enable pin, which would dramatically increase pin count and package cost. Common sources in a system that can be used to drive the ICS87973I-147 serial interface are FPGA’s and ASICs. PROTOCOL The Serial interface consists of two pins, FRZ_Data (Freeze Data) and FRZ_CLK (Freeze Clock). Each of the outputs which can be frozen has its own freeze enable bit in the 12 bit shift register. The sequence is started by supplying a logic “0” start bit followed by 12NRZ freeze enable bits. The period of each FRZ_DATA bit equals the period of the FRZ_CLK signal. The FRZ_DATA serial transmission should be timed so the ICS87973I-147 can sample FRZ_DATA rt Sta it B QA0 QA1 QA2 QA3 QB0 QB1 QB2 QB3 QC1 QC2 QC3 QSYNC FRZ_CLK FRZ Clocked FRZ Latched Figure 5A. Freeze Data Input Protocol Qx FREEZE Internal Qx Internal Qx Out Figure 5. Output Disable Timing Diagram IDT™ / ICS™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER 13 ICS87973DYI-147 REV. A DECEMBER 9, 2008 ICS87973I-147 LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER Schmatic Example Figure 6 shows a schematic example of using ICS87973I-147. This example shows general design of input, output termination, logic control input pull up/down and power supply filtering. In this example, the clock input is driven by an LVCMOS driver. R1 43 Zo = 50 U1 Serial Data VDD RS R9 1K R10 1K VCO_SEL GNDO QA0 VDDO QA1 GNDO QA2 VDDO QA3 FSEL_A0 FSEL_A1 FSEL_B0 FSEL_B1 VDD Serial Clcok 52 51 50 49 48 47 46 45 44 43 42 41 40 VDD R8 1K 1 2 3 4 5 6 7 8 9 10 11 12 13 Zo = 50 LVCMOS CLOCK GNDI nMR/OE FRZ_CLK FRZ_DATA FSEL_FB2 PLL_SEL REF_SEL CLK_SEL CLK0 CLK1 CLK nCLK VDDA C16 10u C11 0.01u R5 1K R6 1K ICS87973I-147 14 15 16 17 18 19 20 21 22 23 24 25 26 10 - 15 INV_CLK GNDO QC3 VDDO QC2 FSEL_C1 FSEL_C0 QC1 VDDO QC0 GNDO QSYNC FSEL_FB1 R7 VDD 39 38 37 36 35 34 33 32 31 30 29 28 27 GNDO QB0 VDDO QB1 GNDO QB2 VDDO QB3 EXT_FB GNDO QFB VDD FSEL_FB0 R2 Logic Input Pin Examples Set Logic Input to '1' VDD RU1 1K RU2 Not Install To Logic Input pins RD1 Not Install To Logic Input pins RD2 1K Zo = 50 R4 1K Set Logic Input to '0' VDD 43 R3 (U1-17) C3 0.1uF VDD (U1-22) C4 0.1uF (U1-28) C5 0.1uF (U1-33) C6 0.1uF (U1-37) C7 0.1uF 43 (U1-45) C8 0.1uF Zo = 50 (U1-49) C9 0.1uF VDD=3.3V ICS87973I-147 Schematic Layout IDT™ / ICS™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER 14 ICS87973DYI-147 REV. A DECEMBER 9, 2008 ICS87973I-147 LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER Reliability Information Table 7. θJA vs. Air Flow Table for a 52 Lead LQFP θJA by Velocity Linear Feet per Minute 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 58.0°C/W 47.1°C/W 42.0°C/W Multi-Layer PCB, JEDEC Standard Test Boards 42.3°C/W 36.4°C/W 34.0°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. Transistor Count The transistor count for ICS87973I-147: 8364 Pin Compatible with MPC973 IDT™ / ICS™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER 15 ICS87973DYI-147 REV. A DECEMBER 9, 2008 ICS87973I-147 LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER Package Outline and Package Dimensions Package Outline - Y Suffix for 52 Lead LQFP Table 8. Package Dimensions for 52 Lead LQFP JEDEC Variation: BCC All Dimensions in Millimeters Symbol Minimum Nominal Maximum N 52 A 1.60 A1 0.05 0.10 0.15 A2 1.35 1.40 1.45 b 0.22 0.38 c 0.09 0.20 D&E 12.00 Basic D1 & E1 10.00 Basic D2 & E2 7.80 Ref. e 0.65 Basic L 0.45 0.60 0.75 θ 0° 7° ccc 0.10 Reference Document: JEDEC Publication 95, MS-026 IDT™ / ICS™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER 16 ICS87973DYI-147 REV. A DECEMBER 9, 2008 ICS87973I-147 LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER Ordering Information Table 9. Ordering Information Part/Order Number 87973DYI-147 87973DYI-147T 87973DYI-147LF 87973DYI-147LFT Marking ICS7973DYI-147 ICS87973DYI-147 ICS87973DI147L ICS87973DI147L Package 52 Lead LQFP 52 Lead LQFP “Lead-Free” 52 Lead LQFP “Lead-Free” 52 Lead LQFP Shipping Packaging Tray 1000 Tape & Reel Tray 1000 Tape & Reel Temperature -40°C to 85°C -40°C to 85°C -40°C to 85°C -40°C to 85°C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. IDT™ / ICS™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER 17 ICS87973DYI-147 REV. A DECEMBER 9, 2008 ICS87973I-147 LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER Revision History Sheet Rev Table Page T4B T6 7 8 10 12 16 17 A T8 T9 Description of Change Date Differential DC Characteristics Table - updated NOTES. AC Characteristics Table - added thermal note. Added Recommendations for Unused Input and Output Pins section. Updated Differetnial Clock Input Interface section. UpdatePackage Outline and Package Dimensions Table. Ordering Information Table - added lead-free part number and marking. IDT™ / ICS™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER 18 12/9/08 ICS87973DYI-147 REV. A DECEMBER 9, 2008 ICS87973I-147 LOW SKEW, 1-TO-12, LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER Contact Information: www.IDT.com www.IDT.com Sales Technical Support 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT [email protected] +480-763-2056 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800-345-7015 (inside USA) +408-284-8200 (outside USA) © 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA