SDAS234 − D2661, DECEMBER 1982 − REVISED AUGUST 1985 • • • • • • Package Options Include Plastic Small Outline Packages, Both Plastic and Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs Buffered 3-State Outputs Drive Bus Lines Directly Cascaded to n-Bits Eight Selectable Transceiver/Port Functions: A to B or B to A Register to A or Register to B Shifted to A or Shifted to B Off-Line Shifts (A and B Ports in High-Impedance State) Register Clear Particularly Suitable for Use in Signature Analysis Circuitry Serial Register Provides: Parallel Storage of Either A or B Input Data Serial Transmission of Data from Either A or B Port Dependable Texas Instruments Quality and Reliability description SN54AS877 . . . JT PACKAGE SN74AS877 . . . DW OR NT PACKAGE (TOP VIEW) S0 S1 S2 A1 A2 A3 A4 A5 A6 A7 A8 GND 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC CLK SERIN B1 B2 B3 B4 B5 B6 B7 B8 Q8 SN54AS877 . . . JT PACKAGE SN74AS877 . . . DW OR NT PACKAGE (TOP VIEW) S2 S1 S0 NC VCC CLK SERIN • A1 A2 A3 NC A4 A5 A6 5 4 3 2 1 28 27 26 25 6 24 7 23 8 22 B1 B2 B3 NC B4 B5 B6 A7 A8 GND NC Q8 B8 B7 9 21 The ’AS877 features two 8-bit I/O ports (A1-A8 10 and B1-B8), an 8-bit parallel-load, serial-in, 20 parallel-out shift register, and control logic. With 11 19 12 13 14 15 16 17 18 these features, this device is capable of performing eight selectable transceiver or port functions, depending on the state of the three select lines S0, S1, and S2. These functions NC − No internal connection include: transferring data from port A to port B or vice versa (i.e., the transceiver function), transferring data from the register to either port, serial shifting data to either port, performing off-line shifts (with A and B ports in high-impedance state), and clearing the register. Synchronous parallel loading of the internal register can be accomplished from either port on the positive transition of the clock while serially shifting data in via the SERIN input. The ’AS877 is ideally suited for applications needing signature-analysis circuitry to enhance system verification and/or fault analysis. All serial data is shifted right. All outputs are buffer-type outputs designed specifically to drive bus lines directly and all are 3-state except for Q8, which is a totem-pole output. The SN54AS877 is characterized for operation over the full military temperature range of −55°C to 125°C. The SN74AS877 is characterized for operation from 0°C to 70°C. Copyright 1985, Texas Instruments Incorporated ! "#$ ! %#&'" ($) (#"! " !%$""! %$ *$ $! $+! !#$! !(( ,-) (#" %"$!!. ($! $"$!!'- "'#($ $!. '' %$$!) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 2 H H H H H H L L L H H H L L L H H L L H H L L S0 X H L ↑ ↑ H ↑ H or L X L ↑ H or L H ↑ L X ↑ H or L X H ↑ X H or L X ↑ X H or L X ↑ X H or L X ↑ X H or L X ↑ SERIN H or L CLOCK Z Z Z Z Z L H Q1 Z Z Z B1 Q1 Z X B1 B1 Z Z A1 H Qn L H Qn L H Qn L H Qn B1 Qn A1 Qn B1 Qn A1 Qn Q1 Z Z Z Z Z Z Z Z L H Q1 Z X A1 Q1 Z Z A1 A1 B1 Z Z Z Z Z Q1 Q1 Q2 Z Z Z B2 Q2 Z X B2 B2 Z Z A2 L Qn Q1 Q1 Qn Q1 Q1 Qn Q1 Q1 Qn B2 Qn A2 Qn B2 Qn A2 Qn Q2 Z Z Z Z Z Z Z Z Q1 Q1 Q2 Z X A2 Q2 Z Z A2 A2 B2 Z Z Z Z Z Q2 Q2 Q3 Q2 Q2 Q3 B3 Q3 Z X B3 B3 Z Z A3 L Qn Q2 Q2 Qn Q2 Q2 Qn Q2 Q2 Qn B3 Qn A3 Qn B3 Qn A3 Qn Q3 Z Z Z Z Z Z Z Z Q2 Q2 Q3 Z Z A3 Q3 Z Z A3 A3 B3 Z Z Z Z Z Q3 Q3 Q4 Z Z Z B4 Q4 Z X B4 B4 Z Z A4 L Qn Q3 Q3 Qn Q3 Q3 Qn Q3 Q3 Qn B4 Qn A4 Qn B4 Qn A4 Qn Q4 Z Z Q3 Q3 Q4 Z Z Z Q3 Q3 Q4 Z Z A4 Q4 Z Z Q4 Q4 B4 Z Z Z Z Z Q4 Q4 Q5 Z Z Z B5 Q5 Z X B5 B5 Z Z A5 L Qn Q4 Q4 Qn Q4 Q4 Qn Q4 Q4 Qn B5 Qn A5 Qn B5 Qn Q5 Qn Q5 Z Z Z Z Z Z Z Z Q4 Q4 Q5 Z X A5 Q5 Z Z A5 A5 B5 Z Z Z Z Z Q5 Q5 Q6 Z Z Z B6 Q6 Z X B6 B6 Z Z A6 L Qn Q5 Q5 Qn Q5 Q5 Qn Q5 Q5 Qn B6 Qn A6 Qn B6 Qn A6 Qn Q6 Z Z Q5 Q5 Q6 Z Z Z Q5 Q5 Q6 Z Z A6 Q6 Z Z Q6 Q6 B6 Z Z Z Z Z Q6 Q6 Q7 Z Z Z B7 Q7 Z X B7 B7 Z Z A7 L Qn Q6 Q6 Qn Q6 Q6 Qn Q6 Q6 Qn B7 Qn A7 Qn B7 Qn A7 Qn Q7 Z Z Q6 Q6 Q7 Z Z Z Q6 Q6 Q7 Z Z A7 Q7 Z Z Q7 Q7 B7 Z Z Z Z Z Q7 Q7 Q8 Z Z Z B8 Q8 Z X B8 B8 Z Z A8 L Qn Q7 Q7 Qn Q7 Q7 Qn Q7 Q7 Qn B8 Qn A8 Qn B8 Qn A8 Qn Q8 Z Z Z Z Z Z Z Z Q7 Q7 Q8 Z X A8 Q8 Z Z A8 A8 B8 Clear Shift A To Shift B To Shift QN To AN QN To BN B To A A To B PORT FUNCTION n = level Of Qn(n = 1, 2 . . . 8) established on most recent transition of CLK. Q1 thru Q8 are the shift register outputs; only Q8 is available externally. The double inversions that take place as data travels from port to port are ignored in this table. H L H H L H H L H H H L H H L H H L L H L L L L H L L H L L L L L H S1 MODE S2 FUNCTION TABLE SDAS234 - D2661, DECEMBER 1982 - REVISED AUGUST 1985 • HOUSTON, • DALLAS,TEXAS POST POST OFFICE OFFICE BOX BOX 1443 655303 TEXAS 77001 75265 SDAS234 − D2661, DECEMBER 1982 − REVISED AUGUST 1985 logic symbol † 1 S0 2 S1 3 S2 23 CLK 22 SERIN 4 A1 A2 A3 A4 A5 A6 A7 A8 5 6 7 8 9 10 11 (PORT CONTROLLER) 0 2 0 EN 7 SRG8 9 9 Z9 ≥1 11 12 (1/3/5) 13,1 13 14,(3/5) ≥1 15 Z15 (1/3/5) 16 16,1 17(3/5) Z11 Z12 ≥1 Z33 33 (1/3/5) 34,1 34 35(3/5) (4/5/6) C10/7R ≥1 I=0 (4/5/6)10D (0/2)10D 12 (1/3)10D I=0 (0/2)10D 15 (1/3)10D I=0 (0/2)10D 33 (1/3)10D (0/2/4) 0 Z13 2/4 Z14 ≥1 (0/2/4) Z16 0 2/4 Z17 ≥1 (0/2/4) 0 Z34 2/4 35 Z35 21 20 19 18 17 16 15 14 13 B1 B2 B3 B4 B5 B6 B7 B8 Q8 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for DW, JT, and NT packages. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 • 3 /010 SDAS234 − D2661, DECEMBER 1982 − REVISED AUGUST 1985 logic diagram (positive logic) S0 S1 S2 CLK SERIN A1 A2 1 2 3 23 22 4 5 I=1 1D C1 21 I=1 1D C1 20 B1 B2 Four Identical Channels Not Shown: Inputs/Outputs Not Shown: 6 A3 19 B3 7 A4 18 B4 8 A5 17 B5 9 A6 16 B6 A7 A8 10 11 I=1 1D C1 15 I=1 1D C1 14 13 Pin numbers shown are for DW, JT, and NT packages. 4 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 • B7 B8 Q8 SDAS234 − D2661, DECEMBER 1982 − REVISED AUGUST 1985 absolute maximum ratings over free-air temperature range Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage: All inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range: SN54AS877 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C SN74AS877 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C recommended operating conditions SN54AS877 VCC VIH Supply voltage VIL Low-level input voltage High-level input voltage IOH High-level input voltage IOL Low-level input voltage fclock tw MAX 4.5 5 5.5 4.5 5 5.5 2 0.8 Q8 −2 −2 A1-A8, B1-B8 32 48 Q8 20 20 0 SERIN SERIN S0, S1, S2 Operating free-air temperature • 0 10 5.5 5.5 5.5 5.5 0 0 0 0 −55 POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 • 45 11 125 0 UNIT V V −15 A1-A8, B1-B8 TA NOM 0.8 Pulse duration, CLK Hold time, data after CLK↑ MIN −12 S0, S1, S2 th MAX A1-A8, B1-B8 Clock frequency Setup time before CLK↑ NOM 2 A1-A8, B1-B8 tsu SN74AS877 MIN 50 V mA mA MHz ns ns ns 70 °C 5 SDAS234 − D2661, DECEMBER 1982 − REVISED AUGUST 1985 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK 3.2 2 VCC = 4.5 V, VCC = 4.5 V to 5.5 V, IOH = − 15 mA IOH = − 2 mA VCC −2 IOL = 32 mA IOL = 48 mA 0.25 0.5 except Q8 VCC = 4.5 V, VCC = 4.5 V, Q8 VCC = 4.5 V, IOL = 20 mA 0.25 0.5 CLK and SERIN VCC = 5.5 V, VI = 7 V A1-A8, B1-B8 VCC = 5.5 V, VI = 5.5 V VCC = 5.5 V, VI = 2.7 V B1-B8 All outputs S0, S1, S2 II SN54AS877 TYP† MAX II = − 18 mA IOH = − 12 mA All outputs VOL MIN VCC = 4.5 V, VCC = 4.5 V, A1-A8 VOH TEST CONDITIONS CLK and SERIN A1-A8, B1-B8‡ CLK and SERIN VCC = 5.5 V, 2 VI = 0.4 V A1-A8, B1-B8 IO§ Except Q8 Q8 VCC = 5.5 V, −1.2 VO = 2.25 V 3.3 UNIT V V VCC −2 S0, S1, S2 IIL SN74AS877 TYP† MAX −1.2 S0, S1, S2 IIH MIN 0.35 0.5 0.25 0.5 0.3 0.3 0.1 0.1 0.2 0.2 60 60 20 20 70 70 −1 −1 −0.5 −0.5 −0.75 −0.75 −30 −112 −30 −112 −20 −112 −20 −112 V mA µA mA mA ICC VCC = 5.5 V 136 220 136 220 mA † All typical values are at VCC = 5 V, TA = 25°C. ‡ For I/O ports, the parameters IIH and IIL include the output currents IOZH and IOZL, respectively. § The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. 6 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 • SDAS234 − D2661, DECEMBER 1982 − REVISED AUGUST 1985 switching characteristics (see Note 1) VCC = 4.5 V to 5.5 V, CL = 50 pF, R1 = 500 Ω, PARAMETER FROM TO (INPUT) (OUTPUT) R2 = 500 Ω, TA = MIN to MAX SN54AS877 SN74AS877 MIN fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHZ tPLZ tPZH MAX 45 2 7 3 10.5 3 9 2 9 2 7.5 3 10.5 3 9 Any A or B 2 11.5 2 10 port 3 9.5 3 8 Any A or B 2 11 2 9 port 3 13 3 11.5 2 10.5 2 8 3 10 3 8.5 2 7.5 2 6.5 3 13 3 10.5 2 9 2 Any B port Any A port CLK QB Any A or B port S0, S1, S2 † tPZL 3 11.5 3 NOTE 1: Load circuit and voltage waveforms are shown in Section 1. † The positive transition of S2 will cause low-level data at the A output Bus or stored in the shift register to be invalid for 12 ns. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 • MHz 8.5 Any B port CLk MAX 50 2 Any A port S0, S1, S2 † MIN UNIT 7 9.5 ns ns ns ns ns ns ns 7 SDAS234 − D2661, DECEMBER 1982 − REVISED AUGUST 1985 TYPICAL APPLICATION DATA BUS A TO BUS B OR SERIAL TRANSMISSION BUS B TO BUS A OR SERIAL TRANSMISSION Serial In CLK Serial In CLK SERIN REG A SERIN REG B A Q8 Q8 SERIN REG A SERIN REG B A B Q8 Q8 Serial Out Serial Out SERIAL IN TO A PORT SERIAL IN TO B PORT Serial In CLK Serial In CLK SERIN REG SERIN REG B Hi-Z A 8 B Hi-Z A B Q8 Q8 Serial Out Serial Out • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 • PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74AS877DW OBSOLETE SOIC DW 24 TBD Call TI Call TI SN74AS877NT OBSOLETE PDIP NT 24 TBD Call TI Call TI SN74AS877NT OBSOLETE PDIP NT 24 TBD Call TI Call TI SN74AS877NT OBSOLETE PDIP NT 24 TBD Call TI Call TI Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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