PSEMI PE42821

Product Specification
PE42821
UltraCMOS® SPDT RF Switch
100 - 2700 MHz
Product Description
The PE42821 is a HaRP™ technology-enhanced high
power reflective SPDT RF switch designed for use in
mobile radio, relay replacement and other high
performance wireless applications.
This switch is a pin-compatible faster switching version of
the PE42820. It maintains high linearity and power
handling from 100 MHz through 2.7 GHz. PE42821 also
features low insertion loss and is offered in a 32-lead
5x5 mm QFN package. In addition, no external blocking
capacitors are required if 0V DC is present on the RF
ports.
Features
 High power handling
 45 dBm @ 850 MHz, 32W
 44 dBm @ 2 GHz, 25W
 High linearity
 82 dBm IIP3 @ 850 MHz
 76 dBm IIP3 @ 2.7 GHz
 Low insertion loss
 0.35 dB @ 850 MHz
 0.60 dB @ 2 GHz
 Fast switching time of 4 µs
The PE42821 is manufactured on Peregrine’s
UltraCMOS® process, a patented variation of silicon-oninsulator (SOI) technology on a sapphire substrate.



Peregrine’s HaRP™ technology enhancements deliver
high linearity and excellent harmonics performance. It is
an innovative feature of the UltraCMOS® process, offering
the performance of GaAs with the economy and
integration of conventional CMOS.

(bypass mode)
Wide supply range of 2.3V to 5.5V
+1.8V control logic compatible
ESD performance
 1.5kV HBM on all pins
External negative supply option
Figure 2. Package Type
32-lead 5x5 mm QFN
Figure 1. Functional Diagram
DOC-52312
Document No. DOC-13714-3 │ www.psemi.com
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 12
PE42821
Product Specification
Table 1. Electrical Specifications @ 25°C (ZS = ZL = 50Ω ) unless otherwise noted
Normal mode1: VDD = 3.3V, VssEXT = 0V or Bypass mode2: VDD = 3.3V, VssEXT = -3.3V
Parameter
Insertion loss
Path
3
RFC–RFX
Isolation
RFX–RFX
Unbiased isolation
Return loss
RFC–RFX
3
RFX
Condition
Min
Typ
Max
Unit
100 MHz – 1 GHz
0.40
0.55
dB
1 GHz – 2 GHz
0.60
0.80
dB
2 GHz – 2.7 GHz
0.80
1.05
dB
100 MHz – 1 GHz
33
35
dB
1 GHz – 2 GHz
26
28
dB
2 GHz – 2.7 GHz
22
24
dB
VDD, V1 = 0V, +27 dBm
6
dB
100 MHz – 1 GHz
20
dB
1 GHz – 2 GHz
13
dB
2 GHz – 2.7 GHz
14
dB
Harmonics
RFC–RFX
2fo: +45 dBm pulsed @ 1GHz, 50Ω
3fo: +45 dBm pulsed @ 1GHz, 50Ω
-82
-78
dBc
-85
-81
dBc
Input IP3
RFC–RFX
850 MHz
2700 MHz
82
dBm
76
dBm
Input 0.1 dB compression point4
RFC-RFX
100 MHz – 2 GHz
2 GHz – 2.7 GHz
45.5
44.5
dBm
dBm
Switching time in normal mode1
50% CTRL to 90% or 10% RF
2
50% CTRL to 90% or 10% RF
Switching time in bypass mode
Settling time
7
11
4
50% CTRL to harmonics within specifications
5
15
µs
µs
25
µs
Notes: 1. Normal mode: single external positive supply used
2. Bypass mode: both external positive supply and external negative supply used
3. Performance specified with external matching. Refer to Evaluation Kit section for additional information
4. The input 0.1dB compression point is a linearity figure of merit. Refer to Table 3 for the operating RF input power (50Ω)
5. See harmonics specs above
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 12
Document No. DOC-13714-3 │ UltraCMOS® RFIC Solutions
PE42821
Product Specification
Figure 3. Pin Configuration (Top View)
Table 3. Operating Ranges
Pin 1 Dot
Marking
Parameter
Symbol
Min
Supply voltage
VDD
2.3
Supply current
IDD
Supply voltage
Supply current
Normal mode
GND
1
24
GND
RF1
2
23
RF2
GND
3
22
GND
GND
4
21
GND
GND
5
20
GND
GND
6
19
GND
GND
7
18
GND
8
17
Exposed
Ground Pad
Max
Unit
5.5
V
130
200
µA
Bypass mode
VDD
3.3
5.5
V
IDD
50
80
µA
-3.2
V
2
Negative supply
voltage
VssEXT
-3.6
GND
Negative supply
current
ISS
-40
GND
Normal or Bypass mode
Digital input high (V1)
VIH
1.17
3.63
V
Digital input low (V1)
VIL
-0.3
0.6
V
43
42
dBm
dBm
45
44
dBm
dBm
27
dBm
+85
°C
+140
°C
Table 2. Pin Descriptions
RF input power, CW
100 MHz – 2 GHz
>2 GHz – 2.7 GHz
PMAX,CW
PMAX,PULSED
Pin #
Pin Name
1, 3-11, 14,
15, 17-22,
24-27, 29-32
GND
Ground
RF input power,
pulsed4
100 MHz – 2 GHz
>2 GHz – 2.7 GHz
2
RF11
RF port
RF input power,
unbiased
12
VDD
Supply voltage (nominal 3.3V)
13
V1
Digital control logic input 1
16
VssEXT2
23
RF21
RF port
28
RFC1
RF common
Pad
GND
Exposed pad: ground for proper operation
Description
External Vss negative voltage control
Notes: 1. RF pins 2, 23 and 28 must be at 0V DC. The RF pins do not require
DC blocking capacitors for proper operation if the 0V DC requirement is
met
2. Use VssEXT (pin 16, VssEXT = -VDD) to bypass and disable internal
negative voltage generator. Connect VssEXT (pin 16, VssEXT = GND) to
enable internal negative voltage generator
Document No. DOC-13714-3 │ www.psemi.com
Typ
1
Operating temperature
range (Case)
Operating junction
temperature
PMAX,UNB
TOP
TJ
-40
-16
µA
Notes: 1. Normal mode: connect pin 16 to GND to enable internal negative
voltage generator
2. Bypass mode: apply a negative voltage to VssEXT (pin 16) to bypass
and disable internal negative voltage generator
3. Maximum VIH voltage is limited to VDD and cannot exceed 3.6V
4. Pulsed, 10% duty cycle of 4620 µs period, 50Ω
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 12
PE42821
Product Specification
Table 5. Control Logic Truth Table
Table 4. Absolute Maximum Ratings
Parameter/Condition
Supply voltage
Digital input voltage (V1)
Max
Unit
VDD
-0.3
5.5
V
RFC – RF1
H
VCTRL
-0.3
3.6
V
RFC – RF2
L
45.5
44.5
dBm
dBm
+150
°C
-65
Storage temperature range
TST
Maximum case temperature
TCASE
+85
°C
TJ
+200
°C
VESD,HBM
1500
V
VESD,MM
200
V
VESD,CDM
250
V
ESD voltage HBM1, all pins
2
ESD voltage MM , all pins
3
ESD voltage CDM , all pins
CTRL
Min
Maximum input power
100 MHz – 2 GHz PMAX,ABS
>2 GHz – 2.7 GHz
Peak maximum junction
temperature (10 seconds max)
Path
Symbol
Optional External Vss Control (VssEXT)
For applications that require a faster switching rate
or spur-free performance, this part can be
operated in bypass mode. Bypass mode requires
an external negative voltage in addition to an
external VDD supply voltage.
As specified in Table 3, the external negative
voltage (VssEXT) when applied to pin 16 will
disable and bypass the internal negative voltage
generator.
Notes: 1. Human Body Model (MIL-STD 883 Method 3015)
2. Machine Model (JEDEC JESD22-A115)
3. Charged Device Model (JEDEC JESD22-C101)
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be
restricted to the limits in the Operating Ranges
table. Operation between operating range
maximum and absolute maximum for extended
periods may reduce reliability.
Switching Frequency
Electrostatic Discharge (ESD) Precautions
The PE42821 has a maximum 25 kHz switching
rate in normal mode (pin 16 = GND). A faster
switching rate is available in bypass mode (pin 16
= VssEXT). The rate at which the PE42821 can be
switched is then limited to the switching time as
specified in Table 1.
When handling this UltraCMOS® device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified.
Switching frequency describes the time duration
between switching events. Switching time is the
time duration between the point the control signal
reaches 50% of the final value and the point the
output signal reaches within 10% or 90% of its
target value.
Latch-Up Avoidance
Spurious Performance
Unlike conventional CMOS devices, UltraCMOS
devices are immune to latch-up.
Moisture Sensitivity Level
The Moisture Sensitivity Level rating for the 32lead 5x5 mm QFN package is MSL3.
®
The typical low-frequency spurious performance
of the PE42821 in normal mode is -137 dBm (pin
16 = GND). If spur-free performance is desired,
the internal negative voltage generator can be
disabled by applying a negative voltage to VssEXT
(pin 16).
Hot Switching Capability
The typical hot switching capability of the
PE42821 is +30 dBm. Hot switching occurs when
RF power is applied while switching between RF
ports.
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 12
Document No. DOC-13714-3 │ UltraCMOS® RFIC Solutions
PE42821
Product Specification
Typical Performance Data @ 25°C, VDD = 3.3V, VssEXT = 0V unless otherwise noted
Figure 4. Insertion Loss vs. Temp (RFC–RFX)
Figure 5. Insertion Loss vs. VDD (RFC–RFX)
Figure 6. RFC Port Return Loss vs. Temp
(RF1 Active)
Figure 7. RFC Port Return Loss vs. VDD
(RF1 Active)
Document No. DOC-13714-3 │ www.psemi.com
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 5 of 12
PE42821
Product Specification
Typical Performance Data @ 25°C, VDD = 3.3V, VssEXT = 0V unless otherwise noted
Figure 8. Active Port Return Loss vs. Temp
(RF1 Active)
Figure 9. Active Port Return Loss vs. VDD
(RF1 Active)
Figure 10. Isolation vs. Temp
(RFC–RFX, RFX Active)
Figure 11. Isolation vs. VDD
(RFC–RFX, RFX Active)
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 6 of 12
Document No. DOC-13714-3 │ UltraCMOS® RFIC Solutions
PE42821
Product Specification
Typical Performance Data @ 25°C, VDD = 3.3V, VssEXT = 0V unless otherwise noted
Figure 12. Isolation vs. Temp
(RFX–RFX, RFX Active)
Document No. DOC-13714-3 │ www.psemi.com
Figure 13. Isolation vs. VDD
(RFX–RFX, RFX Active)
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 7 of 12
PE42821
Product Specification
Thermal Data
Though the insertion loss for this part is very low,
when handling high power RF signals, the junction
temperature rises significantly.
Table 6. Theta JC
Parameter
Theta JC (+85°C)
Min
Typ
20
Max
Unit
C/W
VSWR conditions that present short circuit loads to
the part can cause significantly more power
dissipation than with proper matching.
Special consideration needs to be made in the
design of the PCB to properly dissipate the heat
away from the part and maintain the 85°C maximum
case temperature. It is recommended to use best
design practices for high power QFN packages:
multi-layer PCBs with thermal vias in a thermal pad
soldered to the slug of the package. Special care
also needs to be made to alleviate solder voiding
under the part.
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 8 of 12
Document No. DOC-13714-3 │ UltraCMOS® RFIC Solutions
PE42821
Product Specification
Evaluation Kit
Figure 14. Evaluation Board Layout
The PE42821 Evaluation Kit board was designed
to ease customer evaluation of the PE42821 RF
switch.
The evaluation board in Figure 14 was designed
to test the part. DC power is supplied through J10,
with VDD on pin 9, and GND on the entire lower
row of even numbered pins. To evaluate a switch
path, add or remove jumpers on V1 (pin 3) using
Table 5.
The ANT port is connected through a 50Ω
transmission line via the top SMA connector, J1.
RF1 and RF2 paths are also connected through
50Ω transmission lines via SMA connectors as J2
and J3. A 50Ω through transmission line is
available via SMA connectors J5 and J6. This
transmission line can be used to estimate the loss
of the PCB over the environmental conditions
being evaluated. An open-ended 50Ω
transmission line is also provided at J4 for
calibration if needed.
Narrow trace widths are used near each part to
improve impedance matching. The shunt C1 on
RFC port is to provide for high frequency
impedance matching.
PRT-10605
Document No. DOC-13714-3 │ www.psemi.com
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 9 of 12
PE42821
Product Specification
Figure 15. Evaluation Board Schematic
DOC-13627
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 10 of 12
Document No. DOC-13714-3 │ UltraCMOS® RFIC Solutions
PE42821
Product Specification
Figure 16. Package Drawing
32-lead 5x5 mm QFN
A
0.10 C
(2X)
5.00
3.30±0.05
B
17
0.50
24
16
5.00
25
3.30±0.05
Pin #1 Corner
8
1
3.50
DOC-01872
0.10
0.05
0.05 C
C A B
C
ALL FEATURES
SEATING PLANE
0.203
Ref.
5.20
RECOMMENDED LAND PATTERN
0.90 MAX
0.10 C
5.20
3.35
DETAIL A
BOTTOM VIEW
TOP VIEW
3.35
32
9
0.10 C
(2X)
0.50
(X28)
0.575
(x32)
3.50
0.24±0.05
(X32)
0.290
(x32)
0.375±0.05
(X32)
SIDE VIEW
0.05
C
Figure 17. Top Marking Specification
42821
YYWW
ZZZZZZ
= Pin 1 indicator
YYWW = Date code, last two digits of the year and work week
ZZZZZZ = Six digits of the lot number
17-0085
Document No. DOC-13714-3 │ www.psemi.com
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 11 of 12
PE42821
Product Specification
Figure 18. Tape and Reel Specs
Pin 1
Notes: 1. 10 sprocket hole pitch cumulative tolerance ± 0.2
2. Camber in compliance with EIA 481
3. Pocket position relative to sprocket hole measured
as true position of pocket, not pocket hole
Top of
Device
Ao = 5.25 ± 0.1 mm
Bo = 5.25 ± 0.1 mm
Ko = 1.10 ± 0.1 mm
Device Orientation in Tape
Table 7. Ordering Information
Order Code
Description
Package
Shipping Method
PE42821MLBA-X
PE42821 SPDT RF switch
Green 32-lead 5x5 mm QFN
500 units/T&R
PE42821MLBA-Z
PE42821 SPDT RF switch
Green 32-lead 5x5 mm QFN
3000 units/T&R
EK42821-02
PE42821 Evaluation kit
Evaluation kit
1/Box
Sales Contact and Information
For sales and contact information please visit www.psemi.com.
Advance Information: The product is in a formative or design stage. The datasheet contains design target
specifications for product development. Specifications and features may change in any manner without notice.
Preliminary Specification: The datasheet contains preliminary data. Additional data may be added at a later
date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best
possible product. Product Specification: The datasheet contains final data. In the event Peregrine decides to
change the specifications, Peregrine will notify customers of the intended changes by issuing a CNF (Customer
Notification Form).
The information in this datasheet is believed to be reliable. However, Peregrine assumes no liability for the use
of this information. Use shall be entirely at the user’s own risk.
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 12 of 12
No patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party.
Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant,
or in other applications intended to support or sustain life, or in any application in which the failure of the
Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no
liability for damages, including consequential or incidental damages, arising out of the use of its products in
such applications.
The Peregrine name, logo, UltraCMOS and UTSi are registered trademarks and HaRP, MultiSwitch and DuNE
are trademarks of Peregrine Semiconductor Corp. Peregrine products are protected under one or more of
the following U.S. Patents: http://patents.psemi.com.
Document No. DOC-13714-3 │ UltraCMOS® RFIC Solutions