ONSEMI NTLUS3A40PZTAG

NTLUS3A40PZ
Power MOSFET
−20 V, −9.4 A, mCoolt Single P−Channel,
ESD, 2.0x2.0x0.55 mm UDFN Package
Features
• UDFN Package with Exposed Drain Pads for Excellent Thermal
•
•
•
•
Conduction
Low Profile UDFN 2.0x2.0x0.55 mm for Board Space Saving
Lowest RDS(on) in 2.0x2.0 Package
ESD Protected
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
http://onsemi.com
MOSFET
RDS(on) MAX
V(BR)DSS
ID MAX
29 mW @ −4.5 V
39 mW @ −2.5 V
−20 V
−9.4 A
60 mW @ −1.8 V
120 mW @ −1.5 V
Applications
• High Side Load Switch
• PA Switch and Battery Switch
• Optimized for Power Management Applications for Portable
S
Products, such as Cell Phones, PMP, DSC, GPS, and others
G
MAXIMUM RATINGS (TJ = 25°C unless otherwise stated)
Parameter
Drain-to-Source Voltage
Gate-to-Source Voltage
Continuous Drain
Current (Note 1)
Power Dissipation (Note 1)
Continuous Drain
Current (Note 2)
Symbol
Value
Units
VDSS
−20
V
VGS
±8.0
V
ID
−6.4
A
Steady
State
TA = 25°C
TA = 85°C
−4.6
t≤5s
TA = 25°C
−9.4
Steady
State
TA = 25°C
t≤5s
TA = 25°C
Steady
State
TA = 25°C
PD
TA = 85°C
W
1.7
1
A
−4.0
−2.9
TA = 25°C
PD
Pulsed Drain Current
tp = 10 ms
IDM
−30
A
TJ,
TSTG
-55 to
150
°C
Source Current (Body Diode) (Note 2)
IS
−1.0
A
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
TL
260
°C
ESD
>2000
V
ESD Rating (HBM) per JESD22−A114F
0.7
July, 2011 − Rev. 3
1
AA MG
G
AA = Specific Device Code
M = Date Code
G = Pb−Free Package
W
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq
[2 oz] including traces).
2. Surface-mounted on FR4 board using the minimum recommended pad size
of 30 mm2, 2 oz. Cu.
© Semiconductor Components Industries, LLC, 2011
UDFN6
CASE 517BG
mCOOLt
(Note: Microdot may be in either location)
Power Dissipation (Note 2)
Operating Junction and Storage
Temperature
MARKING
DIAGRAM
6
3.8
ID
D
P−Channel MOSFET
1
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
Publication Order Number:
NTLUS3A40PZ/D
NTLUS3A40PZ
THERMAL RESISTANCE RATINGS
Symbol
Max
Units
Junction-to-Ambient – Steady State (Note 3)
RθJA
72
°C/W
Junction-to-Ambient – t ≤ 5 s (Note 3)
RθJA
33
Junction-to-Ambient – Steady State min Pad (Note 4)
RθJA
189
Parameter
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
−20
Typ
Max
Units
OFF CHARACTERISTICS
Drain-to-Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = −250 mA
Drain-to-Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/TJ
ID = −250 mA, ref to 25°C
Zero Gate Voltage Drain Current
Gate-to-Source Leakage Current
IDSS
VGS = 0 V,
VDS = −20 V
V
−5.0
mV/°C
TJ = 25°C
−1.0
TJ = 85°C
−10
IGSS
VDS = 0 V, VGS = ±8.0 V
VGS(TH)
VGS = VDS, ID = −250 mA
±10
mA
mA
ON CHARACTERISTICS (Note 5)
Gate Threshold Voltage
Negative Threshold Temp. Coefficient
Drain-to-Source On Resistance
Forward Transconductance
−0.4
VGS(TH)/TJ
−1.0
3.0
RDS(on)
gFS
V
mV/°C
mW
VGS = −4.5 V, ID = −6.4 A
23
29
VGS = −2.5 V, ID = −4.8 A
31
39
VGS = −1.8 V, ID = −2.5 A
43
60
VGS = −1.5 V, ID = −1.5 A
60
120
VDS = −15 V, ID = −4.0 A
18
S
2600
pF
CHARGES, CAPACITANCES & GATE RESISTANCE
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
Total Gate Charge
QG(TOT)
Threshold Gate Charge
QG(TH)
Gate-to-Source Charge
QGS
Gate-to-Drain Charge
QGD
VGS = 0 V, f = 1 MHz,
VDS = −15 V
200
190
nC
29
VGS = −4.5 V, VDS = −15 V;
ID = −4.0 A
1.4
3.7
8.1
SWITCHING CHARACTERISTICS, VGS = 4.5 V (Note 6)
Turn-On Delay Time
td(ON)
9.0
tr
18
Rise Time
Turn-Off Delay Time
td(OFF)
Fall Time
VGS = −4.5 V, VDD = −15 V,
ID = −4.0 A, RG = 1 W
tf
ns
126
71
DRAIN-SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
VSD
Reverse Recovery Time
tRR
Charge Time
Discharge Time
Reverse Recovery Charge
3.
4.
5.
6.
ta
tb
VGS = 0 V,
IS = −1.0 A
TJ = 25°C
0.65
TJ = 125°C
0.55
25
VGS = 0 V, dis/dt = 100 A/ms,
IS = −1.0 A
QRR
http://onsemi.com
2
V
ns
10
15
13.6
Surface-mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [2 oz] including traces).
Surface-mounted on FR4 board using the minimum recommended pad size of 30 mm2, 2 oz. Cu.
Pulse Test: pulse width ≤ 300 ms, duty cycle ≤ 2%.
Switching characteristics are independent of operating junction temperatures.
1.0
nC
NTLUS3A40PZ
TYPICAL CHARACTERISTICS
20
−ID, DRAIN CURRENT (A)
−1.8 V
12
−4.0 V
VGS = −4.5 V
10
−1.6 V
8
6
4
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
12
10
8
4.5
TJ = 25°C
6
4
TJ = 125°C
0
0.5
TJ = −55°C
1.0
1.5
2.0
2.5
−VGS, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
TJ = 25°C
ID = −4.0 A
0.16
0.14
0.12
0.10
0.08
0.06
0.04
0.02
1.5
2.0
2.5
3.0
3.5
4.0
4.5
3.0
0.080
TJ = 25°C
0.070
−1.8 V
−1.5 V
0.060
0.050
0.040
−2.5 V
0.030
0.020
VGS = −4.5 V
0
2
4
6
10
8
12
14
18
16
20
−VGS, GATE VOLTAGE (V)
−ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
1.6
1.5
1.4
100,000
VGS = −4.5 V
ID = −4.0 A
−IDSS, LEAKAGE (nA)
RDS(on), NORMALIZED DRAIN−TO−
SOURCE RESISTANCE (W)
14
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
0.18
1.0
16
2
0
0.20
0.00
VDS ≤ −10 V
18
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
−ID, DRAIN CURRENT (A)
16
14
2
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
20
−2.0 V
−2.5 V
−3.0 V
−3.5 V
18
1.3
1.2
1.1
1.0
0.9
10,000
TJ = 125°C
1000
TJ = 85°C
0.8
0.7
−50
−25
0
25
50
75
100
125
150
100
2
4
6
8
10
12
14
16
18
TJ, JUNCTION TEMPERATURE (°C)
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
http://onsemi.com
3
20
NTLUS3A40PZ
VGS = 0 V
TJ = 25°C
f = 1 MHz
C, CAPACITANCE (pF)
3600
3200
Ciss
2800
2400
2000
1600
1200
800
Coss
400
0
Crss
0
2
4
6
8
10
12
14
18
16
20
5
16
4
VDS
2
8
QGD
VDS = −15 V
ID = −4.0 A
TJ = 25°C
1
0
0
5
15
10
20
25
4
0
30
QG, TOTAL GATE CHARGE (nC)
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
1000
−IS, SOURCE CURRENT (A)
10
VGS = −4.5 V
VDD = −15 V
ID = −4.0 A
t, TIME (ns)
12
QGS
Figure 7. Capacitance Variation
td(off)
100
tf
tr
10
td(on)
1
10
TJ = 125°C
TJ = 25°C
1
100
TJ = −55°C
0.2
0.4
0.6
0.8
1.0
1.2
RG, GATE RESISTANCE (W)
−VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
0.85
225
ID = −250 mA
0.75
200
175
POWER (W)
0.65
−VGS(th) (V)
VGS
3
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
1
20
QT
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
4000
−VGS, GATE−TO−SOURCE VOLTAGE (V)
TYPICAL CHARACTERISTICS
0.55
0.45
0.35
150
125
100
75
50
0.25
0.15
−50
25
−25
0
25
50
75
100
125
0
1.E−05
150
1.E−03
1.E−01
1.E+01
1.E+03
TJ, JUNCTION TEMPERATURE (°C)
SINGLE PULSE TIME (s)
Figure 11. Threshold Voltage
Figure 12. Single Pulse Maximum Power
Dissipation
http://onsemi.com
4
NTLUS3A40PZ
TYPICAL CHARACTERISTICS
−ID, DRAIN CURRENT (A)
100
10 ms
10
100 ms
1 ms
1
10 ms
VGS = −8 V
Single Pulse
TC = 25°C
0.1
0.01
dc
RDS(on) Limit
Thermal Limit
Package Limit
0.1
1
10
100
R(t), EFFECTIVE TRANSIENT THERMAL RESPONSE
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 13. Maximum Rated Forward Biased
Safe Operating Area
80
RqJA = 72°C/W
70
60
50
40
Duty Cycle = 0.5
30
20 0.2
0.05
0.02
0.01
10 0.1
0
1E−06
Single Pulse
1E−05
1E−04
1E−03
1E−02
1E−01
1E+00
1E+01
1E+02
1E+03
t, TIME (s)
Figure 14. FET Thermal Response
DEVICE ORDERING INFORMATION
Package
Shipping†
NTLUS3A40PZTAG
UDFN6
(Pb−Free)
3000 / Tape & Reel
NTLUS3A40PZTBG
UDFN6
(Pb−Free)
3000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
5
NTLUS3A40PZ
PACKAGE DIMENSIONS
UDFN6 2x2, 0.65P
CASE 517BG−01
ISSUE O
D
PIN ONE
REFERENCE
0.10 C
0.10 C
ÇÇÇ
ÇÇ ÇÇÇ
ÉÉ
ÉÉÉ
B
A
ÍÍ
ÍÍ
ÍÍ
EXPOSED Cu
PLATING
E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS
MEASURED BETWEEN 0.15 AND 0.30 mm FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS
THE TERMINALS.
5. CENTER TERMINAL LEAD IS OPTIONAL. CENTER TERMINAL
IS CONNECTED TO TERMINAL LEAD # 4.
6. LEADS 1, 2, 5 AND 6 ARE TIED TO THE FLAG.
MOLD CMPD
DETAIL B
OPTIONAL
CONSTRUCTIONS
L
L
TOP VIEW
DETAIL B
A
A3
0.10 C
DIM
A
A1
A3
b
b1
D
D2
E
E2
e
K
J
J1
L
L1
L2
L1
DETAIL A
OPTIONAL
CONSTRUCTIONS
0.08 C
NOTE 4
A1
L
SEATING
PLANE
D2
DETAIL A
6X
C
SIDE VIEW
1
L2
3
RECOMMENDED
MOUNTING FOOTPRINT
e
b1
2.30
0.10 C A
E2
0.05 C
K
6
4
J
J1
6X
MILLIMETERS
MIN
MAX
0.45
0.55
0.00
0.05
0.13 REF
0.25
0.35
0.51
0.61
2.00 BSC
1.00
1.20
2.00 BSC
1.10
1.30
0.65 BSC
0.15 REF
0.27 BSC
0.65 BSC
0.20
0.30
--0.10
0.20
0.30
B
NOTE 5
1.10
6X
6X
0.35
0.43
1
b
0.60
1.25
0.10 C A
0.05 C
B
0.35
NOTE 3
BOTTOM VIEW
0.34
0.65
PITCH
PACKAGE
OUTLINE
0.66
DIMENSIONS: MILLIMETERS
mCool is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
http://onsemi.com
6
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NTLUS3A40PZ/D