HSMP-381x, 481x Surface Mount RF PIN Low Distortion Attenuator Diodes Data Sheet Description/Applications Features The HSMP-381x series is specifically designed for low distortion attenuator applications. The HSMP-481x products feature ultra low parasitic inductance in the SOT-23 and SOT-323 packages. They are specifically designed for use at frequencies which are much higher than the upper limit for conventional diodes. x Diodes Optimized for: – Low Distortion Attenuating – Microwave Frequency Operation x Surface Mount Packages – Single and Dual Versions – Tape and Reel Options Available x Low Failure in Time (FIT) Rate[1] A SPICE model is not available for PIN diodes as SPICE does not provide for a key PIN diode characteristic, carrier lifetime. x Lead free Note: 1. For more information see the Surface Mount PIN Reliability Data Sheet. Package Lead Code Identification, SOT-23 (Top View) SINGLE 3 SERIES 3 1 1 #0 2 COMMON ANODE 3 1 #3 2 REVERSE SERIES 3 1 #5 2 #2 2 COMMON CATHODE 3 1 #4 SINGLE SERIES B C COMMON ANODE COMMON CATHODE E F 2 DUAL CATHODE 3 1 Package Lead Code Identification, SOT-323 (Top View) 2 4810 DUAL CATHODE 481B Absolute Maximum Ratings[1] TC = +25°C Symbol Parameter Unit SOT-23 SOT-323 If Forward Current (1 μs Pulse) Amp 1 1 PIV Peak Inverse Voltage V Same as VBR Same as VBR Tj Junction Temperature °C 150 150 Tstg Storage Temperature °C -65 to 150 -65 to 150 Tjc Thermal Resistance [2] °C/W 500 150 Notes: 1. Operation in excess of any one of these conditions may result in permanent damage to the device. 2. TC = +25°C, where TC is defined to be the temperature at the package pins where contact is made to the circuit board. Electrical Specifications TC = +25°C (Each Diode) Conventional Diodes Part Number HSMP- Package Marking Code Lead Code 3810 E0 0 Single 3812 E2 2 Series 3813 E3 3 Common Anode 3814 E4 4 Common Cathode 3815 E5 5 Reverse Series 381B E0 B Single Configuration 381C E2 C Series 381E E3 E Common Anode 381F E4 F Common Cathode Test Conditions Minimum Breakdown Voltage VBR (V) Maximum Total Capacitance CT (pF) Minimum Resistance at IF = 0.01mA, RH (Ω) Maximum Resistance at IF = 20mA, RL (Ω) 100 0.35 1500 VR = VBR Measure IR≤ 10uA VR = 50V f = 1MHz IF = 0.01mA IF = 20mA f = 100MHz f = 100MHz 10 Maximum Resistance at IF = 100mA, RT (Ω) Resistance at IF = 1mA, RM (Ω) 3.0 48 to 70 IF = 100mA f = 100MHz IF = 1mA f = 100MHz High Frequency (Low Inductance, 500 MHz – 3 GHz) PIN Diodes Part Number HSMP- Package Marking Code Lead Code Configuration 4810 EB B Dual Cathode 481B EB B Dual Cathode Test Conditions 2 Minimum Breakdown Voltage VBR (V) Maximum Series Resistance RS (Ω) Series Resistance IF = 1mA, RM (Ω) Typical Total Capacitance CT (pF) Maximum Total Capacitance CT (pF) Typical Total Inductance LT (nH) 100 3 48 - 70 0.35 0.4 1 VR = VBR Measure IR ≤ 10μA IF = 100mA f= 100MHz IF = 1mA f = 100MHz VR = 50V f = 1MHz VR = 50V f = 1MHz f= 500MHz - 3GHz Typical Parameters at TC = 25°C Part Number Total Capacitance Series Resistance Carrier Lifetime Reverse Recovery Time HSMP- RS (Ω) W (ns) Trr (ns) CT (pF) 381x 53 1500 300 0.27 @ 50 V IF = 1 mA f = 100 MHz IF = 50 mA IR = 250 mA VR = 10 V IF = 20 mA 90% Recovery f = 1 MHz Test Conditions Typical Parameters at TC = 25°C (unless otherwise noted), Single Diode 0.35 1 MHz 0.30 0.25 30 MHz 0.20 INPUT INTERCEPT POINT (dBm) 0.40 RF RESISTANCE (OHMS) TOTAL CAPACITANCE (pF) 120 10000 0.45 TA = +85 C TA = +25 C TA = –55 C 1000 100 10 frequency>100 MHz 0.15 0 2 4 6 8 1 0.01 10 12 14 16 18 20 1 10 100 90 80 70 60 50 40 1000 IF – FORWARD BIAS CURRENT (mA) REVERSE VOLTAGE (V) Figure 1. RF Capacitance vs. Reverse Bias. 100 IF – FORWARD CURRENT (mA) 0.1 Diode Mounted as a 110 Series Attenuator in a 50 Ohm Microstrip 100 and Tested at 123 MHz Figure 2. RF Resistance vs. Forward Bias Current, f = 100MHz 100 10 DIODE RF RESISTANCE (OHMS) Figure 3. 2nd Harmonic Input Intercept Point vs. Diode RF Resistance. Typical Applications for Multiple Diode Products VARIABLE BIAS 10 1 RF IN/OUT INPUT 0.1 125 C 25 C –50 C 0.01 0 0.2 0.4 0.6 0.8 1.0 1.2 VF – FORWARD VOLTAGE (mA) Figure 4. Forward Current vs. Forward Voltage. FIXED BIAS VOLTAGE Figure 5. Four Diode π Attenuator. See Application Note 1048 for Details. Notes: 3. Typical values were derived using limited samples during initial product characterization and may not be representative of the overall distribution. 3 Typical Applications for HSMP-481x Low Inductance Series Microstrip Series Connection for HSMP-481x Series In order to take full advantage of the low inductance of the HSMP-481x series when using them in series applications, both lead 1 and lead 2 should be connected together, as shown in Figure 7. 3 1 2 HSMP-481x Figure 6. Internal Connections. Figure 7. Circuit Layout. Microstrip Shunt Connections for HSMP-481x Series In Figure 8, the center conductor of the microstrip line is interrupted and leads 1 and 2 of the HSMP-481x series diode are placed across the resulting gap. This forces the 1.5 nH lead inductance of leads 1 and 2 to appear as part of a low pass filter, reducing the shunt parasitic inductance and increasing the maximum available attenuation. The 0.3 nHof shunt inductance external to the diode is created by the via holes, and is a good estimate for 0.032" thick material. 1.5 nH 1.5 nH 50 OHM MICROSTRIP LINES Rj 0.3 pF 0.3 nH PAD CONNECTED TO GROUND BY TWO VIA HOLES Figure 8. Circuit Layout. 4 Rj 0.08 + 2.5 I b0.9 Figure 9. Equivalent Circuit. 0.3 nH Typical Applications for HSMP-481x Low Inductance Series (continued) Co-Planar Waveguide Shunt Connection for HSMP-481x Series Equivalent Circuit Model HSMP-381x Chip* Co-Planar waveguide, with ground on the top side of the printed circuit board, is shown in Figure 10. Since it eliminates the need for via holes to ground, it offers lower shunt parasitic inductance and higher maximum attenuation when compared to microstrip circuit. Co-Planar Waveguide Groundplane Center Conductor Groundplane Rs Rj 2.5 Ω Cj RT = 2.5 + R j CT = CP + Cj 0.18 pF* * Measured at -20 V 80 R j = 0.9 Ω I I = Forward Bias Current in mA *See AN1124 for package models. Figure 10. Circuit Layout. Rj 0.3 pF 0.75 nH Figure 11. Equivalent Circuit. 5 Assembly Information SOT-323 PCB Footprint A recommended PCB pad layout for the miniature SOT-323 (SC-70) package is shown in Figure 12 (dimensions are in inches). This layout provides ample allowance for package placement by automated assembly equipment without adding parasitics that could impair the performance. 0.026 After ramping up from room temperature, the circuit board with components attached to it (held in place with solder paste) passes through one or more preheat zones. The preheat zones increase the temperature of the board and components to prevent thermal shock and begin evaporating solvents from the solder paste. The reflow zone briefly elevates the temperature sufficiently to produce a reflow of the solder. 0.079 0.039 0.022 Dimensions in inches Figure 12. Recommended PCB Pad Layout for Avago’s SC70 3L/SOT-323 Products. SOT-23 PCB Footprint 0.039 1 0.039 1 0.079 2.0 0.035 0.9 0.031 0.8 Dimensions in inches mm Figure 13. Recommended PCB Pad Layout for Avago’s SOT-23 Products. 6 SMT Assembly Reliable assembly of surface mount components is a complex process that involves many material, process, and equipment factors, including: method of heating (e.g., IR or vapor phase reflow, wave soldering, etc.) circuit board material, conductor thickness and pattern, type of solder alloy, and the thermal conductivity and thermal mass of components. Components with a low mass, such as the SOT-323/-23 package, will reach solder reflow temperatures faster than those with a greater mass. The rates of change of temperature for the ramp-up and cool-down zones are chosen to be low enough to not cause deformation of the board or damage to components due to thermal shock. The maximum temperature in the reflow zone (TMAX) should not exceed 260°C. These parameters are typical for a surface mount assembly process for Avago diodes. As a general guideline, the circuit board and components should be exposed only to the minimum temperatures and times necessary to achieve a uniform reflow of solder. Package Dimensions Outline SOT-323 (SC-70) Outline 23 (SOT-23) e1 e2 e1 E E XXX XXX E1 E1 e e L B L C D B DIMENSIONS (mm) D A A1 Notes: XXX-package marking Drawings are not to scale SYMBOL A A1 B C D E1 e e1 e2 E L MIN. 0.79 0.000 0.30 0.08 2.73 1.15 0.89 1.78 0.45 2.10 0.45 MAX. 1.20 0.100 0.54 0.20 3.13 1.50 1.02 2.04 0.60 2.70 0.69 A A1 Notes: XXX-package marking Drawings are not to scale Package Characteristics Lead Material .................................................... Copper (SOT-323); Alloy 42 (SOT-23) Lead Finish ......................................................................... Tin 100% (Lead-free option) Maximum Soldering Temperature ............................................ 260°C for 5 seconds Minimum Lead Strength........................................................................... 2 pounds pull Typical Package Inductance ...................................................................................... 2 nH Typical Package Capacitance ..............................................0.08 pF (opposite leads) Ordering Information Specify part number followed by option. For example: HSMP - 381x - XXX Bulk or Tape and Reel Option Part Number; x = Lead Code Surface Mount PIN Option Descriptions -BLKG = Bulk, 100 pcs. per antistatic bag -TR1G = Tape and Reel, 3000 devices per 7" reel -TR2G = Tape and Reel, 10,000 devices per 13" reel Tape and Reeling conforms to Electronic Industries RS-481, “Taping of Surface Mounted Components for Automated Placement.” 7 DIMENSIONS (mm) C SYMBOL A A1 B C D E1 e e1 E L MIN. MAX. 0.80 1.00 0.00 0.10 0.15 0.40 0.08 0.25 1.80 2.25 1.10 1.40 0.65 typical 1.30 typical 1.80 2.40 0.26 0.46 Device Orientation For Outlines SOT-23/323 TOP VIEW REEL END VIEW 4 mm 8 mm ABC ABC ABC ABC CARRIER TAPE USER FEED DIRECTION Note: "AB" represents package marking code. "C" represents date code. COVER TAPE Tape Dimensions and Product Orientation For Outline SOT-23 P P2 D E P0 F W D1 t1 Ko 9 MAX B0 A0 DESCRIPTION 8 13.5 MAX 8 MAX SYMBOL SIZE (mm) SIZE (INCHES) CAVITY LENGTH WIDTH DEPTH PITCH BOTTOM HOLE DIAMETER A0 B0 K0 P D1 3.15 ± 2.77 ± 1.22 ± 4.00 ± 1.00 + PERFORATION DIAMETER PITCH POSITION D P0 E 1.50 + 0.10 4.00 ± 0.10 1.75 ± 0.10 0.059 + 0.004 0.157 ± 0.004 0.069 ± 0.004 CARRIER TAPE WIDTH THICKNESS W t1 8.00 + 0.30 - 0.10 0.229 ± 0.013 0.315 + 0.012 - 0.004 0.009 ± 0.0005 DISTANCE BETWEEN CENTERLINE CAVITY TO PERFORATION (WIDTH DIRECTION) F 3.50 ± 0.05 0.138 ± 0.002 CAVITY TO PERFORATION (LENGTH DIRECTION) P2 2.00 ± 0.05 0.079 ± 0.002 0.10 0.10 0.10 0.10 0.05 0.124 ± 0.109 ± 0.048 ± 0.157 ± 0.039 ± 0.004 0.004 0.004 0.004 0.002 Tape Dimensions and Product Orientation For Outline SOT-323 P P2 D P0 E F W C D1 t1 (CARRIER TAPE THICKNESS) Tt (COVER TAPE THICKNESS) K0 An A0 DESCRIPTION B0 SYMBOL SIZE (mm) SIZE (INCHES) CAVITY LENGTH WIDTH DEPTH PITCH BOTTOM HOLE DIAMETER A0 B0 K0 P D1 2.40 ± 0.10 2.40 ± 0.10 1.20 ± 0.10 4.00 ± 0.10 1.00 + 0.25 0.094 ± 0.004 0.094 ± 0.004 0.047 ± 0.004 0.157 ± 0.004 0.039 + 0.010 PERFORATION DIAMETER PITCH POSITION D P0 E 1.55 ± 0.05 4.00 ± 0.10 1.75 ± 0.10 0.061 ± 0.002 0.157 ± 0.004 0.069 ± 0.004 CARRIER TAPE WIDTH THICKNESS W t1 8.00 ± 0.30 0.254 ± 0.02 0.315 ± 0.012 0.0100 ± 0.0008 COVER TAPE WIDTH TAPE THICKNESS C Tt 5.4 ± 0.10 0.062 ± 0.001 0.205 ± 0.004 0.0025 ± 0.00004 DISTANCE CAVITY TO PERFORATION (WIDTH DIRECTION) F 3.50 ± 0.05 0.138 ± 0.002 CAVITY TO PERFORATION (LENGTH DIRECTION) P2 2.00 ± 0.05 0.079 ± 0.002 FOR SOT-323 (SC70-3 LEAD) An 8 C MAX ANGLE FOR SOT-363 (SC70-6 LEAD) An 10 C MAX For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2009 Avago Technologies. All rights reserved. Obsoletes AV01-0378EN AV02-0402EN - December 22, 2009