SANYO LC877248A

Ordering number : ENN*6719
CMOS IC
LC877264A/56A/48A
8-Bit Single Chip Microcontroller with
64/56/48 KB ROM and 2048-Byte RAM On Chip
Preliminary
Overview
The LC877264A, LC877256A and LC877248A are 8 bit single chip microcontrollers with the following on-chip functional
blocks :
- CPU: operable at a minimum bus cycle time of 100 ns
- On-chip ROM Maximum Capacity :
LC877264A
64K bytes
LC877256A 56K bytes
LC877248A 48K bytes
- On-chip RAM capacity: 2048 bytes
- LCD controller / driver
- 16 bit timer / counter (can be divided into two 8 bit timers)
- 16 bit timer / PWM (can be divided into two 8 bit timers)
- Timer for use as date / time clock
- Synchronous serial I/O port (with automatic block transmit / receive function)
- Asynchronous / synchronous serial I/O port
- 12-channel × 8-bit AD converter
- Small signal detector
- 14-source 10-vectored interrupt system
All of the above functions are fabricated on a single chip.
Ver.1.04
70899
91400 RM (IM) SK No.6719-1/24
LC877264A/56A/48A
Features
(1) Read-Only Memory (ROM)
- 65536 × 8bits (LC877264A)
- 57344 × 8bits (LC877256A)
- 49152 × 8bits (LC877248A)
(2) Random Access Memory (RAM): 2048 × 9 bits (LC877264A, LC877256A, LC877248A)
(3) Minimum Bus Cycle Time: 100 ns (10 MHz)
Note: The bus cycle time indicates ROM read time.
(4) Minimum Instruction Cycle Time: 300 ns (10MHz)
(5) Ports
- Input/output ports
Data direction programmable for each bit individually :
26 (P1n, P30-P35, P70-P73, P8n)
Data direction programmable in nibble units :
8 (P0n)
(When N-channel open drain output is selected, data can be input in bit units.)
- Input ports :
2 (XT1,XT2)
- LCD ports
Segment output :
48 (S00-S47)
Common output :
4 (COM0-COM3)
Bias terminals for LCD driver
3 (V1-V3)
Other functions
Input/output ports :
48(PAn,PBn,PCn,PDn,PEn,PFn)
Input ports :
7 (PLn)
- Oscillator pins :
2 (CF1,CF2)
- Reset pin :
1 (RES )
- Power supply :
6 (VSS1-3,VDD1-3)
(6) LCD controller
- Seven display modes are available (static, 1/2, 1/3, 1/4 duty × 1/2, 1/3 bias)
- Segment output and common output can be switched to general purpose input/output ports.
(7) Small signal detection (MIC signals etc)
- Counts pulses with the level which is greater than a preset value
- 2 bit counter
(8) Timers
- Timer 0: 16 bit timer / counter with capture register
Mode 0: 2 channel 8-bit timer with programmable 8 bit prescaler and 8 bit capture register
Mode 1: 8 bit timer with 8 bit programmable prescaler and 8 bit capture register + 8 bit
Counter with 8-bit capture register
Mode 2: 16 bit timer with 8 bit programmable prescaler and 16 bit capture register
Mode 3: 16 bit counter with 16 bit capture register
- Timer 1: PWM / 16 bit timer with toggle output function
Mode 0: 2 channel 8 bit timer (with toggle output)
Mode 1: 2 channel 8 bit PWM
Mode 2: 16 bit timer (with toggle output) Toggle output from lower 8 bits is also possible.
Mode 3: 16 bit timer (with toggle output) Lower order 8 bits can be used as PWM.
No.6719-2/24
LC877264A/56A/48A
- Base Timer
1) The clock signal can be selected from any of the following :
Sub-clock (32.768kHz crystal oscillator), system clock, and prescaler output from timer 0
2) Interrupts of five different time intervals are possible.
(9) Serial-interface
- SIO 0: 8 bit synchronous serial interface
1) LSB first / MSB first is selectable
2) Internal 8 bit baud-rate generator (fastest clock period 4 / 3 Tcyc)
3) Consecutive automatic data communication (1-256 bits)
- SIO 1: 8 bit asynchronous / synchronous serial interface
Mode 0: Synchronous 8 bit serial IO (2-wire or 3-wire, transmit clock 2–512 Tcyc)
Mode 1: Asynchronous serial IO (half duplex, 8 data bits, 1 stop bit, baud rate 8–2048Tcyc)
Mode 2: Bus mode 1 (start bit, 8 data bits, transmit clock 2–512 Tcyc)
Mode 3: Bus mode 2 (start detection, 8 data bits, stop detection)
(10) AD converter
-8 bits × 12 channels
(11) Remote control receiver circuit (connected to P73 / INT3 / T0IN terminal)
-Noise rejection function (noise rejection filter’s time constant can be selected from 1 / 32 / 128 Tcyc)
(12) Watchdog timer
- The watching time period is determined by an external RC.
- Watchdog timer can produce interrupt or system reset
(13) Interrupts: 14 sources, 10 vectors
1) Three priority (low, high and highest) multiple interrupts are supported. During interrupt handling, an equal or
lower priority interrupt request is postponed.
2) If interrupt requests to two or more vector addresses occur at once, the higher priority interrupt takes precedence.
In the case of equal priority levels, the vector with the lowest address takes precedence.
No.
Vector
Selectable Level
Interrupt signal
1
00003H
X or L
INT0
2
0000BH
X or L
INT1
3
00013H
H or L
INT2/T0L
4
0001BH
H or L
INT3/Base timer
5
00023H
H or L
T0H
6
0002BH
H or L
T1L/T1H
7
00033H
H or L
SIO0
8
0003BH
H or L
SIO1
9
00043H
H or L
ADC/MIC
10
0004BH
H or L
Port 0
• Priority Level : X > H > L
• For equal priority levels, vector with lowest address takes precedence.
(14) Subroutine stack levels: 1024 levels max.
Stack is located in RAM.
(15) Multiplication and division
- 16 bit × 8 bit (executed in 5 cycles)
- 24 bit × 16 bit (12 cycles)
- 16 bit ÷ 8 bit (8 cycles)
- 24 bit ÷ 16 bit (12 cycles)
No.6719-3/24
LC877264A/56A/48A
(16) Oscillation circuits
- On-chip RC oscillation for system clock use.
- CF oscillation for system clock use. (Rf built in, Rd external)
- Crystal oscillation low speed system clock use. (Rf built in, Rd external)
(17) Standby function
- HALT mode
HALT mode is used to reduce power consumption. During the HALT mode, program execution is stopped but
peripheral circuits keep operating (some parts of serial transfer operation stop.)
1) Oscillation circuits are not stopped automatically.
2) Released by the system reset or interrupts.
-HOLD mode
HOLD mode is used to reduce power consumption. Program execution and peripheral circuits are stopped.
1) CF, RC and crystal oscillation circuits stop automatically.
2) Released by any of the following conditions.
(1) Low level input to the reset pin
(2) Specified level input to one of INT0, INT1, INT2
(3) Port 0 interrupt
-X’tal HOLD made
X’tal HOLD mode is used to reduce power consumption. Program execution is stopped.
All peripheral circuits except the base timer are stopped.
1) CF and RC oscillation circuits stop automatically.
2) Crystal oscillator operation is kept in its state at HOLD mode inception.
3) Released by any of the following conditions
(1) Low level input to the reset pin
(2) Specified level input to one of INT0, INT1, INT2
(3) Port 0 interrupt
(4) Base-timer interrupt
(18) Package
- QIP100E
- SQFP100
(19) Development tools
- Evaluation chip
: LC876096
- Emulator: EVA62S + ECB876500 (Evaluation chip board) + SUB877200 + POD100QIP
or POD100SQFP (Type B)
- Flash ROM version: LC87F72C8A
No.6719-4/24
P06
P07
P10/SO0
P11/SI0/SB0
P12/SCK0
P13/SO1
P14/SI1/SB1
P15/SCK1
P16/T1PWML
P17/T1PWMH/BUZ
RES
XT1/AN10
XT2/AN11
VSS1
CF1
CF2
VDD1
P80/AN0
P81/AN1
P82/AN2
P83/AN3
P84/AN4
P85/AN5
P86/AN6
P87/AN7/MICIN
P70/INT0/T0LCP/AN8
P71/INT1/T0HCP/AN9
P72/INT2/T0IN
P73/INT3/T0IN
S0/PA0
V2/PL5
V1/PL4
COM0/PL0
COM1/PL1
COM2/PL2
COM3/PL3
P30
P31
VSS3
VDD3
P32
P33
P34
P35
P00
P01
P02
P03
P04
P05
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
V3/PL6
S47/PF7
S46/PF6
S45/PF5
S44/PF4
S43/PF3
S42/PF2
S41/PF1
S40/PF0
S39/PE7
S38/PE6
S37/PE5
S36/PE4
S35/PE3
S34/PE2
S33/PE1
S32/PE0
S31/PD7
S30/PD6
S29/PD5
S28/PD4
S27/PD3
S26/PD2
S25/PD1
S24/PD0
VSS2
VDD2
S23/PC7
S22/PC6
S21/PC5
LC877264A/56A/48A
Pin Assignment
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
S20/PC4
S19/PC3
S18/PC2
S17/PC1
S16/PC0
S15/PB7
S14/PB6
S13/PB5
S12/PB4
S11/PB3
S10/PB2
S9/PB1
S8/PB0
S7/PA7
S6/PA6
S5/PA5
S4/PA4
S3/PA3
S2/PA2
S1PA1
SANYO : QIP-100E
Package Dimension
(unit : mm)
3151
SANYO : QIP-100E
No.6719-5/24
LC877264A/56A/48A
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
S46/PF6
S45/PF5
S44/PF4
S43/PF3
S42/PF2
S41/PF1
S40/PF0
S39/PE7
S38/PE6
S37/PE5
S36/PE4
S35/PE3
S34/PE2
S33/PE1
S32/PE0
S31/PD7
S30/PD6
S29/PD5
S28/PD4
S27/PD3
S26/PD2
S25/PD1
S24/PD0
VSS2
VDD2
Pin Assignment
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
S23/PC7
S22/PC6
S21/PC5
S20/PC4
S19/PC3
S18/PC2
S17/PC1
S16/PC0
S15/PB7
S14/PB6
S13/PB5
S12/PB4
S11/PB3
S10/PB2
S9/PB1
S8/PB0
S7/PA7
S6/PA6
S5/PA5
S4/PA4
S3/PA3
S2/PA2
S1PA1
S0/PA0
P73/INT3/T0IN
P11/SI0/SB0
P12/SCK0
P13/SO1
P14/SI1/SB1
P15/SCK1
P16/T1PWML
P17/T1PWMH/BUZ
RES
XT1/AN10
XT2/AN11
VSS1
CF1
CF2
VDD1
P80/AN0
P81/AN1
P82/AN2
P83/AN3
P84/AN4
P85/AN5
P86/AN6
P87/AN7/MICIN
P70/INT0/T0LCP/AN8
P71/INT1/T0HCP/AN9
P72/INT2/T0IN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
S47/PF7
V3/PL6
V2/PL5
V1/PL4
COM0/PL0
COM1/PL1
COM2/PL2
COM3/PL3
P30
P31
VSS3
VDD3
P32
P33
P34
P35
P00
P01
P02
P03
P04
P05
P06
P07
P10/SO0
SANYO : SQFP-100
Package Dimension
(unit : mm)
3181B
SANYO : SQFP-100
No.6719-6/24
LC877264A/56A/48A
System Block Diagram
Interrupt Control
IR
CF
RC
ROM
Clock
Generator
Stand-by Control
PLA
PC
X’tal
Bus Interface
ACC
SIO0
Port 0
B Register
SIO1
Port 1
C Register
Timer 0
Port 3
ALU
Timer 1
Port 7
Base Timer
Port 8
PSW
LCD Controller
ADC
RAR
INT0 - 3
Noise Rejection Filter
Weak Signa Detector
RAM
Stack Pointer
Watch Dog Timer
No.6719-7/24
LC877264A/56A/48A
Pin Assignment
Pin name
I/O
VSS1
VSS2
VSS3
VDD1
VDD2
VDD3
PORT0
P00 to P07
-
• Power supply (-)
Function
Option
No
-
• Power supply (+)
No
I/O
• 8bit input/output port
• Data direction programmable in nibble units
• Use of pull-up resistor can be specified in nibble units
• Input for HOLD release
• Input for port 0 interrupt
Yes
PORT1
P10 to P17
I/O
• 8bit input/output port
• Data direction programmable for each bit
• Use of pull-up resistor can be specified for each bit individually
• Other pin functions
P10 SIO0 data output
P11 SIO0 data input or bus input/output
P12 SIO0 clock input/output
P13 SIO1 data output
P14 SIO1 data input or bus input/output
P15 SIO1 clock input/output
P16: Timer 1 PWML output
P17: Timer 1 PWMH output/Buzzer output
Yes
PORT3
P30 to P35
I/O
Yes
PORT7
P70 to P73
I/O
• 6bit Input/output port
• Data direction can be specified for each bit
• Use of pull-up resistor can be specified for each bit individually
• 4bit Input/output port
• Data direction can be specified for each bit
• Use of pull-up resistor can be specified for each bit individually
• Other functions
P70: INT0 input/HOLD release input/Timer0L capture input/output for watchdog
timer
P71: INT1 input/HOLD release input/Timer0H capture input
P72: INT2 input/HOLD release input/timer 0 event input/Timer0L capture input
P73: INT3 input(noise rejection filter attached)/timer 0 event input/Timer0H capture
input
AD input port: AN8(P70), AN9(P71)
• Interrupt detection selection
Rising and
Rising
Falling
H level
L level
falling
Yes
Yes
No
Yes
Yes
INT0
Yes
Yes
No
Yes
Yes
INT1
No
No
Yes
Yes
Yes
INT2
No
No
Yes
Yes
Yes
INT3
No
No.6719-8/24
LC877264A/56A/48A
Pin name
I/O
Function description
Option
I/O
• 8bit Input/output port
• Input/output can be specified for each bit individually
• Other functions:
AD input port: AN0 to AN7
Small signal detector input port: MICIN(P87)
No
S0/PA0 to
S7/PA7
I/O
• Segment output for LCD
• Can be used as general purpose input/output port (PA)
No
S8/PB0 to
S15/PB7
I/O
• Segment output for LCD
• Can be used as general purpose input/output port (PB)
No
S16/PC0 to
S23/PC7
I/O
• Segment output for LCD
• Can be used as general purpose input/output port (PC)
No
S24 /PD0to
S31/PD7
I/O
• Segment output for LCD
• Can be used as general purpose input/output port (PD)
No
S32/PE0 to
S39/PE7
I/O
• Segment output for LCD
• Can be used as general purpose input/output port (PE)
No
S40/PF0 to
S47/PF7
I/O
• Segment output for LCD
• Can be used as general purpose input/output port (PF)
No
COM0/PL0 to
COM3/PL3
I/O
• Common output for LCD
• Can be used as general purpose input port (PL)
No
V1/PL4 to
V3/PL6
I/O
• LCD output bias power supply
• Can be used as general purpose input port (PL)
No
PORT8
P80 to P87
RES
I
Reset terminal
No
XT1
I
• Input for 32.768kHz crystal oscillation
• Other functions:
General purpose input port
AD input port: AN10
• When not in use, connect to VDD1
No
XT2
I/O
• Output for 32.768kHz crystal oscillation
• Other functions:
General purpose input port
AD input port: AN11
• When not in use, set to oscillation mode and leave open
No
CF1
I
Input terminal for ceramic oscillator
No
CF2
O
Output terminal for ceramic oscillator
No
No.6719-9/24
LC877264A/56A/48A
Port Configuration
Port form and pull-up resistor options are shown in the following table.
Port status can be read even when port is set to output mode.
Terminal
P00 to P07
P10 to P17
P30 to P35
Option applies to:
Options
each bit
1
CMOS
2
Nch-open drain
1
CMOS
Programmable
2
Nch-open drain
Programmable
1
CMOS
Programmable
2
Nch-open drain
None
each bit
each bit
Output Form
Pull-up resistor
Programmable
(Note 1)
None
P70
–
None
Nch-open drain
Programmable
P71 to P73
–
None
CMOS
Programmable
P80 to P87
–
None
Nch-open drain
S0/PA0 to
S47/PF7
–
None
CMOS
COM0/PL0 to
COM3/PL3
–
None
Input only
None
V1/PL4 to
V3/PL6
–
None
Input only
None
XT1
–
None
Input only
None
XT2
–
None
Output for 32.768kHz crystal
oscillation
None
None
Programmable
Note 1 Attachment of Port0 programmable pull-up resistors is controllable in nibble units (P00-03, P04-07).
* Note 1: Connect as follows to reduce noise on VDD.
VSS1, VSS2 and VSS3 must be connected together and grounded.
*Note 2 : The power supply for the internal memory is VDD1 but it uses the VDD3 as the power supply for ports. When the
VDD3 is not backed up, the port level does not become “H” even if the port latch is in the “H” level. Therefore,
when the VDD3 is not backed up and the port latch is “H” level, the port level is unstable in the HOLD mode, and
the back up time becomes shorter because the through current runs from VDD to GND in the input buffer.
If VDD3 is not backed up, output “L” by the program or pull the port to “L” by the external circuit in the HOLD
mode so that the port level becomes “L” level and unnecessary current consumption is prevented.
LSI
VDD1
Power
supply
Back-up capacitors *2
VDD2
VDD3
VSS1 VSS2 VSS3
No.6719-10/24
LC877264A/56A/48A
1. Absolute Mximum Ratings at Ta=25°C and VSS1=VSS2=VSS3=0V
Parameter
Symbol
Pins
Conditions
Ratings
VDD[V]
min.
typ.
max.
Supply voltage
VDDMAX VDD1,VDD2,VDD3
VDD1=VDD2
=VDD3
-0.3
+7.0
Supply voltage
for LCD
VLCD
V1/PL4, V2/PL5,
V3/PL6
VDD1=VDD2
=VDD3
-0.3
VDD
Input voltage
VI
Port L
XT1,XT2,CF1, RES
-0.3
VDD+0.3
Input/Output
voltage
VI0(1)
•Port0, 1, 3, 7, 8
•Port A, B, C, D, E, F
-0.3
VDD+0.3
High
level
output
current
IOPH(1)
Port 0, 1, 3
Peak
output
current
Total
output
current
Low
level
output
current
Peak
output
current
Total
output
current
•CMOS output
selected
•Current at each pin
-10
-3
V
mA
IOPH(2)
Port 71,72,73
Current at each pin
IOPH(3)
Port A, B, C, D, E, F
Current at each pin
ΣIOAH(1)
Port 0, 1, 32, 33, 34, 35 Total of all pins
-40
ΣIOAH(2)
Port 30, 31
Total of all pins
-10
ΣIOAH(3)
Port 7
Total of all pins
-5
ΣIOAH(4)
Port A, B, C
Total of all pins
-25
ΣIOAH(5)
Port D, E, F
Total of all pins
-25
IOPL(1)
Port 0, 1, 32-35
Current at each pin
20
IOPL(2)
Port 30, 31
Current at each pin
30
IOPL(3)
Port 7,8
Current at each pin
5
IOPL(4)
Port A, B,C, D, E, F
Current at each pin
ΣIOAL(1)
Port 0, 1, 32, 33, 34, 35 Total of all pins
-5
15
60
ΣIOAL(2)
Port 30, 31
Total of all pins
60
ΣIOAL(3)
Port 7,8
Total of all pins
20
ΣIOAL(4)
Port A,B,C
Total of all pins
40
ΣIOAL(5)
Port D, E, F
Total of all pins
40
QIP100E
Ta = -30 to +70°C
500
Maximum power Pdmax
consumption
unit
SQFP100
mW
400
Operating
temperature
range
Topg
-30
70
Storage
temperature
range
Tstg
-55
125
°C
No.6719-11/24
LC877264A/56A/48A
2. Recommended Oerating Range at Ta=-30°C to +70°C, VSS1=VSS2=VSS3=0V
Parameter
Symbol
Operating
VDD(1)
supply voltage
range
VDD(2)
Pins
VDD1=VDD2=VDD3
Conditions
Ratings
VDD[V]
min.
typ.
max.
0.294µs≤ tCYC ≤
200µs
4.5
6.0
0.735µs ≤ tCYC ≤
200µs
2.5
6.0
2.0
6.0
Supply voltage
range in Hold
mode
VHD
VDD1
Keep RAM and
register data in
HOLD mode.
Input high
voltage
VIH(1)
•Port 0, 3, 8
•Port A,B,C,D,E,F,L
Output disable
2.5–6.0
0.3VDD
+0.7
VDD
VIH(2)
•Port 1
•Port 71,72,73
•P70 port input/interrupt
Output disable
2.5-6.0
0.3VDD
+0.7
VDD
VIH(3)
P87 small signal input
Output disable
2.5-6.0 0.75VDD
VDD
VIH(4)
Port 70
Watchdog timer
Output disable
2.5-6.0
0.9VDD
VDD
VIH(5)
XT1, XT2, CF1, RES
2.5-6.0 0.75VDD
VDD
VIL(1)
•Port 0, 3, 8
•Port A,B,C,D,E,F,L
Output disable
2.5-6.0
VSS
0.15VDD
+0.4
VIL(2)
•Port 1
•Port 71,72,73
•P70 port input/interrupt
Output disable
2.5-6.0
VSS
0.1VDD
+0.4
VIL(3)
Port 87 small signal input Output disable
2.5-6.0
VSS
0.25VDD
VIL(4)
Port 70
Watchdog timer
2.5-6.0
VSS
0.8VDD
-1.0
VIL(5)
XT1,XT2,CF1, RES
Input low
voltage
Operation
cycle time
Output disable
tCYC
External system FEXCF(1) CF1
clock
frequency
2.5-6.0
VSS
0.25VDD
4.5–6.0
0.294
200
2.5-6.0
0.735
200
•CF2 open
•system clock
divider :1/1
•external clock
DUTY = 50±5%
4.5–6.0
0.1
10
2.5-6.0
0.1
4
•CF2 open
•system clock
divider :1/2
4.5–6.0
0.2
20
2.5-6.0
0.2
unit
V
µs
MHz
8
Continued/
No.6719-12/24
LC877264A/56A/48A
Parameter
Oscillation
frequency
range
(Note 1)
Symbol
Pins
Conditions
FmCF(1)
CF1, CF2
10MHz ceramic resonator
oscillation
FmCF(2)
CF1, CF2
4MHz ceramic resonator
oscillation
Ratings
VDD[V]
min.
typ.
4.5–6.0
10
2.5–6.0
4
max.
unit
MHz
Refer to figure 1
Refer to figure 1
FmRC
FsX’tal
XT1, XT2
RC oscillation
2.5-6.0
32.768kHz crystal resonator
oscillation
2.5-6.0
0.3
1.0
32.768
2.0
kHz
Refer to figure 2
(Note 1) The port value of oscillation circuit is shown in table 1 and table 2.
No.6719-13/24
LC877264A/56A/48A
3. Electrical Characteristics at Ta=-30°C to +70°C, VSS1=VSS2=VSS3=0V
Parameter
High level
input
current
Low level
input
current
High level
output
voltage
Low level
output
voltage
LCD output
voltage
regulation
LCD bias
resistor
Symbol
Pins
Conditions
IIH(1)
•Port 0,1,3,7,8
•Port A,B,C,D,E,F,L
IIH(2)
IIH(3)
RES
XT1,XT2
IIH(4)
IIH(5)
CF1
P87/AN7/MICIN
small signal input
•Port 0,1,3,7,8
•Port A,B,C,D,E,F,L
•Output disabled
•Pull-up resister OFF.
•VIN=VDD
(including OFF state leak
current of the output Tr.)
VIN=VDD
When configured as an input
port
VIN=VDD
VIN=VDD
VIN=VBIS+0.5V
(VBIS : Bias voltage)
•Output disabled
•Pull-up resister OFF.
•VIN=VSS
(including OFF state leak
current of the output Tr.)
VIN=VSS
When configured as an input
port
VIN=VSS
VIN=VSS
VIN=VBIS-0.5V
(VBIS : Bias voltage)
IOH=-1.0mA
IOH=-0.1mA
IOH=-0.4mA
IOH=-1.0mA
IOH=-0.1mA
IOL=10mA
IOL=1.6mA
IOL=30mA
IOL=1mA
IOL=0.5mA
IOL=8mA
IOL=1.4mA
IIL(1)
IIL(2)
IIL(3)
RES
XT1,XT2
IIL(4)
IIL(5)
CF1
P87/AN7/MICIN
small signal input
Port 0,1,3: CMOS
output option
VOH(1)
VOH(2)
VOH(3)
VOH(4)
VOH(5)
VOL(1)
VOL(2)
VOL(3)
VOL(4)
VOL(5)
VOL(6)
VOL(7)
Port 7
Port A,B,C,D,E,F
Port 0,1,3
Port 30,31
Port 7,8
Port A,B,C,D,E,F
VODLS
S0–S47
VODLC
COM0–COM3
RLCD(1) Resistance per one
bias resistor
RLCD(2) •Resistance per one
bias resistor
•1/2R mode
Ratings
VDD[V]
typ.
max.
2.5-6.0
1
2.5-6.0
2.5-6.0
1
1
2.5-6.0
2.5-6.0
4.2
8.5
15
15
2.5-6.0
-1
2.5-6.0
2.5-6.0
-1
-1
2.5-6.0
2.5-6.0
-15
-15
-8.5
-4.2
4.5-6.0 VDD-1
2.5–6.0 VDD-0.5
2.5-6.0 VDD-1
4.5–6.0 VDD-1
2.5–6.0 VDD-0.5
4.5–6.0
2.5–6.0
4.5–6.0
4.5–6.0
2.5–6.0
4.5–6.0
2.5-6.0
I0=0mA
2.5–6.0
VLCD, 2/3VLCD,
1/3VLCD level output
Refer to figure 8
I0=0mA
2.5–6.0
VLCD, 2/3VLCD, 1/2VLCD
1/3VLCD level output
Refer to figure 8
Refer to figure 8
2.5–6.0
Refer to figure 8
min.
2.5–6.0
unit
µA
V
1.5
0.4
1.5
0.4
0.4
1.5
0.4
0
±0.2
0
±0.2
60
kΩ
30
Continued/
No.6719-14/24
LC877264A/56A/48A
Parameter
Symbol
Resistance of Rpu
pull-up
MOS Tr.
Hysterisis
VHIS(1)
voltage
VHIS(2)
Pin
capacitance
CP
Input
sensitivity
Vsen
Pins
•Port 0,1,3,7
•Port A,B,C,D,E,F
•Port 1,7
• RES
Port 87 small signal
input
All pins
Port 87 small signal
input
Conditions
VOH=0.9VDD
•All other terminals connected
to VSS.
•f=1MHz
•Ta=25°C
Ratings
VDD[V]
min.
typ.
4.5–6.0
15
40
70
2.5-4.5
25
70
150
2.5-6.0
0.1VDD
2.5-6.0
0.1VDD
2.5-6.0
10
2.5-6.0 0.12VDD
max.
unit
kΩ
V
pF
Vpp
No.6719-15/24
LC877264A/56A/48A
4. Serial Input / Output Characteristics at Ta=-30°C to +70°C, VSS1=VSS2=VSS3=0V
Serial output
Serial input
Output clock
Serial clock
Input clock
Parameter
Symbol
Pins
Conditions
Ratings
VDD[V]
min.
2.5-6.0
4/3
Cycle time
tSCK(1)
Low level
pulse width
tSCKL(1)
2/3
tSCKLA(1)
2/3
tSCKH(1)
2/3
High level
pulse width
SCK0(P12)
Refer to figure 6
tSCKHA(1)
typ.
3
tSCK(2)
Low level
pulse width
High level
pulse width
Cycle time
tSCKL(2)
1
tSCKH(2)
1
Low level
pulse width
tSCKL(3)
1/2
tSCKLA(2)
3/4
tSCKH(3)
1/2
High level
pulse width
SCK1(P15)
SCK0(P12)
Refer to figure 6
•CMOS output
•Refer to figure 6
2.5-6.0
2.5-6.0
2
4/3
tSCKHA(2)
SCK1(P15)
•CMOS output
•Refer to figure 6
2.5-6.0
tSCK(4)
Low level
pulse width
High level
pulse width
tSCKL(4)
1/2
tSCKH(4)
1/2
tsDI
Data hold time
thDI
Output
time
tdDO
delay
tSCK
2
Cycle time
Data set-up time
unit
tCYC
Cycle time
tSCK(3)
max.
2
tCYC
tSCK
µs
SI0(P10),
SI1(P13),
SB0(P11),
SB1(P14)
•Measured with respect
to SI0CLK leading
edge.
•Refer to figure 6
4.5–6.0
2.5-6.0
0.03
0.1
4.5–6.0
2.5-6.0
0.03
0.1
SO0(P12),
SO1(P15),
SB0(011),
SB1(P14)
•When Port is open
drain:
Time delay form
SIOCLK trailing edge
to the SO data change
•Refer to figure 6
4.5–6.0
1/3
tCYC
+0.05
2.5-6.0
1/3
tCYC
+0.25
No.6719-16/24
LC877264A/56A/48A
5. Pulse Input Conditions at Ta=-30°C to +70°C, VSS1=VSS2=VSS3=0V
Parameter
Symbol
Pins
Ratings
Conditions
VDD[V]
min.
INT0(P70),
INT1(P71),
INT2(P72)
•Condition that interrupt is 2.5-6.0
accepted
•Condition that event input
to timer 0 is accepted
1
tPIH(2)
tPIL(2)
INT3(P73)
(Noise rejection ratio
is 1/1.)
•Condition that interrupt is 2.5-6.0
accepted
•Condition that event input
to timer 0 is accepted
2
tPIH(3)
tPIL(3)
INT3(P73)
(Noise rejection ratio
is 1/32.)
•Condition that interrupt is 2.5-6.0
accepted
•Condition that event input
to timer 0 is accepted
64
tPIH(4)
tPIL(4)
INT3(P73)
(Noise rejection ratio
is 1/128.)
•Condition that interrupt is 2.5-6.0
accepted
•Condition that event input
to timer 0 is accepted
256
tPIL(5)
tPIL(5)
MICIN(P87)
•Condition that signal is
accepted to small signal
detection counter.
2.5-6.0
1
tPIL(6)
RES
•Condition that reset is
accepted
2.5-6.0
200
High/low level tPIH(1)
pulse width
tPIL(1)
typ.
max.
unit
tCYC
µs
6. AD Converter Characteristics at Ta=-30°C to + 70°C, VSS1=VSS2=VSS3=0V
Parameter
Symbol
Resolution
N
Absolute precision
ET
Conversion time
TCAD
Pins
AN0(P80)
–AN7(P87)
AN8(P70)
AN9(P71)
AN10(XT1)
AN11(XT2)
Conditions
Ratings
VDD[V]
min.
3.0–6.0
typ.
max.
8
unit
bit
(Note2)
3.0-6.0
AD conversion time
= 32 × tCYC
(ADCR2=0)
(Note 3)
4.0-6.0
15.62
(tCYC=
0.488µs)
±1.5
97.92
(tCYC=
3.06µs)
3.0-6.0
23.52
(tCYC=
0.735µs)
97.92
(tCYC=
3.06µs)
AD conversion time
= 64 × tCYC
(ADCR2=1)
(Note 3)
4.5-6.0
18.82
(tCYC=
0.294µs)
97.92
(tCYC=
1.53µs)
3.0-6.0
47.04
(tCYC=
0.735µs)
97.92
(tCYC=
1.53µs)
3.0-6.0
VSS
VDD
V
1
µA
Analog input
voltage range
VAIN
Analog port input
current
IAINH
VAIN=VDD
3.0-6.0
IAINL
VAIN=VSS
3.0-6.0
LSB
µs
-1
(Note 2) Absolute precision does not include quantizing error (±1/2 LSB).
(Note 3) Conversion time means time from executing AD conversion instruction to loading complete digital value to register.
No.6719-17/24
LC877264A/56A/48A
7. Current Consumption Characteristics at Ta=-30°C to +70°C, VSS1=VSS2=VSS3=0V
Parameter
Symbol
Current consumption IDDOP(1)
during normal
operation
(Note 4)
IDDOP(2)
IDDOP(3)
IDDOP(4)
IDDOP(5)
IDDOP(6)
IDDOP(7)
IDDOP(8)
Pins
Conditions
VDD1= •FmCF=10MHz
Ceramic resonator
VDD2=
oscillation
VDD3
•FsX’tal=32.768kHz
crystal oscillation
•System clock: CF
10MHz oscillation
•Internal RC oscillation
stopped.
•Divider : 1/1
•CF1=20MHz external
clock
•FsX’tal=32.768kHz
crystal oscillation
•System clock: CF1
oscillation
•Internal RC oscillation
stopped.
•Divider :1/2
•FmCF=4MHz Ceramic
resonator oscillation
•FsX’tal=32.768kHz
crystal oscillation
•System clock: CF
4MHz oscillation
•Internal RC oscillation
stopped.
•Divider :1/1
•FmCF=0Hz (No
oscillation)
•FsX’tal=32.768kHz
crystal oscillation
•System clock: RC
oscillation
•Divider :1/2
•FmCF=0Hz (No
oscillation)
•FsX’tal=32.768kHz
crystal oscillation
•System clock:
32.768kHz
•Internal RC oscillation
stopped.
•Divider :1/2
Ratings
typ.
max
4.5–6.0
12.5
30
4.5–6.0
14
31
4.5–6.0
5.8
17
2.5–4.5
2.7
11
4.5–6.0
1
10
2.5–4.5
0.5
6
4.5–6.0
40
140
2.5–4.5
16
60
VDD[V]
min.
unit
mA
µA
Continued/
No.6719-18/24
LC877264A/56A/48A
Parameter
Current
consumption
during
HALT mode
(Note 4)
Symbol
Pins
Conditions
Ratings
VDD[V]
min.
typ.
max.
IDDHALT(1) VDD1= HALT mode
VDD2= •FmCF=10MHz Ceramic
resonator oscillation
VDD3
•FsX’tal=32.768kHz
crystal oscillation
•System clock :
CF 10MHz oscillation
•Internal RC oscillation
stopped.
•Divider: 1/1
4.5–6.0
5
12
IDDHALT(2)
HALT mode
•CF1=20MHz for external
clock
•FsX’tal=32.768kHz
crystal oscillation
•System clock :
CF1 oscillation
•Internal RC oscillation
stopped.
•Divider :1/2
4.5–6.0
6
13
IDDHALT(3)
HALT mode
•FmCF=4MHz Ceramic
resonator oscillation
•FsX’tal=32.768kHz
crystal oscillation
•System clock :
CF 4MHz oscillation
•Internal RC oscillation
stopped.
•Divider: 1/1
IDDHALT(4)
IDDHALT(5)
IDDHALT(6)
IDDHALT(7)
IDDHALT(8)
HALT mode
•FmCF=0Hz
(Oscillation stop)
•FsX’tal=32.768kHz
crystal oscillation
•System clock :
RC oscillation
•Divider: 1/2
HALT mode
•FmCF=0Hz
(Oscillation stop)
•FsX’tal=32.768kHz
crystal oscillation
•System clock : 32.768kHz
•Internal RC oscillation
stopped.
•Divider: 1/2
4.5–6.0
2.2
6
2.5–4.5
1.2
5
4.5–6.0
500
1600
2.5–4.5
250
1300
4.5–6.0
25
100
2.5–4.5
12
60
unit
mA
µA
Continued/
No.6719-19/24
LC877264A/56A/48A
Parameter
Symbol
Pins
Conditions
Current consumption IDDHOLD(1)
during HOLD mode IDDHOLD(2)
VDD1
HOLD mode
•CF1=VDD or open
(when using external
clock)
Current consumption IDDHOLD(3)
during Date/time
IDDHOLD(4)
clock HOLD mode
VDD1
Date/time clock HOLD
mode
•CF1=VDD or open
(when using external
clock)
•FmX’tal=32.768kHz
crystal oscillation
Ratings
VDD[V]
min.
typ.
max.
4.5–6.0
0.015
25
2.5–4.5
0.015
20
4.5–6.0
20
90
2.5–4.5
8
50
unit
µA
(Note 4) The currents through the output transistors and the pull-up MOS transistors are ignored.
No.6719-20/24
LC877264A/56A/48A
Main system clock oscillation circuit characteristics
The characteristics in the table bellow is based on the following conditions:
1. Use the standard evaluation board SANYO has provided.
2. Use the peripheral parts with indicated value externally.
3. The peripheral parts value is a recommended value of oscillator manufacturer
Table 1. Main system clock oscillation circuit characteristics using ceramic resonator
Frequency
Manufacturer
C1
10MHz
Murata
CSA10.0MTZ
CST10.0MTW
4MHz
Murata
CSA4.00MG
CST4.00MGW
Oscillation
stabilizing time
Operating
supply voltage
range
Rd1
Circuit parameters
Oscillator
33pF
C2
typ
33pF 470Ω
4.5 – 6.0V
0.06ms
0.3ms
(30pF) (30pF) 470Ω
4.5 – 6.0V
0.06ms
0.3ms
33pF 680Ω
2.5 – 6.0V
0.05ms
0.2ms
(30pF) (30pF) 680Ω
2.5 – 6.0V
0.05ms
0.2ms
33pF
Notes
max
Built in C1,C2
Built in C1,C2
The oscillation stabilizing time is a period until the oscillation becomes stable after VDD becomes higher than minimum
operating voltage. (Refer to Figure4)
Subsystem clock oscillation circuit characteristics
The characteristics in the table bellow is based on the following conditions:
1. Use the standard evaluation board SANYO has provided.
2. Use the peripheral parts with indicated value externally.
3. The peripheral parts value is a recommended value of oscillator manufacturer
Table 2. Subsystem clock oscillation circuit characteristics using crystal oscillator
Frequency
Manufacturer
Circuit parameters
Oscillator
C3
32.768MHz
Seiko EPSON
C-002RX
18pF
C4
Rf
Rd2
18pF OPEN 390kΩ
Operating
supply voltage
range
2.5 – 6.0V
Oscillation
stabilizing time
typ
max
1.0s
3.0s
Notes
MC-306
The oscillation stabilizing time is a period until the oscillation becomes stable after executing the instruction which starts the
sub-clock oscillation or after releasing the HOLD mode. (Refer to Figure4)
(Notes) • Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to
the oscillation pins as possible with the shortest possible pattern length.
CF1
CF2
XT1
Rd1
XT2
Rf
Rd2
C1
CF
C2
C4
C3
X’tal
Figure 1
Ceramic oscillation circuit
Figure 2
Crystal oscillation circuit
No.6719-21/24
LC877264A/56A/48A
0.5VDD
Figure 3
AC timing measurement point
VDD
Power Supply
VDD limit
0V
Reset time
RES
Internal RC
Resonator oscillation
tmsCF
CF1,CF2
tmsXtal
XT1,XT2
Operation mode
Reset
Unfixed
Instruction execution mode
Reset time and oscillation stable time
HOLD release signal
Without HOLD
Release signal
HOLD release signal VALID
Internal RC
Resonator oscillation
tmsCF
CF1,CF2
tmsXtal
XT1,XT2
Operation mode
HOLD
HALT
HOLD release signal and oscillation stable time
Figure 4
Oscillation stabilizing time
No.6719-22/24
LC877264A/56A/48A
VDD
(Note)
Select CRES and RRES value to assure that at least
200µs reset time is generated after the VDD becomes
higher than the minimum operating voltage.
RRES
RES
CRES
Figure 5
Reset circuit
SIOCLK
DATAIN
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DATAOUT
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DI7
DI8
DO7
DO8
Data RAM
transmission period
(only SIO0)
tSCK
tSCKL
tSCKH
SIOCLK
tsDI
thDI
DATAIN
tdDO
DATAOUT
Data RAM
transmission period
(only SIO0)
tSCKLA
tSCKHA
SIOCLK
tsDI
thDI
DATAIN
tdDO
DATAOUT
Figure 6
Serial input / output wave form
No.6719-23/24
LC877264A/56A/48A
tPIL
tPIH
Figure 7
Pulse input timing
VDD
SW : ON/OFF(programmable)
4R
SW : ON(VLCD=VDD)
VLCD
2R
2/3VLCD
R
1/2VLCD
R
1/3VLCD
2R
GND
Figure 8
LCD bias resistor
PS No.6719-24/24