MAXIM MAX97002

19-5111; Rev 0; 1/10
TION KIT
EVALUA BLE
IL
AVA A
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifiers
Features
The MAX97002 mono audio subsystem combines a
mono speaker amplifier with a stereo headphone amplifier and an analog DPST switch. The headphone and
speaker amplifiers have independent volume control and
on/off control. The 4 inputs are configurable as 2 differential inputs or 4 single-ended inputs.
S 2.7V to 5.5V Speaker Supply Voltage
The entire subsystem is designed for maximum efficiency. The high-efficiency, 700mW, Class D speaker
amplifier operates directly from the battery and consumes no more than 1FA in shutdown mode. The Class
H headphone amplifier utilizes a dual-mode charge
pump to maximize efficiency while outputting a groundreferenced signal that does not require output coupling
capacitors.
S Low-Emission Class D Amplifier
The speaker amplifier incorporates a distortion limiter to
automatically reduce the volume level when excessive
clipping occurs. This allows high gain for low-level signals without compromising the quality of large signals.
S 1.6V to 2V Headphone Supply Voltage
S 700mW Speaker Output (VPVDD = 3.7V,
ZSPK = 8ω + 68µH)
S 37mW/Channel Headphone Output (RHP = 16I)
S Efficient Class H Headphone Amplifier
S Ground-Referenced Headphone Outputs
S 2 Stereo Single-Ended/Mono Differential Inputs
S Integrated Distortion Limiter (Speaker Outputs)
S Integrated DPST Analog Switch
S No Clicks and Pops
S TDMA Noise Free
S 2mm x 2.5mm, 20-Bump, 0.5mm Pitch WLP
Package
All control is performed using the 2-wire I2C interface.
The MAX97002 operates over the extended -40NC to
+85NC temperature range, and is available in the 2mm x
2.5mm, 20-bump, WLP package (0.5mm pitch).
Applications
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX97002EWP+
-40NC to +85NC
20 WLP
Cell Phones
Portable Media Players
Simplified Block Diagram
1.8V
I2C
BATTERY
POWER SUPPLY
CONTROL
MAX97002
STEREO/
MONO
INPUT
VOLUME
CLASS H
AMPLIFIER
CHARGE
PUMP
STEREO/
MONO
INPUT
LIMITER
VOLUME
CLASS D
AMPLIFIER
BYPASS
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX97002
General Description
MAX97002
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifiers
TABLE OF CONTENTS
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Functional Diagram/Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Digital I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
I2 C TIMING Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Signal Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Class D Speaker Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Ultra-Low EMI Filterless Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Distortion Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Headphone Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DirectDrive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Class H Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Low-Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
I2C Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
I2C Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Volume Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Distortion Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Charge-Pump Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
I2C Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Bit Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
START and STOP Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Charge-Pump Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifiers
Early STOP Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Write Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Read Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Filterless Class D Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
RF Susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Optional Ferrite Bead Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Input Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Charge-Pump Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Charge-Pump Flying Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Charge-Pump Holding Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Supply Bypassing, Layout, and Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
WLP Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3
MAX97002
TABLE OF CONTENTS (CONTINUED)
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifiers
MAX97002
Functional Diagram/Typical Application Circuit
1.6V TO 2V
2.7V TO 5.5V
1µF
PGAINA
-6dB TO +18dB
INA1 C1
VDD
PVDD
B4
D4
10µF
BIAS
INADIFF
OPTIONAL
1µF
HPVDD
LPMODE
HPLVOL:
-64dB TO +6dB
0.47µF
INA2 C2
+
HPVSS
HPLMIX
HPVDD
OPTIONAL
HPRVOL:
-64dB TO +6dB
INB1 D1
INBDIFF
PVDD
SPKVOL:
-30dB TO +20dB
INB2 D2
C5 OUTP
CLASS D
+12dB
MIX
PGAINB
-6dB TO +18dB
0.47µF
HPVSS
HPRMIX
OPTIONAL
A1 HPR
CLASS H
0/3dB
HPREN
MIX
PGAINB
-6dB TO +18dB
0.47µF
A2 HPL
CLASS H
0/3dB
HPLEN
MIX
PGAINA
-6dB TO +18dB
D5 OUTN
SPKEN
SPKMIX
PGND
+
THD LIMITER
OPTIONAL
LMTEN
ANALOG SWITCHES
COM1 C3
COM2 D3
VDD
BYPEN
SDA B2
SCL B3
I2C
INTERFACE
VDD
MAX97002
C4
GND
4
B1 BIAS
MUX
0.47µF
0.1µF
CHARGE PUMP
A4
A5
B5
A3
C1P
C1N
HPVDD
HPVSS
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifiers
(Voltages with respect to GND.)
VDD, HPVDD.........................................................-0.3V to +2.2V
PVDD.....................................................................-0.3V to +6.0V
HPVSS...................................................................-2.2V to +0.3V
C1N...................................... (HPVSS - 0.3V) to (HPVDD + 0.3V)
C1P....................................................... -0.3V to (HPVDD + 0.3V)
HPL, HPR............................. (HPVSS - 0.3V) to (HPVDD + 0.3V)
INA1, INA2, INB1, INB2, BIAS..............................-0.3V to +6.0V
SDA, SCL..............................................................-0.3V to +6.0V
COM1, COM2, OUTP, OUTN..................-0.3V to (PVDD + 0.3V)
Continuous Current In/Out of PVDD, GND, OUT_......... Q800mA
Continuous Current In/Out of HPR, HPL, VDD.............. Q140mA
Continuous Current In/Out of COM1, COM2................. Q150mA
Continuous Input Current (all other pins)......................... Q20mA
Duration of OUT_ Short Circuit to GND or PVDD......Continuous
Duration of Short Circuit Between
OUTP and OUTN....................................................Continuous
Duration of HP_ Short Circuit to GND or VDD. ..........Continuous
Continuous Power Dissipation (TA = +70NC)
20-Bump WLP Multilayer Board
(derate 13mW/NC above +70NC)................................1040mW
Junction Temperature......................................................+150NC
Operating Temperature Range........................... -40NC to +85NC
Storage Temperature Range............................. -65NC to +150NC
Lead Temperature (soldering, 10s).................................+260NC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VVDD = 1.8V, VPVDD = 3.7V, VGND = 0V. Input signal applied at INA configured single-ended, preamp gain = 0dB, HPLVOL =
HPRVOL = SPKVOL = 0dB, speaker loads (ZSPK) connected between OUTP and OUTN. Headphone loads (RHP) connected from
HPL or HPR to GND. SDA and SCL pullup voltage = 1.8V. ZSPK = J, RHP = J. CC1P-C1N = CHPVDD = CHPVSS = CBIAS = 1FF.
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1)
PARAMETER
Speaker Amplifier Supply
Voltage Range
Headphone Amplifier Supply
Voltage Range
SYMBOL
CONDITIONS
MIN
2.7
5.5
V
VDD
Guaranteed by PSRR test
1.6
2
V
HP mode, TA = +25NC,
stereo SE input on INA,
INB disabled
SPK mode, TA = +25NC
mono differential Input on
INB, INA disabled
SPK + HP mode, TA =
+25NC, stereo SE input on
INA, INB disabled
IVDD
1.35
1.85
IPVDD
0.35
0.55
IVDD
1.35
1.85
IPVDD
0.75
1.15
IVDD
0.32
0.6
IPVDD
1.38
2.2
IVDD
1.35
1.85
1.8
2.7
0
8
IPVDD
IVDD + IPVDD
ISHDN
TA = +25NC, VSHDN = 0V
VVDD = 0V,
IPVDD
tON
Time from power-on to full operation,
including soft-start
RIN
TA = +25NC,
internal gain
mA
FA
<1
10
Gain = -6dB, -3dB
Input Resistance
UNITS
Guaranteed by PSRR test
Quiecsent Supply Current
Turn-On Time
MAX
PVDD
Low-power headphone
mode, TA = +25NC
Shutdown Current
TYP
ms
41.2
Gain = 0dB, 3dB,
6dB, dB
16
20.6
27
Gain = 18dB
5.5
7.2
9.6
kI
5
MAX97002
ABSOLUTE MAXIMUM RATINGS
MAX97002
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifiers
ELECTRICAL CHARACTERISTICS (continued)
(VVDD = 1.8V, VPVDD = 3.7V, VGND = 0V. Input signal applied at INA configured single-ended, preamp gain = 0dB, HPLVOL =
HPRVOL = SPKVOL = 0dB, speaker loads (ZSPK) connected between OUTP and OUTN. Headphone loads (RHP) connected from
HPL or HPR to GND. SDA and SCL pullup voltage = 1.8V. ZSPK = J, RHP = J. CC1P-C1N = CHPVDD = CHPVSS = CBIAS = 1FF.
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1)
PARAMETER
Feedback Resistance
SYMBOL
RF
CONDITIONS
TA = +25NC, external gain
MIN
TYP
MAX
UNITS
19
20
21
kI
Preamp = 0dB
Maximum Input Signal Swing
2.3
Preamp = +18dB
0.29
Preamp = external gain
Common-Mode Rejection
Ratio
Input DC Voltage
Bias Voltage
CMRR
VBIAS
VP-P
2.3 x
RINEX/RF
f = 1kHz (differential input mode),
gain = 0dB
55
f = 1kHz (differential input mode),
gain = 18dB
32
dB
IN__ inputs
1.125
1.2
1.275
V
1.13
1.2
1.27
V
TA = +25NC, SPKM = 1
Q0.5
Q4
TA = +25NC, SPKMIX = 0x01, IN_DIFF = 0
Q1.5
SPEAKER AMPLIFIER
Output Offset Voltage
Click-and-Pop Level
VOS
KCP
Peak voltage, TA =
+25NC, A-weighted,
32 samples per second, volume at mute
(Note 2)
Into shutdown
Output Power (Note 3)
Total Harmonic Distortion
Plus Noise
Signal-to-Noise Ratio
6
PSRR
THD+N
SNR
TA = +25NC
-70
dBV
Out of shutdown
VPVDD = 2.7V to
5.5V
Power-Supply Rejection Ratio
(Note 2)
-70
50
77
f = 217Hz,
200mVP-P ripple
73
f = 1kHz,
200mVP-P ripple
73
f = 20kHz,
200mVP-P ripple
57
dB
VPVDD = 4.2V
920
VPVDD = 3.7V
700
VPVDD = 3.3V
550
f = 1kHz, POUT = 360mW, TA = +25NC,
RSPK = 8I
0.05
0.6
THD+N P 1%,
f = 1kHz,
ZSPK = 8I + 68FH
A-weighted,
SPKMIX = 0x03, referenced to 700mW
mV
mW
IN_DIFF = 0
(single-ended)
96
IN_DIFF = 1
(differential)
96
%
dB
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifiers
(VVDD = 1.8V, VPVDD = 3.7V, VGND = 0V. Input signal applied at INA configured single-ended, preamp gain = 0dB, HPLVOL =
HPRVOL = SPKVOL = 0dB, speaker loads (ZSPK) connected between OUTP and OUTN. Headphone loads (RHP) connected from
HPL or HPR to GND. SDA and SCL pullup voltage = 1.8V. ZSPK = J, RHP = J. CC1P-C1N = CHPVDD = CHPVSS = CBIAS = 1FF.
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1)
PARAMETER
MIN
TYP
MAX
UNITS
250
kHz
Q20
kHz
11.5
12
12.5
dB
1.5
A
Efficiency
E
POUT = 600mW, f = 1kHz
87
%
Output Noise
A-weighted, (SPKMIX = 0x01),
IN_DIFF = 1, SPKVOL = -30dB
37
FVRMS
VHPL = VHPR = 0V, TA = +25NC
80
83
85
Oscillator Frequency
SYMBOL
CONDITIONS
fOSC
Spread-Spectrum Bandwidth
Gain
Current Limit
CHARGE PUMP
Charge-Pump Frequency
Positive Output Voltage
VHPVDD
Negative Output Voltage
VHPVSS
Headphone Output Voltage
Threshold
Mode Transition Timeouts
VHPL = VHPR = 0.2V
VHPL = VHPR = 0.5V
665
VHPL, VHPR > VTH
VDD
VHPL, VHPR < VTH
VDD/2
VHPL, VHPR > VTH
VHPL, VHPR < VTH
-VDD
kHz
500
V
V
-VDD/2
VTH1
Output voltage at which the charge pump
switches between fast and slow clock
QVDD
x 0.05
QVDD
x 0.08
QVDD
x 0.13
VTH2
Output voltage at which the charge pump
switches modes, VOUT rising or falling
QVDD
x 0.21
QVDD
x 0.25
QVDD
x 0.3
V
Time it takes for the charge pump to transition from Invert to split mode
32
ms
Time it takes for the charge pump to transition from split to invert mode
20
Fs
HEADPHONE AMPLIFIERS
Output Offset Voltage
Click-and-Pop Level
VOS
KCP
TA = +25NC, volume at mute
Q0.15
Q0.6
TA = +25NC, HP_MIX = 0x1, IN_DIFF = 0
Q0.5
Peak voltage, TA =
+25NC, A-weighted, 32
samples per second,
volume at mute (Note 2)
-74
Into shutdown
Out of shutdown
mV
dBV
-74
7
MAX97002
ELECTRICAL CHARACTERISTICS (continued)
MAX97002
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifiers
ELECTRICAL CHARACTERISTICS (continued)
(VVDD = 1.8V, VPVDD = 3.7V, VGND = 0V. Input signal applied at INA configured single-ended, preamp gain = 0dB, HPLVOL =
HPRVOL = SPKVOL = 0dB, speaker loads (ZSPK) connected between OUTP and OUTN. Headphone loads (RHP) connected from
HPL or HPR to GND. SDA and SCL pullup voltage = 1.8V. ZSPK = J, RHP = J. CC1P-C1N = CHPVDD = CHPVSS = CBIAS = 1FF.
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1)
PARAMETER
Power-Supply Rejection Ratio
(Note 2)
Output Power
SYMBOL
PSRR
POUT
Channel-to-Channel Gain
Tracking
Total Harmonic Distortion
Plus Noise
THD+N
Signal-to-Noise Ratio
SNR
CONDITIONS
TA = +25NC
THD+N = 1%, f = 1kHz
MIN
TYP
MAX
VDD = 1.62V to
1.98V
70
85
f = 217Hz,
VRIPPLE =
200mVP-P
84
f = 1kHz,
VRIPPLE =
200mVP-P
80
f = 20kHz,
VRIPPLE =
200mVP-P
69
UNITS
dB
37
RHP = 16I
mW
30
Q0.3
Q2.5
RHP = 32I
0.02
RHP = 16I
0.03
0.1
A-weighted, RHP = 16I, HPLMIX = 0x01,
HPRMIX = 0x02, IN_DIFF = 0
100
dB
RHP = 32I
TA = +25NC, HPL to HPR, HPLMIX = 0x01,
HPRMIX = 0x02, IN_DIFF = 0
POUT = 10mW, f = 1kHz
%
%
Slew Rate
SR
0.35
V/Fs
Capacitive Drive
CL
200
pF
HPL to HPR, HPR to HPL, f = 20Hz to
20kHz
68
dB
TA = +25NC
1.6
4
TA = TMIN to
TMAX
5.2
10I in series
with each
switch
0.05
No series
resistors
0.3
90
Crosstalk
ANALOG SWITCH
On-Resistance
Total Harmonic Distortion
Plus Noise
Off-Isolation
8
RON
THD+N
INC_ = 20mA, VCOM_ =
0V and PVDD, SWEN = 1
VDIFCOM_ = 2VP-P,
VCMCOM_= PVDD/2,
f = 1kHz, SWEN = 1,
ZSPK = 8I + 68FH
SWEN = 0, COM1 and COM2 to GND = 50I,
f = 10kHz, referred to signal applied to
OUTP and OUTN
I
%
dB
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifiers
(VVDD = 1.8V, VPVDD = 3.7V, VGND = 0V. Input signal applied at INA configured single-ended, preamp gain = 0dB, HPLVOL =
HPRVOL = SPKVOL = 0dB, speaker loads (ZSPK) connected between OUTP and OUTN. Headphone loads (RHP) connected from
HPL or HPR to GND. SDA and SCL pullup voltage = 1.8V. ZSPK = J, RHP = J. CC1P-C1N = CHPVDD = CHPVSS = CBIAS = 1FF.
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
PGAIN_ = 000
-6.5
-6
-5.5
PGAIN_ = 001
-3.5
-3
-2.5
PGAIN_ = 010
-0.5
0
+0.5
PGAIN_ = 011
2.5
3
3.5
PGAIN_ = 100
5.5
6
6.5
PGAIN_ = 101
8.5
9
9.5
PGAIN_ = 110
17.5
18
18.5
UNITS
PREAMPLIFIER
Gain
dB
VOLUME CONTROL
Volume Level
HP_VOL = 0x1F
5.5
6
6.5
HP_VOL = 0x00
-68
-64
-60
SPKVOL = 0x3F
19
20
21
-30
-29
SPKVOL = 0x00
-31
Speaker
100
Headphone
110
Mute Attenuation
f = 1kHz
Zero-Crossing Detection
Timeout
1
THDT1 = 0
1.4
THDT1 = 1 2.8
dB
dB
100
ms
LIMITER
Attack Time
Release Time Constant
ms
s
DIGITAL I/O CHARACTERISTICS
(VPVDD = 3.7V, VGND = 0V. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
0.75 x
VDD
V
0.35 x
VDD
V
200
mV
10
pF
±1.0
FA
0.4
V
DIGITAL INPUTS (SDA, SCL)
Input Voltage High
VIH
Input Voltage Low
VIL
Input Hysteresis
VHYS
Input Capacitance
CIN
Input Leakage Current
IIN
TA = +25NC
DIGITAL OUTPUTS (SDA Open Drain)
Output Low Voltage
VOL
ISINK = 3mA
9
MAX97002
ELECTRICAL CHARACTERISTICS (continued)
MAX97002
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifiers
I2C TIMING CHARACTERISTICS
(VPVDD = 3.7V, VGND = 0V. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
400
kHz
Serial-Clock Frequency
fSCL
0
Bus Free Time Between STOP
and START Conditions
tBUF
1.3
Fs
Hold Time (Repeated) START
Condition
tHD,STA
0.6
Fs
SCL Pulse-Width Low
tLOW
1.3
Fs
SCL Pulse-Width High
tHIGH
0.6
Fs
Setup Time for a REPEATED
START Condition
tSU,STA
0.6
Fs
Data Hold Time
tHD,DAT
0
Data Setup Time
tSU,DAT
100
900
ns
ns
SDA and SCL Receiving Rise
Time
tR
(Note 4)
20 +
0.1CB
300
ns
SDA and SCL Receiving Fall
Time
tF
(Note 4)
20 +
0.1CB
300
ns
SDA Transmitting Fall Time
tF
(Note 4)
20 +
0.1CB
300
ns
400
pF
50
ns
Setup Time for STOP Condition
tSU,STO
Bus Capacitance
CB
Pulse Width of Suppressed
Spike
tSP
Note
Note
Note
Note
1:
2:
3:
4:
0.6
0
100% production tested at TA = +25NC. Specifications over temperature limits are guaranteed by design.
Amplifier inputs are AC-coupled to GND.
Class D amplifier testing performed with a resistive load in series with an inductor to simulate an actual speaker load.
CB is in pF.
CLOCK PULSE FOR
ACKNOWLEDGMENT
START
CONDITION
SCL
1
28
9
NOT ACKNOWLEDGE
SDA
ACKNOWLEDGE
Figure 1. I2C Interface Timing Diagram
10
Fs
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifiers
SHUTDOWN CURRENT
vs. SUPPLY VOLTAGE
2
1
3.0
2.5
2.0
1.5
1.0
0.5
0
4.0
4.5
5.0
2.5
3.0
3.5
SUPPLY VOLTAGE (V)
4.0
4.5
5.0
0
-10
-20
-30
10
0
5.5
RIGHT AND LEFT
32I LOAD
-10
THD+N vs. FREQUENCY
VPVDD = 3.7V
ZSPRK = 8I + 68µF
1
THD+N (%)
-20
-30
-40
30
40
50
60
70
THD+N vs. FREQUENCY
POUT = 600mW
0.1
0.01
-50
20
VOLUME CONTROL CODE (NUMERIC)
10
MAX97002 toc04
10
VPVDD = 3.7V
ZSPRK = 4I + 33µF
1
POUT = 1000mW
0.1
POUT = 200mW
0.01
POUT = 200mW
-60
0.001
5
10
15
20
25
HP_VOL CODE (NUMERIC)
30
0.001
0.01
35
0.1
SSM
0.01
10
1
FREQUENCY (kHz)
10
0.1
fIN = 1kHz
0.1
100
400
800
100
1200
POUT (mW)
1600
VPVDD = 5.0V
ZSPRK = 4I + 33µF
10
10
100
fIN = 6kHz
1
fIN = 1kHz
0.1
fIN = 100Hz
0.01
fIN = 100Hz
0
1
THD+N vs. OUTPUT POWER
fIN = 6kHz
1
0.001
0.001
0.1
0.01
FREQUENCY (kHz)
VPVDD = 5.0V
ZSPRK = 8I + 68µF
0.01
FFM
0.01
100
THD+N vs. OUTPUT POWER
THD+N (%)
1
10
100
MAX97002 toc07
VPVDD = 3.7V
ZSPRK = 8I + 68µF
1
FREQUENCY (kHz)
THD+N vs. FREQUENCY
10
0.1
THD+N (%)
0
2000
2400
MAX97002 toc09
-70
MAX97002 toc08
HEADPHONE VOLUME ATTENUATION (dB)
10
THD+N (%)
10
SUPPLY VOLTAGE (V)
HEADPHONE VOLUME ATTENUATION
vs. HP_VOL CODE
0
8I LOAD
20
-40
0
5.5
THD+N (%)
3.5
MAX97002 toc05
3.0
2.5
MAX97002 toc03
3.5
30
MAX97002 toc06
3
INPUTS AC-COUPLED TO GND
VSDA = VSCL = 3.3V
SPEAKER VOLUME ATTENUATION (dB)
4
4.0
SHUTDOWN CURRENT (µA)
SPEAKER ONLY
INPUTS AC-COUPLED TO GND
INPUT = INA
VSDA = VSCL = 3.3V
5
SUPPLY CURRENT (mA)
MAX97002 toc01
6
SPEAKER VOLUME ATTENUATION
vs. VOLUME CONTROL CODE
MAX97002 toc02
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
0.001
0
500 1000 1500 2000 2500 3000 3500 4000
POUT (mW)
11
MAX97002
Typical Operating Characteristics
(VLDOIN = VPVDD = 3.7V, VGND = VPGND = 0V. Single-ended inputs, preamp gain = 0dB, HPLVOL = HPRVOL = SPKVOL = 0dB. Speaker
loads (ZSPK) connected between OUTP and OUTN. Headphone loads (RHP) connected from HPL or HPR to GND. ZSPK = ∞, RHP = ∞.
CC1P-C1N = CHPVDD = CHPVSS = CBIAS = 1μF. TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(VLDOIN = VPVDD = 3.7V, VGND = VPGND = 0V. Single-ended inputs, preamp gain = 0dB, HPLVOL = HPRVOL = SPKVOL = 0dB. Speaker
loads (ZSPK) connected between OUTP and OUTN. Headphone loads (RHP) connected from HPL or HPR to GND. ZSPK = ∞, RHP = ∞.
CC1P-C1N = CHPVDD = CHPVSS = CBIAS = 1μF. TA = +25°C, unless otherwise noted.)
THD+N vs. OUTPUT POWER
fIN = 1kHz
0.1
fIN = 100Hz
0.01
500
1000
2000
2500
3000
0
80
70
ZSPRK = 4I + 33µF
60
50
40
0
1200
1600
2000
0
0.5
1.0
OUTPUT POWER vs. SUPPLY VOLTAGE
1.0
0.8
THD+N = 1%
0.4
0.2
0
4.0
4.5
SUPPLY VOLTAGE (V)
12
0
0.2
0.4
0.6
2.5
THD+N = 10%
2.0
1.5
THD+N = 1%
1.0
5.0
5.5
0.8
1.0
1.2
1.4
1.6
OUTPUT POWER vs. LOAD RESISTANCE
2.0
VPVDD = 3.7V
fIN = 1kHz
ZSPRK = LOAD + 68µF
1.8
1.6
1.4
THD+N = 10%
1.2
1.0
0.8
0.6
THD+N = 1%
0.4
0.2
0
0
3.5
VPVDD = 3.7V
fIN = 1kHz
0
2.5
0.5
3.0
40
POUT (W)
fIN = 1kHz
ZSPRK = 4I + 33µF
3.0
OUTPUT POWER (W)
THD+N = 10%
2.5
50
OUTPUT POWER vs. SUPPLY VOLTAGE
1.4
0.6
2.0
OUTPUT POWER (W)
fIN = 1kHz
ZSPRK = 8I + 68µF
1.2
1.5
3.5
MAX97002 toc16
2.0
1.6
ZSPRK = 4I + 33µF
60
POUT (W)
POUT (mW)
1.8
70
10
MAX97002 toc17
800
1200
20
VPVDD = 5.0V
fIN = 1kHz
10
400
1000
30
20
0.001
800
80
30
fIN = 100Hz
600
ZSPRK = 8I + 68µF
90
EFFICIENCY (%)
fIN = 1kHz
ZSPRK = 8I + 68µF
90
EFFICIENCY (%)
fIN = 6kHz
0
400
EFFICIENCY vs. OUTPUT POWER
100
MAX97002 toc14
100
MAX97002 toc13
VPVDD = 3.7V
ZSPRK = 4I + 33µF
0.01
200
POUT (mW)
EFFICIENCY vs. OUTPUT POWER
THD+N vs. OUTPUT POWER
0.1
1500
POUT (mW)
100
1
fIN = 100Hz
0.001
0
POUT (mW)
10
fIN = 1kHz
0.1
0.01
0.001
200 400 600 800 1000 1200 1400 1600
1
MAX97002 toc15
fIN = 100Hz
0.001
THD+N (%)
fIN = 6kHz
1
MAX97002 toc18
0.01
0
10
THD+N (%)
THD+N (%)
fIN = 1kHz
0.1
VPVDD = 3.7V
ZSPRK = 8I + 68µF
fIN = 6kHz
fIN = 6kHz
1
VPVDD = 4.2V
ZSPRK = 4I + 33µF
10
100
MAX97002 toc11
10
THD+N (%)
MAX97002 toc10
VPVDD = 4.2V
ZSPRK = 8I + 68µF
THD+N vs. OUTPUT POWER
100
MAX97002 toc12
THD+N vs. OUTPUT POWER
100
OUTPUT POWER (W)
MAX97002
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifiers
2.5
3.0
3.5
4.0
4.5
SUPPLY VOLTAGE (V)
5.0
5.5
1
10
100
LOAD RESISTANCE (I)
1000
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifiers
POWER-SUPPLY REJECTION RATIO
vs. SUPPLY VOLTAGE
VRIPPLE = 200mVP-P
fIN = 1kHz
INPUTS AC-COUPLED GND
-20
-40
PSRR (dB)
-40
-50
-60
-60
-40
-60
-80
-70
-100
-80
-90
-120
-100
-100
0.1
0.01
1
10
2.5
100
3.0
3.5
4.0
4.5
5.0
15
20
WIDEBAND OUTPUT SPECTRUM
IN-BAND OUTPUT SPECTRUM
FFM
fIN = 1kHz
-40
-60
-80
0
RBW = 100Hz
FFM
-20
OUTPUT AMPLITUDE (dBV)
MAX97002 toc22
0
AMPLITUDE (dBV)
10
FREQUENCY (kHz)
SUPPLY VOLTAGE (V)
FREQUENCY (kHz)
-20
5
0
5.5
MAX97002 toc23
-80
-40
-60
-80
-100
-100
-120
-120
5
10
15
20
0.1
1
10
100
FREQUENCY (kHz)
FREQUENCY (MHz)
WIDEBAND OUTPUT SPECTRUM
SOFTWARE SHUTDOWN RESPONSE
0
RBW = 100Hz
SSM
-10
-20
1000
MAX97002 toc25
MAX97002 toc24
0
OUTPUT AMPLITUDE (dBV)
PSRR (dB)
-30
SSM
fIN = 1kHz
-20
AMPLITUDE (dBV)
-20
IN-BAND OUTPUT SPECTRUM
0
MAX97002 toc20
VRIPPLE = 200mVP-P
VPVDD = 3.7V
INPUTS AC-COUPLED GND
-10
0
MAX97002 toc19
0
MAX97002 toc21
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY
SDA
2V/div
-30
-40
-50
-60
SPKR
OUTPUT
200mA/div
-70
-80
-90
-100
0.1
1
10
100
1000
1ms/div
FREQUENCY (MHz)
13
MAX97002
Typical Operating Characteristics (continued)
(VLDOIN = VPVDD = 3.7V, VGND = VPGND = 0V. Single-ended inputs, preamp gain = 0dB, HPLVOL = HPRVOL = SPKVOL = 0dB. Speaker
loads (ZSPK) connected between OUTP and OUTN. Headphone loads (RHP) connected from HPL or HPR to GND. ZSPK = ∞, RHP = ∞.
CC1P-C1N = CHPVDD = CHPVSS = CBIAS = 1μF. TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(VLDOIN = VPVDD = 3.7V, VGND = VPGND = 0V. Single-ended inputs, preamp gain = 0dB, HPLVOL = HPRVOL = SPKVOL = 0dB. Speaker
loads (ZSPK) connected between OUTP and OUTN. Headphone loads (RHP) connected from HPL or HPR to GND. ZSPK = ∞, RHP = ∞.
CC1P-C1N = CHPVDD = CHPVSS = CBIAS = 1μF. TA = +25°C, unless otherwise noted.)
THD+N vs. FREQUENCY
THD+N vs. FREQUENCY
RLOAD = 32I
THD+N (%)
SPKR
OUTPUT
200mA/div
0.1
RLOAD = 16I
1
POUT = 25mW
0.01
0.1
POUT = 10mW
0.01
POUT = 5mW
0.001
0.001
0.01
2ms/div
0.1
1
10
100
0.01
0.1
FREQUENCY (kHz)
RLOAD = 16I
1
THD+N (%)
fIN = 6kHz
MAX97002 toc30
10
MAX97002 toc29
1
fIN = 100Hz
0.01
10
THD+N vs. OUTPUT POWER
RLOAD = 32I
0.1
1
FREQUENCY (kHz)
THD+N vs. OUTPUT POWER
10
THD+N (%)
POUT = 30mW
THD+N (%)
1
SDA
2V/div
10
MAX97002 toc27
10
MAX97002 toc26
MAX97002 toc28
SOFTWARE TURN-ON RESPONSE
fIN = 6kHz
0.1
fIN = 100Hz
fIN = 1kHz
0.01
fIN = 1kHz
0.001
0.001
5
10
15
20
25
30
35
40
0
OUTPUT POWER (mW)
70
60
50
40
RLOAD = 32I
30
50
60
70
fIN = 1kHz
200
OUTPUT POWER (mW)
RLOAD = 16I
80
40
250
MAX97002 toc31
90
30
OUTPUT POWER vs. LOAD RESISTANCE
fIN = 1kHz
POUT = PHPL + PHPR
100
20
OUTPUT POWER (mW)
POWER DISSIPATION
vs. OUTPUT POWER
110
10
MAX97002 toc32
0
POWER DISSIPATION (mW)
MAX97002
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifiers
THD+N = 10%
150
100
THD+N = 1%
50
20
10
0
0
20
40
60
80
100
OUTPUT POWER (mW)
14
120
140
0
1
10
100
LOAD RESISTANCE (I)
1000
100
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifiers
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY
C1 = C2 = C3 = 2.2µF
C1 = C2 = C3 = 1µF
40
30
fIN = 1kHz
THD+N = 1%
MEASURED AT
HPR ONLY
10
0
10
1
100
1000
-60
-80
-120
-120
-140
-140
0.01
0.1
1
10
0
100
2
4
8
10 12 14 16 18 20
CROSSTALK vs. FREQUENCY
0
MAX97002 toc36
RLOAD = 16I
fIN = 1kHz
6
FREQUENCY (kHz)
FREQUENCY (kHz)
OUTPUT SPECTRUM
-40
-10
-60
-80
-100
RLOAD = 32I
-20
CROSSTALK (dB)
AMPLITUDE (dBV)
-80
-100
0
-30
-40
-50
-60
LEFT TO RIGHT RIGHT TO LEFT
-70
-120
-80
-140
-90
2
0
4
6
8
10 12 14 16 18 20
0.01
0.1
1
10
100
FREQUENCY (kHz)
FREQUENCY (kHz)
COMMON-MODE REJECTION RATIO
vs. FREQUENCY
SOFTWARE SHUTDOWN RESPONSE
MAX97002 toc39
MAX97002 toc38
0
-60
-100
LOAD RESISTANCE (I)
-20
-40
MAX97002 toc37
20
AMPLITUDE (dBV)
PSRR (dB)
50
RLOAD = 32I
fIN = 1kHz
-20
-40
60
RLOAD = 32I
-10
CROSSTALK (dB)
OUTPUT POWER (W)
70
VRIPPLE = 200mVP-P
VDD = 1.8V
INPUTS AC-COUPLED GND
-20
OUTPUT SPECTRUM
0
MAX97002 toc34
80
0
MAX97002 toc33
90
MAX97002 toc35
OUTPUT POWER vs. LOAD RESISTANCE
-20
SDA
2V/div
PREGAIN = +18dB
-30
-40
PREGAIN = +9dB
HPL/HPR
200mV/div
PREGAIN = 0dB
-50
-60
-70
0.01
0.1
1
10
100
1ms/div
FREQUENCY (kHz)
15
MAX97002
Typical Operating Characteristics (continued)
(VLDOIN = VPVDD = 3.7V, VGND = VPGND = 0V. Single-ended inputs, preamp gain = 0dB, HPLVOL = HPRVOL = SPKVOL = 0dB. Speaker
loads (ZSPK) connected between OUTP and OUTN. Headphone loads (RHP) connected from HPL or HPR to GND. ZSPK = ∞, RHP = ∞.
CC1P-C1N = CHPVDD = CHPVSS = CBIAS = 1μF. TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(VLDOIN = VPVDD = 3.7V, VGND = VPGND = 0V. Single-ended inputs, preamp gain = 0dB, HPLVOL = HPRVOL = SPKVOL = 0dB. Speaker
loads (ZSPK) connected between OUTP and OUTN. Headphone loads (RHP) connected from HPL or HPR to GND. ZSPK = ∞, RHP = ∞.
CC1P-C1N = CHPVDD = CHPVSS = CBIAS = 1μF. TA = +25°C, unless otherwise noted.)
CLASS H OPERATION
MAX97002 toc40
THD+N vs. OUTPUT POWER
MAX97002 toc41
10
HPVDD
1V/div
SDA
2V/div
RLOAD = 8I
EXTERNAL CLASS AB
CONNECTED DIRECTLY
TO COM1 AND COMR
1
HPL/HPR
200mV/div
THD+N (%)
0V
MAX97002 toc42
SOFTWARE STARTUP RESPONSE
f = 6kHz
0.1
f = 100Hz
HPL/HPR
200mV/div 0V
f = 1kHz
0.01
HPVSS
1V/div
0.001
0
10ms/div
2ms/div
10
20
30
40
50
60
OUTPUT POWER (mW)
ON-RESISTANCE vs. VCOM
VPVDD = 2.7V
2.5
VPVDD = 3.0V
2.0
VPVDD = 3.7V
1.5
1.0
VPVDD = 5.0V
0.5
VPVDD = 5.5V
1
2
3
VCOM (V)
16
4
5
-20
-40
-60
-80
-100
0
0
MAX97002 toc44
VPVDD = 2.5V
OFF-ISOLATION (dB)
INC = 20mA
3.0
BYPASS SWITCH OFF-ISOLATION
0
MAX97002 toc43
3.5
RON (I)
MAX97002
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifiers
6
-120
0.01
0.1
1
FREQUENCY (kHz)
10
100
70
80
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifiers
TOP VIEW
(BUMP SIDE DOWN)
1
2
3
4
5
+
MAX97002
A
HPR
HPL
HPVSS
C1P
C1N
B
BIAS
SDA
SCL
VDD
HPVDD
C
INA1
INA2
COM1
GND
OUTP
D
INB1
INB2
COM2
PVDD
OUTN
Pin Description
PIN
NAME
A1
HPR
Headphone Amplifier Left Output
DESCRIPTION
A2
HPL
Headphone Amplifier Right Output
A3
HPVSS
A4
C1P
Charge-Pump Flying Capacitor Positive Terminal. Connect a 1FF capacitor between C1P and C1N.
A5
C1N
Charge-Pump Flying Capacitor Negative Terminal. Connect a 1FF capacitor between C1P and
C1N.
B1
BIAS
Common-Mode Bias. Bypass to GND with a 1FF capacitor.
B2
SDA
Serial-Data Input/Output. Connect a pullup resistor from SDA to DVDD.
B3
SCL
Serial-Clock Input. Connect a pullup resistor from SCL to DVDD.
B4
VDD
Headphone Amplifier Supply. Bypass with a 1FF capacitor to GND.
Headphone Amplifier Negative Power Supply. Bypass with a 1FF capacitor to GND.
B5
HPVDD
C1
INA1
Input A1. Left input or negative input.
C2
INA2
Input A2. Right input or positive input.
C3
COM1
Headphone Amplifier Positive Power Supply. Bypass with a 1FF capacitor to GND.
Positive Bypass Switch Input
C4
GND
Analog Ground
C5
OUTP
Positive Speaker Output
D1
INB1
Input B1. Left input or negative input.
D2
INB2
Input B2. Right input or positive input.
D3
COM2
Negative Bypass Switch Input
D4
PVDD
Class D Power Supply. Bypass with a 1FF capacitor to GND.
D5
OUTN
Negative Speaker Output
17
MAX97002
Pin Configuration
MAX97002
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifiers
Detailed Description
(Figure 2). The inputs can be configured for singleended or differential signals (Figure 3). The internal
preamplifiers feature programmable gain settings using
internal resistors and an external gain setting using a
trimmed internal feedback resistor. The external option
allows any desired gain to be selected. Following preamplification, the input signals are mixed, volume adjusted, and routed to the headphone and speaker amplifiers
based on the desired configuration.
The MAX97002 mono audio subsystem combines a
mono speaker amplifier with a stereo headphone amplifier and an analog DPST switch. The high-efficiency
700mW Class D speaker amplifier operates directly
from the battery and consumes no more than 1FA when
in shutdown mode. The headphone amplifier utilizes a
dual-mode charge pump and a Class H output stage
to maximize efficiency while outputting a ground-referenced signal that does not require output coupling
capacitors. The headphone and speaker amplifiers
have independent volume control and on/off control.
The 4 inputs are configurable as 2 differential inputs or
4 single-ended inputs. All control is performed using the
2-wire I2C interface.
Mixers
The MAX97002 features independent mixers for the left
headphone, right headphone, and speaker paths. Each
output can select any combination of any inputs. This
allows for mixing two audio signals together and routing independent signals to the headphone and speaker
amplifiers. If one of the inputs is not selected by either
mixer, it is automatically powered down to save power.
The speaker amplifier incorporates a distortion limiter to
automatically reduce the volume level when excessive
clipping occurs. This allows high gain for low-level signals without compromising the quality of large signals.
Class D Speaker Amplifier
The MAX97002 Class D speaker amplifier utilizes active
emissions limiting and spread-spectrum modulation to
minimize the EMI radiated by the amplifier.
Signal Path
The MAX97002 signal path consists of flexible inputs,
signal mixing, volume control, and output amplifiers
INA2
INA1
INPUT A
-6dB TO +18dB
MIXER
AND
MUX
INB2
INB1
Figure 2. Signal Path
18
-64dB TO +6dB
0/3dB
-64dB TO +6dB
0/3dB
-30dB TO +20dB
+12dB
INPUT B
-6dB TO +18dB
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifiers
MAX97002
STEREO SINGLE-ENDED
IN_2 (R)
R
TO MIXER
IN_1 (L)
L
DIFFERENTIAL
IN_2 (+)
IN_1 (-)
TO MIXER
Figure 3. Differential and Stereo Single-Ended Input Configurations
19
Ultra-Low EMI Filterless Output Stage
Traditional Class D amplifiers require the use of external LC filters or shielding in order to meet EN55022B
electromagnetic-interference (EMI) regulation standards. Maxim’s patented active emissions limiting edgerate control circuitry and spread-spectrum modulation
reduces EMI emissions, while maintaining up to 87% efficiency. Maxim’s patented spread-spectrum modulation
mode flattens wideband spectral components, while
proprietary techniques ensure that the cycle-to-cycle
variation of the switching period does not degrade audio
reproduction or efficiency. The MAX97002’s spreadspectrum modulator randomly varies the switching
frequency by Q20kHz around the center frequency
(250kHz). Above 10MHz, the wideband spectrum looks
like noise for EMI purposes (see Figure 4).
40
AMPLITUDE (dBµV/m)
30
20
10
0
-10
30
60
80
100
120
140
160
180
200
220
240
260
280
300
850
900
950
1000
FREQUENCY (MHz)
40
30
AMPLITUDE (dBµV/m)
MAX97002
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifiers
20
10
0
-10
300
350
400
450
500
550
600
650
700
FREQUENCY (MHz)
Figure 4. EMI with 15cm of Speaker Cable
20
750
800
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifiers
Figure 5 shows the typical output vs. input curves with
and without the distortion limiter. The dotted line shows
the maximum gain for a given distortion limit without
the distortion limiter. The solid line shows how, with the
distortion limiter enabled, the gain can be increased
without exceeding the set distortion limit. When the
limiter is enabled, selecting a high gain level results in
peak signals being attenuated while low signals are left
unchanged. This increases the perceived loudness without the harshness of a clipped waveform.
MAX97002
Distortion Limiter
The MAX97002 speaker amplifiers integrate a limiter
to provide speaker protection and audio compression.
When enabled, the limiter monitors the audio signal at
the output of the Class D speaker amplifier and decreases the gain if the distortion exceeds the predefined
threshold. The limiter automatically tracks the battery
voltage to reduce the gain as the battery voltage drops.
VOUT
MAXIMUM THD+N
LEVEL
VIN
Figure 5. Limiter Gain Curve
VDD
VDD / 2
Analog Switch
The MAX97002 integrates a DPST analog audio switch
that connects COM1 and COM2 to OUTP and OUTN,
respectively. Unlike discrete solutions, the switch design
reduces coupling of Class D switching noise to the COM_
inputs. This eliminates the need for a costly T-switch.
Drive COM1 and COM2 with a low-impedance source
to minimize noise on the pins. In applications that do not
require the analog switch, leave COM1 and COM2 unconnected. When applying signal on COM1 and COM2, disable the Class D amplifier before closing the switch.
GND
CONVENTIONAL AMPLIFIER BIASING SCHEME
+VDD
SGND
Headphone Amplifier
DirectDrive
Traditional single-supply headphone amplifiers have
outputs biased at a nominal DC voltage (typically half
the supply). Large coupling capacitors are needed to
block this DC bias from the headphone. Without these
capacitors, a significant amount of DC current flows to
the headphone, resulting in unnecessary power dissipation and possible damage to both headphone and
headphone amplifier.
Maxim’s patented DirectDrive® architecture uses a
charge pump to create an internal negative supply
voltage. This allows the headphone outputs of the
MAX97002 to be biased at GND while operating from a
single supply (Figure 6). Without a DC component, there
is no need for the large DC-blocking capacitors. Instead
of two large (220FF, typ) capacitors, the MAX97002
charge pump requires two small ceramic capacitors,
conserving board space, reducing cost, and improving
the frequency response of the headphone amplifier.
-VDD
DirectDrive AMPLIFIER BIASING SCHEME
Figure 6.Traditional Amplifier Output vs. MAX97002
DirectDrive Output
See the Output Power vs. Load Resistance graph in the
Typical Operating Characteristics for details of the possible capacitor sizes. There is a low DC voltage on the
amplifier outputs due to amplifier offset. However, the
offset of the MAX97002 is typically Q0.6mV, which, when
combined with a 32I load, results in less than 50FA of
DC current flow to the headphones.
DirectDrive is a registered trademark of Maxim Integrated
Products, Inc.
21
MAX97002
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifiers
In addition to the cost and size disadvantages of
the DC-blocking capacitors required by conventional
headphone amplifiers, these capacitors limit the amplifier’s low-frequency response and can distort the audio
signal. Previous attempts at eliminating the outputcoupling capacitors involved biasing the headphone
return (sleeve) to the DC-bias voltage of the headphone
amplifiers. This method raises some issues:
U The sleeve is typically grounded to the chassis. Using
the midrail biasing approach, the sleeve must be isolated from system ground, complicating product design.
U During an ESD strike, the amplifier’s ESD structures are
the only path to system ground. Thus, the amplifier must
be able to withstand the full energy from an ESD strike.
U When using the headphone jack as a line out to other
equipment, the bias voltage on the sleeve may conflict
with the ground potential from other equipment, resulting in possible damage to the amplifiers.
Charge Pump
The MAX97002’s dual-mode charge pump generates
both the positive and negative power supply for the
headphone amplifier. To maximize effficiency, both the
charge pump’s switching frequency and output voltage
change based on signal level.
When the input signal level is less than 10% of VDD
the switching frequency is reduced to a low rate. This
minimizes switching losses in the charge pump. When
the input signal exceeds 10% of VDD, the switching frequency increases to support the load current.
For input signals below 25% of VDD, the charge pump
generates Q(VDD/2) to minimize the voltage drop across
the amplifier’s power stage and thus improves efficiency.
Input signals that exceed 25% of VDD cause the charge
pump to output QVDD. The higher output voltage allows
for full output power from the headphone amplifier.
To prevent audible glitches when transitioning from the
Q(VDD/2) output mode to the QVDD output mode, the
charge pump transitions very quickly. This quick change
draws significant current from VDD for the duration of the
transition. The bypass capacitor on VDD supplies the
required current and prevent droop on VDD.
22
The charge pump’s dynamic switching mode can be
turned off through the I2C interface. The charge pump
can then be forced to output either Q(VDD/2) or QVDD
regardless of input signal level.
Class H Operation
A Class H amplifier uses a Class AB output stage with
power supplies that are modulated by the output signal.
In the case of the MAX97002, two nominal power-supply
differentials of 1.8V (+0.9V to -0.9V) and 3.6V (+1.8V
to -1.8V) are available from the charge pump. Figure 7
shows the operation of the output voltage dependent
power supply.
Low-Power Mode
To minimize power consumption when using the headphone amplifier, enable the low-power mode. In this
mode, the headphone mixers and volume control are
bypassed and shutdown.
I2C Slave Address
The MAX97002 uses a slave address of 0x9A or
1001101R/W. The address is defined as the 7 most significant bits (MSBs) followed by the read/write bit. Set the read/
write bit to 1 to configure the MAX97002 to read mode. Set
the read/write bit to 0 to configure the MAX97002 to write
mode. The address is the first byte of information sent to
the MAX97002 after the START (S) condition.
1.8V
0.9V
HPVDD
32ms
VTH_H
OUTPUT
VOLTAGE
VTH_L
-0.9V
HPVSS
-1.8V
Figure 7. Class H Operation
32ms
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifiers
Write zeros to all unused bits in the register table when
updating the register, unless otherwise noted. Tables
2–7 describe each bit.
Table 1. Register Map
REGISTER
B7
B6
INADIFF
INBDIFF
B5
B4
B3
B2
B1
B0
ADDRESS
DEFAULT
R/W
0x00
0x00
R/W
HPRMIX
0x01
0x00
R/W
SPKMIX
0x02
0x00
R/W
STATUS
Input Gain
Headphone
Mixers
Speaker
Mixer
PGAINA
PGAINB
HPLMIX
0
0
0
Headphone
Left
ZCD
SLEW
HPLM
HPLVOL
0x03
0x00
R/W
Headphone
Right
HPGAIN
0
HPRM
HPRVOL
0x04
0x00
R/W
Speaker
FFM
SPKM
Reserved
0
0
Limiter
0
SPKVOL
0
0x05
0x00
R/W
0
0
0
0
0x06
0x00
R/W
0
0
0
THDT1
0x07
0x00
R/W
SPKEN
0
HPLEN
HPREN
BYPEN
0x08
0x01
R/W
0
0
0
CPSEL
FIXED
0x09
0x00
R/W
0xFF
0x00
R
0
THDCLP
Power
Management
SHDN
Charge Pump
0
LPMODE
0
0
REVISION ID
Rev ID
REV
23
MAX97002
I2C Registers
Nine internal registers program the MAX97002. Table 1
lists all of the registers, their addresses, and power-onreset states. Register 0xFF indicates the device revision.
MAX97002
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifiers
Table 2. Input Register
REGISTER
BIT
7
6
NAME
INADIFF
Input A Differential Mode. Configures the input A channel as either a mono differential
signal (INA = INA2 - INA1) or as a stereo signal (INA1 = left, INA2 = right).
0 = Stereo single-ended
1 = Differential
INBDIFF
Input B Differential Mode. Configures the input B channel as either a mono differential
signal (INB = INB2 - INB1) or as a stereo signal (INB1 = left, INB2 = right).
0 = Stereo single-ended
1 = Differential
Input A Preamp Gain. Set the input gain to maximize output signal level for a given input
signal range to improve the SNR of the system. PGAINA = 111 switches to a trimmed
20kI feedback resistor for external gain setting.
5
4
PGAINA
0x00
3
0
24
VALUE
000
001
010
011
100
101
110
111
LEVEL (dB)
-6
-3
0
3
6
9
18
External
Input B Preamp Gain. Set the input gain to maximize output signal level for a given input
signal range to improve the SNR of the system. PGAINB = 111 switches to a trimmed
20kI feedback resistor for external gain setting.
2
1
DESCRIPTION
PGAINB
VALUE
000
001
010
011
100
101
110
111
LEVEL (dB)
-6
-3
0
3
6
9
18
External
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifiers
Table 3. Mixer Registers
REGISTER
BIT
NAME
DESCRIPTION
Left Headphone Mixer. Selects which of the four inputs is routed to the left headphone
output.
7
6
HPLMIX
5
4
0x01
VALUE
0000
1xxx
x1xx
xx1x
xxx1
INPUT
No input
INA1 (disabled when INADIFF = 1)
INA2 (select when INADIFF = 1)
INB1 (disabled when INBDIFF = 1)
INB2 (select when INBDIFF = 1)
Right Headphone Mixer. Selects which of the four inputs is routed to the right headphone output.
3
0
VALUE
0000
1xxx
x1xx
xx1x
xxx1
3
Speaker Mixer. Selects which of the four inputs is routed to the speaker output.
2
VALUE
0000
1xxx
x1xx
xx1x
xxx1
2
HPRMIX
1
0x02
SPKMIX
1
0
INPUT
No input
INA1 (disabled when INADIFF = 1)
INA2 (select when INADIFF = 1)
INB1 (disabled when INBDIFF = 1)
INB2 (select when INBDIFF = 1)
INPUT
No input
INA1 (disabled when INADIFF = 1)
INA2 (select when INADIFF = 1)
INB1 (disabled when INBDIFF = 1)
INB2 (select when INBDIFF = 1)
25
MAX97002
Mixers
MAX97002
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifiers
Volume Control
Table 4. Volume Control Registers
REGISTER
BIT
NAME
DESCRIPTION
ZCD
Zero-Crossing Detection. Determines whether zero-crossing detection is used on all volume control changes to reduce clicks and pops. Disabling zero-crossing detection allows
volume changes to occur immediately.
0 = Enabled
1 = Disabled
6
SLEW
Volume Slewing. Determines whether volume slewing is used on all volume control changes to reduce clicks and pops. When enabled, volume changes cause the
MAX97002 to ramp through intermediate volume settings whenever a change to the
volume is made. If ZCD = 1, slewing occurs at a rate of 0.2ms per step. If ZCD = 0, slew
time depends on the input signal. Write a 1 to this bit to disable slewing and implement
volume changes immediately. This bit also activates soft-start at power-on and soft-stop
and power-off.
0 = Enabled
1 = Disabled
5
HPLM
Left Headphone Mute
0 = Unmuted
1 = Muted
7
Left Headphone Volume
4
VALUE
0x03
3
2
1
0
26
HPLVOL
LEVEL (dB)
VALUE
LEVEL (dB)
0x00
-64
0x10
-12
0x01
-60dB
0x11
-10
0x02
-56
0x12
-8
0x03
-52
0x13
-6
0x04
-48
0x14
-4
0x05
-44
0x15
-2
0x06
-40
0x16
-1
0x07
-37
0x17
0
0x08
-34
0x18
1
0x09
-31
0x19
2
0x0A
-28
0x1A
3
0x0B
-25
0x1B
4
0x0C
-22
0x1C
4.5
0x0D
-19
0x1D
5
0x0E
-16
0x1E
5.5
0x0F
-14
0x1F
6
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifiers
REGISTER
BIT
NAME
7
HPGAIN
5
HPRM
3
0x04
2
HPRVOL
0
DESCRIPTION
Headphone Gain. Controls the headphone amplifier gain.
0 = 0dB
1 = 3dB
Right Headphone Mute
0 = Unmuted
1 = Muted
Right Headphone Volume
4
1
MAX97002
Table 4. Volume Control Registers (continued)
VALUE
LEVEL (dB)
VALUE
LEVEL (dB)
0x00
-64
0x10
-12
0x01
-60dB
0x11
-10
0x02
-56
0x12
-8
0x03
-52
0x13
-6
0x04
-48
0x14
-4
0x05
-44
0x15
-2
0x06
-40
0x16
-1
0x07
-37
0x17
0
0x08
-34
0x18
1
0x09
-31
0x19
2
0x0A
-28
0x1A
3
0x0B
-25
0x1B
4
0x0C
-22
0x1C
4.5
0x0D
-19
0x1D
5
0x0E
-16
0x1E
5.5
0x0F
-14
0x1F
6
27
MAX97002
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifiers
Table 4. Volume Control Registers (continued)
REGISTER
BIT
NAME
7
FFM
6
SPKM
DESCRIPTION
Fixed-Frequency Oscillation. Removes spread spectrum from the Class D oscillator.
0 = Spread-spectrum mode
1 = Fixed-frequency mode
Speaker Mute
0 = Unmuted
1 = Mute
Speaker Volume
5
4
0x05
3
2
1
0
28
SPKVOL
VALUE
LEVEL (dB)
VALUE
LEVEL (dB)
VALUE
LEVEL
(dB)
0x00–0x18
-30
0x26
3
0x34
14.5
0x19
-26
0x27
4
0x35
15
0x1A
-22
0x28
5
0x36
15.5
0x1B
-18
0x29
6
0x37
16
0x1C
-14
0x2A
7
0x38
16.5
0x1D
-12
0x2B
8
0x39
17
0x1E
-10
0x2C
9
0x3A
17.5
0x1F
-8
0x2D
10
0x3B
18
0x20
-6
0x2E
11
0x3C
18.5
0x21
-4
0x2F
12
0x3D
19
0x22
-2
0x30
12.5
0x3E
19.5
0x23
0
0x31
13
0x3F
20
0x24
1
0x32
13.5
0x25
2
0x33
14
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifiers
Table 5. Distortion Limiter Register
REGISTER
BIT
NAME
DESCRIPTION
Distortion Limit
7
6
VALUE
THD LIMIT (%)
0000
Disabled
0001–1001
P4
1010
P5
1011
P6
THDCLP
0x07
5
4
0
THDT1
1100
P8
1101
P 11
1110
P 12
1111
P 15
0000
Disabled
Distortion Release Time Constant
0 = 1.4s
1 = 2.8s
Power Management
Table 6. Power Management Register
REGISTER
BIT
7
NAME
SHDN
DESCRIPTION
Software Shutdown
0 = Device disabled
1 = Device enabled
Low-Power Headphone Mode. Enables low-power headphone mode. When activated this
mode directly connects the selected channel to the headphone amplifiers, bypassing the
mixers and the volume control. Additionally, low-power mode disables the speaker path.
6
LPMODE
5
0x08
VALUE
LIMIT
00
Disabled
01
INA (SE) Connected to the headphone output
10
INB (SE) Connected to the headphone output
11
INA (Diff) to HPL and INB (Diff) to HPR
4
SPKEN
Speaker Amplifier Enable
0 = Disabled
1 = Enabled
2
HPLEN
Left Headphone Amplifier Enable
0 = Disabled
1 = Enabled
1
HPREN
Right Headphone Amplifier Enable
0 = Disabled
1 = Enabled
0
BYPEN
Analog Switch
0 = Open
1 = Closed
29
MAX97002
Distortion Limiter
MAX97002
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifiers
Charge-Pump Control
Table 7. Charge-Pump Control Register
REGISTER
BIT
1
NAME
DESCRIPTION
CPSEL
Charge-Pump Output Select. Works with the FIXED to set Q1.8V or Q0.9V outputs on
HPVDD and HPVSS. Ignored when FIXED = 0.
0 = Q1.8V on HPVDD/HPVSS
1 = Q0.9V on HPVDD/HPVSS
FIXED
Class H Mode. When enabled, this bit forces the charge pump to generate static power
rails for HPVDD and HPVSS, instead of dynamically adjusting them based on output signal level.
0 = Class H mode
1 = Fixed-supply mode
0x09
0
I2C Serial Interface
The MAX97002 features an I2C/SMBusK-compatible,
2-wire serial interface consisting of a serial-data line
(SDA) and a serial-clock line (SCL). SDA and SCL facilitate communication between the MAX97002 and the
master at clock rates up to 400kHz. Figure 1 shows the
2-wire interface timing diagram. The master generates
SCL and initiates data transfer on the bus. The master
device writes data to the MAX97002 by transmitting the
proper slave address followed by the register address
and then the data word. Each transmit sequence is
framed by a START (S) or REPEATED START (Sr) condition and a STOP (P) condition. Each word transmitted
to the MAX97002 is 8 bits long and is followed by an
acknowledge clock pulse. A master reading data from
the MAX97002 transmits the proper slave address followed by a series of nine SCL pulses. The MAX97002
transmits data on SDA in sync with the master-generated
SCL pulses. The master acknowledges receipt of each
byte of data. Each read sequence is framed by a START
or REPEATED START condition, a not acknowledge,
and a STOP condition. SDA operates as both an input
and an open-drain output. A pullup resistor, typically
greater than 500I, is required on SDA. SCL operates
only as an input. A pullup resistor, typically greater than
500I, is required on SCL if there are multiple masters on
the bus, or if the single master has an open-drain SCL
output. Series resistors in line with SDA and SCL are
optional. Series resistors protect the digital inputs of the
MAX97002 from high voltage spikes on the bus lines and
minimize crosstalk and undershoot of the bus signals.
SMBus is a trademark of Intel Corp.
30
Bit Transfer
One data bit is transferred during each SCL cycle. The data
on SDA must remain stable during the high period of the
SCL pulse. Changes in SDA while SCL is high are control
signals (see the START and STOP Conditions section).
START and STOP Conditions
SDA and SCL idle high when the bus is not in use. A
master initiates communication by issuing a START condition. A START condition is a high-to-low transition on
SDA with SCL high. A STOP condition is a low-to-high
transition on SDA while SCL is high (Figure 8). A START
condition from the master signals the beginning of a
transmission to the MAX97002. The master terminates
transmission, and frees the bus, by issuing a STOP condition. The bus remains active if a REPEATED START
condition is generated instead of a STOP condition.
S
Sr
P
SCL
SDA
Figure 8. START, STOP, and REPEATED START Conditions
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifiers
Slave Address
The slave address is defined as the seven most significant bits (MSBs) followed by the read/write bit. For
the MAX97002 the 7 MSBs are 1001101. Setting the
read/write bit to 1 (slave address = 0x9B) configures the
MAX97002 for read mode. Setting the read/write bit to 0
(slave address = 0x9A) configures the MAX97002 for write
mode. The address is the first byte of information sent to
the MAX97002 after the START condition.
Acknowledge
The acknowledge bit (ACK) is a clocked 9th bit that
the MAX97002 uses to handshake receipt each byte
of data when in write mode (Figure 9). The MAX97002
pulls down SDA during the entire master-generated 9th
clock pulse if the previous byte is successfully received.
Monitoring ACK allows for detection of unsuccessful
data transfers. An unsuccessful data transfer occurs
if a receiving device is busy or if a system fault has
occurred. In the event of an unsuccessful data transfer,
the bus master retries communication. The master pulls
down SDA during the 9th clock cycle to acknowledge
receipt of data when the MAX97002 is in read mode. An
acknowledge is sent by the master after each read byte
to allow data transfer to continue. A not-acknowledge is
Write Data Format
A write to the MAX97002 includes transmission of a
START condition, the slave address with the R/W bit set
to 0, one byte of data to configure the internal register
address pointer, one or more bytes of data, and a STOP
condition. Figure 10 illustrates the proper frame format
for writing one byte of data to the MAX97002. Figure 11
illustrates the frame format for writing n-bytes of data to
the MAX97002.
The slave address with the R/W bit set to 0 indicates that
the master intends to write data to the MAX97002. The
MAX97002 acknowledges receipt of the address byte
during the master-generated 9th SCL pulse.
The second byte transmitted from the master configures
the MAX97002’s internal register address pointer. The
pointer tells the MAX97002 where to write the next byte
of data. An acknowledge pulse is sent by the MAX97002
upon receipt of the address pointer data.
The third byte sent to the MAX97002 contains the
data that is written to the chosen register. An acknowledge pulse from the MAX97002 signals receipt of the
data byte. The address pointer autoincrements to the
next register address after each received data byte.
This autoincrement feature allows a master to write to
sequential registers within one continuous frame. The
master signals the end of transmission by issuing a
STOP condition. Register addresses greater than 0x09
are reserved. Do not write to these addresses.
CLOCK PULSE FOR
ACKNOWLEDGMENT
START
CONDITION
SCL
sent when the master reads the final byte of data from
the MAX97002, followed by a STOP condition.
1
28
9
NOT ACKNOWLEDGE
SDA
ACKNOWLEDGE
Figure 9. Acknowledge
31
MAX97002
Early STOP Conditions
The MAX97002 recognizes a STOP (P) condition at any
point during data transmission except if the STOP condition occurs in the same high pulse as a START (S) condition. For proper operation, do not send a STOP condition
during the same SCL high pulse as the START condition.
MAX97002
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifiers
ACKNOWLEDGE FROM MAX97002
B7
ACKNOWLEDGE FROM MAX97002
SLAVE ADDRESS
S
0
B6
B5
B4
B3
B2
B1
B0
ACKNOWLEDGE FROM MAX97002
A
REGISTER ADDRESS
A
A
DATA BYTE
R/W
P
1 BYTE
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
Figure 10. Writing One Byte of Data to the MAX97002
ACKNOWLEDGE FROM MAX97002
ACKNOWLEDGE FROM MAX97002
ACKNOWLEDGE FROM MAX97002
S
SLAVE ADDRESS
0
A
REGISTER ADDRESS
B7 B6 B5 B4 B3 B2 B1 B0
B7 B6 B5 B4 B3 B2 B1 B0
ACKNOWLEDGE FROM MAX97002
A
R/W
DATA BYTE 1
A
1 BYTE
DATA BYTE n
A
P
1 BYTE
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
Figure 11. Writing n-Bytes of Data to the MAX97002
Read Data Format
Send the slave address with the R/W bit set to 1 to initiate
a read operation. The MAX97002 acknowledges receipt
of its slave address by pulling SDA low during the 9th
SCL clock pulse. A START (S) command followed by
a read command resets the address pointer to register
0x00.
The first byte transmitted from the MAX97002 is the contents of register 0x00. Transmitted data is valid on the
rising edge of SCL. The address pointer autoincrements
after each read data byte. This autoincrement feature
allows all registers to be read sequentially within one
continuous frame. A STOP condition can be issued after
any number of read data bytes. If a STOP (P) condition is
issued followed by another read operation, the first data
byte to be read is from register 0x00.
32
The address pointer can be preset to a specific register
before a read command is issued. The master presets
the address pointer by first sending the MAX97002’s
slave address with the R/W bit set to 0 followed by the
register address. A REPEATED START (Sr) condition is
then sent followed by the slave address with the R/W bit
set to 1. The MAX97002 then transmits the contents of
the specified register. The address pointer autoincrements after transmitting the first byte.
The master acknowledges receipt of each read byte
during the acknowledge clock pulse. The master must
acknowledge all correctly received bytes except the last
byte. The final byte must be followed by a not acknowledge from the master and then a STOP condition. Figure
12 illustrates the frame format for reading one byte from
the MAX97002. Figure 13 illustrates the frame format for
reading multiple bytes from the MAX97002.
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifiers
ACKNOWLEDGE FROM MAX97002
SLAVE ADDRESS
REGISTER ADDRESS
0
R/W
NOT ACKNOWLEDGE FROM MASTER
ACKNOWLEDGE FROM MAX97002
A
Sr
SLAVE ADDRESS
REPEATED START
MAX97002
S
ACKNOWLEDGE FROM MAX97002
1
R/W
A
DATA BYTE
A
P
1 BYTE
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
Figure 12. Reading One Byte of Data from the MAX97002
ACKNOWLEDGE FROM MAX97002
S
SLAVE ADDRESS
0
R/W
ACKNOWLEDGE FROM MAX97002
REGISTER ADDRESS
ACKNOWLEDGE FROM MAX97002
A
Sr
REPEATED START
SLAVE ADDRESS
1
DATA BYTE
A
R/W
A
P
1 BYTE
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
Figure 13. Reading n-Bytes of Data from the MAX97002
Applications Information
Filterless Class D Operation
Traditional Class D amplifiers require an output filter to
recover the audio signal from the amplifier’s output. The
filters add cost, increase the solution size of the amplifier,
and can decrease efficiency and THD+N performance.
The traditional PWM scheme uses large differential output swings (2 x VDD(P-P)) and causes large ripple currents. Any parasitic resistance in the filter components
results in a loss of power, lowering the efficiency.
The MAX97002 does not require an output filter. The
device relies on the inherent inductance of the speaker
coil and the natural filtering of both the speaker and
the human ear to recover the audio component of the
square-wave output. Eliminating the output filter results
in a smaller, less costly, more efficient solution.
Because the frequency of the MAX97002 output is well
beyond the bandwidth of most speakers, voice coil
movement due to the square-wave frequency is very
small. Although this movement is small, a speaker not
designed to handle the additional power can be damaged. For optimum results, use a speaker with a series
inductance > 10FH. Typical 8I speakers exhibit series
inductances in the 20FH to 100FH range.
RF Susceptibility
GSM radios transmit using time-division multiple access
(TDMA) with 217Hz intervals. The result is an RF signal
with strong amplitude modulation at 217Hz and its harmonics that are easily demodulated by audio amplifiers.
The MAX97002 is designed specifically to reject RF
signals; however, PCB layout has a large impact on the
susceptibility of the end product.
In RF applications, improvements to both layout and
component selection decreases the MAX97002’s susceptibility to RF noise and prevent RF signals from being
demodulated into audible noise. Trace lengths should
be kept below 1/4 of the wavelength of the RF frequency
of interest. Minimizing the trace lengths prevents them
from functioning as antennas and coupling RF signals
into the MAX97002. The wavelength (l) in meters is
given by:
l = c/f
where c = 3 x
interest.
108
m/s, and f = the RF frequency of
Route the audio signals on the middle layers of the PCB
to allow the ground planes above and below to shield
them from RF interference. Ideally, the top and bottom
layers of the PCB should primarily be ground planes to
create effective shielding.
33
MAX97002
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifiers
Additional RF immunity can also be obtained from relying on the self-resonant frequency of capacitors as it
exhibits the frequency response similar to a notch filter.
Depending on the manufacturer, 10pF to 20pF capacitors
typically exhibit self resonance at RF frequencies. These
capacitors when placed at the input pins can effectively
shunt the RF noise at the inputs of the MAX97002. For
these capacitors to be effective, they must have a lowimpedance, low-inductance path to the ground plane.
Do not use microvias to connect to the ground plane as
these vias do not conduct well at RF frequencies.
Component Selection
Optional Ferrite Bead Filter
Additional EMI suppression can be achieved using a
filter constructed from a ferrite bead and a capacitor to
ground (Figure 14). Use a ferrite bead with low DC resistance, high-frequency (> 600MHz) impedance between
100I and 600I, and rated for at least 1A. The capacitor
value varies based on the ferrite bead chosen and the
actual speaker lead length. Select a capacitor less than
1nF based on EMI performance.
Input Capacitor
An input capacitor, CIN, in conjunction with the input
impedance of the MAX97002 line inputs forms a highpass filter that removes the DC bias from an incoming
analog signal. The AC-coupling capacitor allows the
amplifier to automatically bias the signal to an optimum
DC level. Assuming zero-source impedance, the -3dB
point of the highpass filter is given by:
f−3dB =
1
2πRINCIN
Choose CIN such that f-3dB is well below the lowest frequency of interest. For best audio quality, use capacitors
whose dielectrics have low-voltage coefficients, such as
tantalum or aluminum electrolytic. Capacitors with highvoltage coefficients, such as ceramics, may result in
increased distortion at low frequencies.
Charge-Pump Capacitor Selection
Use capacitors with an ESR less than 100mI for optimum
performance. Low-ESR ceramic capacitors minimize the
output resistance of the charge pump. Most surfacemount ceramic capacitors satisfy the ESR requirement.
For best performance over the extended temperature
range, select capacitors with an X7R dielectric.
34
OUT+
MAX97002
OUT-
Figure 14. Optional Class D Ferrite Bead Filter
Charge-Pump Flying Capacitor
The value of the flying capacitor (connected between
C1N and C1P) affects the output resistance of the
charge pump. A value that is too small degrades the
device’s ability to provide sufficient current drive, which
leads to a loss of output voltage. Increasing the value
of the flying capacitor reduces the charge-pump output
resistance to an extent. Above 1FF, the on-resistance
of the internal switches and the ESR of external chargepump capacitors dominate.
Charge-Pump Holding Capacitor
The holding capacitor (bypassing HPVDD and HPVSS)
value and ESR directly affect the ripple on the supply.
Increasing the capacitor’s value reduces output ripple.
Likewise, decreasing the ESR reduces both ripple and
output resistance. Lower capacitance values can be
used in systems with low maximum output power levels.
See the Output Power vs. Load Resistance graph in the
Typical Operating Characteristics for more information
Supply Bypassing, Layout, and Grounding
Proper layout and grounding are essential for optimum performance. Use a large continuous ground
plane on a dedicated layer of the PCB to minimize
loop areas. Connect GND directly to the ground plane
using the shortest trace length possible. Proper grounding improves audio performance, minimizes crosstalk
between channels, and prevents any digital noise from
coupling into the analog audio signals.
Place the capacitor between C1P and C1N as close
to the MAX97002 as possible to minimize trace length
from C1P to C1N. Inductance and resistance added
between C1P and C1N reduce the output power of the
headphone amplifier. Bypass HPVDD and HPVSS with
capacitors located close to the pins with a short trace
length to GND. Close decoupling of HPVDD and HPVSS
minimizes supply ripple and maximizes output power
from the headphone amplifier.
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifiers
An evaluation kit (EV kit) is available to provide an
example layout for the MAX97002. The EV kit allows
quick setup of the MAX97002 and includes easy-to-use
software, allowing all internal registers to be controlled.
WLP Applications Information
For the latest application details on WLP construction,
dimensions, tape carrier information, PCB techniques,
bump-pad layout, and the recommended reflow temperature profile, as well as the latest information on reliability
testing results, refer to the Application Note 1891: WaferLevel Packaging (WLP) and Its Applications on Maxim’s
website at www.maxim-ic.com/ucsp. See Figure 15 for
the recommended PCB footprint for the MAX97002.
MAX97002
Bypass PVDD to GND with as little trace length as possible. Connect OUTP and OUTN to the speaker using
the shortest and widest traces possible. Reducing trace
length minimizes radiated EMI. Route OUTP/OUTN as
a differential pair on the PCB to minimize the loop area,
thereby reducing the inductance of the circuit. If filter
components are used on the speaker outputs, be sure
to locate them as close as possible to the MAX97002
to ensure maximum effectiveness. Minimize the trace
length from any ground tied passive components to
GND to further minimize radiated EMI.
0.25mm
0.22mm
Figure 15. Recommended PCB Footprint
35
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the
package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
20 WLP
W202A2+2
21-0059
20L WLP.EPS
MAX97002
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifiers
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.
36
© 2010
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.