TPS53315 www.ti.com SLUSAE6 – DECEMBER 2010 12-A Step-Down Regulator with Integrated Switcher Check for Samples: TPS53315 FEATURES APPLICATIONS • • • • • • • • 1 EN 31 30 29 28 27 26 25 24 23 22 21 LL LL LL LL PGOOD 32 LL VREG The TPS53315 is available in a 5 mm × 7 mm 40-pin, QFN package and is specified from –40°C to 85°C. LL • • • The conversion input voltage ranges from 3 V to 15 V, the supply voltage range is from 4.5 V to 25 V, and the output voltage range is from 0.6 V to 5.5 V. LL • This device features single-rail input support, one 19-mΩ and one 7-mΩ integrated MOSFET, accurate 1%, 0.6 V Reference, and integrated boost switch. A sample of competitive features include: greater than 96% maximum efficiency, 3 V to 15 V wide input voltage range, very low external component count, D-CAP™ mode control for super fast transient, selectable auto-skip and PWM operation, internal soft-start control, adjustable frequency, and no need for compensation. LL • • • TPS53315 is a D-CAP™ mode, 12-A synchronous switcher with integrated MOSFETs. It is designed for ease of use, low external component count, and small package power systems. N/C • • DESCRIPTION VBST • • Server and Desktop Computers Notebook Computers Telecommunication Equipments N/C • • Conversion Input Voltage Range: 3 V to 15 V VDD Input Voltage Range: 4.5 V to 25 V Output Voltage Range: 0.6 V to 5.5 V 5-V LDO Output Integrated Power MOSFETs with 12-A Continuous Output Current <10-mA Shut Down Current Auto-Skip Eco-mode™ for Light-Load Efficiency D-CAP™ Mode with Fast Transient Response Selectable Switching Frequency from 250 kHz to 1 MHz with an External Resistor Built-in 1%, 0.6-V Reference 0.7-ms, 1.4-ms, 2.8-ms and 5.6-ms Selectable Internal Voltage Servo Soft-Start Pre-Charged Start-up Capability Integrated Boost Switch Adjustable Overcurrent Limit Via External Resistor Overvoltage/Undervoltage, UVLO and Over-Temperature Protection Support All Ceramic Output Capacitors Open Drain Power Good Indication 40-pin QFN Package with PowerPAD™ PGOOD 2 VOUT LL 20 33 N/C 34 N/C LL 19 35 TRIP LL 18 36 EN 37 VFB LL 17 TPS53315 39 MODE VIN 14 40 VDD PGND VREG GND2 PGND PGND PGND PGND PGND PGND VIN 13 VIN VIN RF GND1 38 LL 16 VIN 15 1 2 3 4 5 6 7 8 9 10 11 12 VDD 4.5 V to 25 V VIN 3 V to 15 V UDG-10199 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Eco-mode, D-CAP, PowerPAD are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010, Texas Instruments Incorporated TPS53315 SLUSAE6 – DECEMBER 2010 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) TA PACKAGE –40°C to 85°C Plastic QFN (RGF) (1) ORDERING NUMBER PINS TRANSPORT MEDIA MINIMUM QUANTITY TPS53315RGFR 40 Tape and reel 3000 TPS53315RGFT 40 Mini reel 250 ECO PLAN Green (RoHS and no Pb/Br) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) VALUE Input voltage range VIN (main supply) –0.3 to 17 VDD –0.3 to 28 VBST –0.3 to 24 VBST(with respect to LL) –0.3 to 7 EN, TRIP, VFB, RF, MODE –0.3 to 7 LL Output voltage range DC V –1 to 23 Pulse < 20 ns, E = 5 mJ –7 PGOOD, VREG –0.3 to 7 PGND Source/Sink Current UNIT V –0.3 to 0.3 VBST 50 mA Operating free-air temperature, TA –40 to 85 °C Storage temperature range, Tstg –55 to 150 °C Junction temperature range, TJ –40 to 150 °C 300 °C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. THERMAL INFORMATION THERMAL METRIC (1) TPS53315 RGF(40 PINS) qJA Junction-to-ambient thermal resistance 35.8 qJCtop Junction-to-case (top) thermal resistance 23.8 qJB Junction-to-board thermal resistance 10.1 yJT Junction-to-top characterization parameter 0.4 yJB Junction-to-board characterization parameter 10.0 qJCbot Junction-to-case (bottom) thermal resistance 2.8 (1) 2 UNITS °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS53315 TPS53315 www.ti.com SLUSAE6 – DECEMBER 2010 RECOMMENDED OPERATING CONDITIONS VALUE VIN (main supply) Input voltage range Output voltage range Source/Sink Current UNIT 3 to 15 VDD 4.5 to 25 VBST 4.5 to 21 VBST(with respect to LL) 4.5 to 6.5 EN, TRIP, VFB, RF, MODE –0.1 to 6.5 LL –0.8 to 15 PGOOD, VREG –0.1 to 6.5 VBST Junction temperature range, TJ Product Folder Link(s): TPS53315 V 50 mA –40 to 125 °C Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated V 3 TPS53315 SLUSAE6 – DECEMBER 2010 www.ti.com ELECTRICAL CHARACTERISTICS Over recommended free-air temperature range, VDD = 12 V (Unless otherwise noted) PARAMETER CONDITIONS MIN TYP MAX UNIT SUPPLY VOLTAGE AND SUPPLY CURRENT VVIN VIN pin power conversion input voltage VDD Supply input voltage IVIN(leak) VIN pin leakage current VEN = 0 V IVDD VDD supply current VDD current, TA = 25°C, No Load, VEN = 5 V, VVFB = 0.630 V IVDDSDN VDD shutdown current VDD current, TA = 25°C, No Load, VEN = 0 V 3 15 4.5 25 V 1 µA 590 µA 10 µA 420 V INTERNAL REFERENCE VOLTAGE VFB voltage, CCM condition (1) VVFB VFB regulation voltage IVFB VFB input current 0.6000 TA = 25°C TA = 0°C to 85°C TA = -40°C to 85°C V 0.597 0.600 0.603 0.5952 0.600 0.6048 0.594 0.600 0.606 0.002 0.2 5.0 5.35 VVFB = 0.630 V, TA = 25°C V µA LDO OUTPUT VVREG LDO output voltage 0 mA ≤ IVREG ≤ 30 mA IVREG LDO output current (1) Maximum current allowed from LDO VDO LDO drop out voltage VDD = 4.5 V, IVREG = 30 mA 4.77 V 30 mA 295 mV BOOT STRAP SWITCH VFBST Forward voltage VVREG-VBST, IF = 10 mA, TA = 25°C IVBSTLK VBST leakage current VVBST = 23 V, VLL = 17 V, TA = 25°C 0.1 0.2 V 0.01 1.5 µA 260 400 DUTY AND FREQUENCY CONTROL tOFF(min) tON(min) Minimum off time TA = 25°C Minimum on time VVIN = 17 V, VOUT = 0.6 V, RRF = 0 Ω to VREG, TA = 25°C (1) 150 35 RMODE = 39 kΩ 0.7 RMODE = 100 kΩ 1.4 RMODE = 200 kΩ 2.8 RMODE = 470 kΩ 5.6 ns SOFTSTART Internal SS time from VOUT = 0 to VOUT = 95% tSS ms POWERGOOD VTHPG PG threshold PG in from lower 92.5% PG in from higher 107.5% PG hysteresis 98.5% 110% 112.5% 5% 7.8% RPG PG transistor on-resistance 15 30 55 Ω tPGDEL PG Delay after soft-start 0.8 1 1.2 ms (1) 4 2.5% 96% Ensured by design. Not production tested. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS53315 TPS53315 www.ti.com SLUSAE6 – DECEMBER 2010 ELECTRICAL CHARACTERISTICS Over recommended free-air temperature range, VDD = 12 V (Unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LOGIC THRESHOLD AND SETTING CONDITIONS VEN EN voltage threshold IEN EN input current fSW Switching frequency Enable 1.8 V Disable 0.6 VEN = 5 V 1.0 RRF = 0 Ω to GND, TA = 25°C (1) 200 250 300 RRF = 187 kΩ to GND, TA = 25°C (1) 250 300 350 RRF = 619 kΩ to GND, TA = 25°C (1) 350 400 450 RRF = Open, TA = 25°C (1) 450 500 550 (1) 580 650 720 RRF = 309 kΩ to VREG, TA = 25°C (1) 670 750 820 RRF = 124 kΩ to VREG, TA = 25°C (1) 770 850 930 880 970 1070 10.0 10.6 RRF = 866 kΩ to VREG, TA = 25°C RRF = 0 Ω to VREG, TA = 25°C (1) µA kHz PROTECTION: CURRENT SENSE ITRIP TRIP source current VTRIP = 1 V, TA = 25°C TCITRIP TRIP current temperature coefficent On the basis of 25°C (2) VTRIP Current limit threshold setting range VTRIP-GND voltage 0.2 VTRIP = 1.2 V 140 150 160 19 26 33 VTRIP = 1.2 V –160 –150 –140 VTRIP = 0.2 V –33 –26 –19 3 15 VOCL Current limit threshold VOCLN Negative current limit threshold VAZCADJ Auto zero cross adjustable range VTRIP = 0.2 Positive 9.4 4700 Negative µA ppm/°C 1.2 –15 –3 120% 125% V mV mV PROTECTION: UVP and OVP VOVP OVP trip threshold OVP detect tOVPDEL OVP propagation delay time VFB delay with 50-mV overdrive VUVP Output UVP trip threshold time UVP detect tUVPDEL Output UVP propagation delay time tUVPEN Output UVP enable delay time from EN to UVP workable, RMODE = 39 kΩ 115% 1 µs 65% 70% 75% 0.8 1 1.2 ms 2.0 2.6 3.2 ms 4.00 4.20 4.32 UVLO VUVVREG VREG UVLO threshold Wake up Hysteresis 0.25 Shutdown temperature (2) 145 V THERMAL SHUTDOWN TSDN (1) (2) Thermal shutdown threshold Hysteresis (2) 10 °C Not production tested. Test condition is VIN = 12 V, VOUT= 1.1 V, IOUT= 5 A using application circuit shown in Figure 33. Ensured by design. Not production tested. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS53315 5 TPS53315 SLUSAE6 – DECEMBER 2010 www.ti.com PGOOD N\C VBST N/C LL LL LL LL LL LL LL LL PIN DESCRIPTION 32 31 30 29 28 27 26 25 24 23 22 21 N/C 33 20 LL N/C 34 19 LL TRIP 35 18 LL EN 36 17 LL TPS53315RGF VDD 40 13 VIN 1 2 3 4 5 6 7 8 9 10 11 12 VIN VIN VIN 14 PGND 39 PGND MODE PGND VIN PGND 15 PGND 38 PGND RF GND2 LL VREG 16 PGND 37 GND1 VFB PIN FUNCTIONS PIN NAME NO. I/O/P (1) DESCRIPTION EN 36 I Enable pin. GND1 1 G GND for controller GND2 4 G GND for half-bridge B Output of converted power. Connect this pin to the output Inductor. I Soft-start and skip/CCM selection. Connect a resistor to select soft-start time using Table 1. The soft-start time is detected and stored into internal register during start-up. 16 17 18 19 20 21 LL 22 23 24 25 26 27 28 MODE 39 29 N/C 31 33 No connection 34 (1) 6 I=Input, O=Output, B=Bidirectional, P=Supply, G=Ground Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS53315 TPS53315 www.ti.com SLUSAE6 – DECEMBER 2010 PIN FUNCTIONS (continued) PIN NAME PGOOD NO. 32 I/O/P (1) DESCRIPTION O Open drain power good flag. Provides a 1-ms start up delay after the VFB pin voltage falls within specified limits. When the VFB pin voltage goes outside the specified limits, the PGOOD pin goes low within 10 µs. G Power GND Switching frequency selection. Connect a resistance to GND or VREG to select switching frequency using Table 2. The switching frequency is detected and stored during the startup. 2 5 6 PGND 7 8 9 10 RF 38 I TRIP 35 I OCL detection threshold setting pin. 10 µA at room temperature, 4700 ppm/°C current is sourced and set the OCL trip voltage as follows. space VOCL = VTRIP/8 ( VTRIP ≤1.2 V, VOCL ≤ 150 mV) VBST 30 P Supply input for high-side FET gate driver (boost terminal). Connect capacitor from this pin to LL-node. Internally connected to the VREG pin via bootstrap MOSFET switch. VDD 40 P Controller power supply input. VFB 37 I Output feedback input. Connect this pin to VOUT through a resistor divider. P Conversion power input. P 5-V LDO output. 11 12 VIN 13 14 15 VREG 3 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS53315 7 TPS53315 SLUSAE6 – DECEMBER 2010 www.ti.com FUNCTIONAL BLOCK DIAGRAM 0.6 V +10/15% 0.6 V –30% + UV PGOOD + Delay Delay + 0.6 V –10/15% Ramp Compensation Control Logic + OV +20% + VFB UVP/OVP Logic RF VBST 0.6 V SS 10 mA VREG GND TRIP + + PWM VIN tON OneShot + + OCP LL LL XCON + ZC PGND Control Logic PGND SS FCCM/ Skip Decode MODE EN VOUT On/Off time Minimum On/Off Light load OVP/UVP FCCM/Skip LL Fault Sdn VREG LDO + VDD V5OK + 4.2 V/3.95 V Enable 1.2 V/0.95 V + EN THOK 145°C/135°C TPS53315 UDG-10200 8 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS53315 TPS53315 www.ti.com SLUSAE6 – DECEMBER 2010 6 600 5 500 400 300 200 VEN = 5 V VVDD = 12 V VVFB = 0.63 V No Load 100 0 −40 −25 −10 5 20 35 50 65 Temperature (°C) 80 95 VDD Shutdown Current (µA) VDD Supply Current (µA) TYPICAL CHARACTERISTICS 700 3 2 5 20 35 50 65 Temperature (°C) 80 95 110 125 Figure 2. VDD Shutdown Current vs. Temperature 16 140 15 120 TRIP Pin Current (µA) 14 100 80 60 40 13 12 11 10 9 8 20 0 −40 −25 −10 OVP UVP 5 20 35 50 65 Temperature (°C) 80 95 7 VVDD = 12 V 6 −40 −25 −10 110 125 Figure 3. OVP/UVP Trip Threshold vs. Temperature 5 20 35 50 65 Temperature (°C) 80 110 125 Switching Frequency (kHz) 1000 100 fSET = 300 kHz VIN = 12 V VOUT = 1.1 V 10 100 fSET = 500 kHz VIN = 12 V VOUT = 1.1 V 10 FCCM Skip Mode 1 0.01 95 Figure 4. Trip Pin Current vs. Temperature 1000 Switching Frequency (kHz) VEN = 0 V VVDD = 12 V No Load 1 0 −40 −25 −10 110 125 Figure 1. VDD Supply Current vs. Temperature OVP/UVP Trip Threshold (%) 4 0.1 1 Output Current (µA) 10 100 Figure 5. Frequency vs. Temperature (fSET = 300 kHz) FCCM Skip Mode 1 0.01 0.1 1 Output Current (A) 10 100 Figure 6. Frequency vs. Temperature (fSET = 500 kHz) Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS53315 9 TPS53315 SLUSAE6 – DECEMBER 2010 www.ti.com TYPICAL CHARACTERISTICS Inductor Values IN06155: 1 µH, 2.3 mΩ, HCB1175-501: 0.5 µH, 0.29 mΩ 1000 Switching Frequency (kHz) Switching Frequency (kHz) 1000 100 fSET = 750 kHz VIN = 12 V VOUT = 1.1 V 10 100 fSET = 1 MHz VIN = 12 V VOUT = 1.1 V 10 FCCM Skip Mode 1 0.01 0.1 1 Output Current (A) 10 FCCM Skip Mode 1 0.01 100 1200 1.120 1000 1.115 600 400 200 fSW = 300 kHz fSW = 500 kHz fSW = 750 kHz fSW = 1 MHz 0 0 1 2 1.100 1.095 1.090 IOUT =10 A VIN = 12 V 3 4 Output Voltage (V) 5 1.085 1.080 6 90 1.106 80 1.104 70 Efficiency (%) Output Voltage (V) 100 1.108 1.102 1.100 1.098 1.096 Skip Mode FCCM 0 2 4 6 8 Output Current (A) fSW = 500 kHz VIN = 12 V 1.092 5 6 7 8 9 10 11 Input Voltage (V) 12 13 14 Figure 11. Output Voltage vs. Input Voltage 15 12 60 50 VIN = 12 V VOUT = 1.1 V 40 30 FCCM, No Load Skip Mode, No Load FCCM and Skip Mode, IOUT = 10 A 10 Figure 10. Output Voltage vs. Output Current 1.110 1.094 10 100 1.105 Figure 9. Switching Frequency vs. Output Voltage 1.090 10 1.110 800 −200 1 Output Current (A) Figure 8. Frequency vs. Temperature (fSET = 1 MHz) Output Voltage (V) Switching Frequency (kHz) Figure 7. Frequency vs. Temperature (fSET = 750 kHz) 0.1 Skip Mode, fSW = 500 kHz FCCM, fSW = 500 kHz Skip Mode, fSW = 300 kHz FCCM, fSW = 300 kHz 20 10 0 0.01 0.1 1 Output Current (A) 10 100 Figure 12. Efficiency vs. Output Current, Inductor: IN06155 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS53315 TPS53315 www.ti.com SLUSAE6 – DECEMBER 2010 TYPICAL CHARACTERISTICS 98 98 94 94 90 90 Efficiency (%) Efficiency (%) Inductor Values IN06155: 1 µH, 2.3 mΩ, HCB1175-501: 0.5 µH, 0.29 mΩ 86 82 78 VIN = 12 V FCCM fSW = 300 kHz 74 1.0 1.1 1.2 86 82 78 VOUT (V) 1.5 1.8 3.3 5.0 VIN = 12 V Skip Mode fSW = 300 kHz 74 70 2 4 6 8 Output Current (A) 10 0 12 Figure 13. Efficiency vs Output Current, Inductors: VOUT ≤ 1.8 V: HCB1175-501, VOUT ≥ 3.3 V: IN06155 98 98 94 94 90 90 86 82 78 VIN = 12 V FCCM fSW = 500 kHz 74 1.0 1.1 1.2 2 4 6 8 Output Current (A) 10 12 Figure 14. Efficiency vs Output Current, Inductors: VOUT ≤ 1.8 V: HCB1175-501, VOUT ≥ 3.3 V: IN06155 Efficiency (%) Efficiency (%) VOUT (V) 1.5 1.8 3.3 5.0 70 0 86 82 78 VOUT (V) 1.5 1.8 3.3 5.0 VIN = 12 V Skip Mode fSW = 500 kHz 74 70 1.0 1.1 1.2 VOUT (V) 1.5 1.8 3.3 5.0 70 0 2 4 6 8 Output Current (A) 10 0 12 Figure 15. Efficiency vs Output Current, Inductors: VOUT ≤ 1.8 V: HCB1175-501, VOUT ≥ 3.3 V: IN06155 98 98 94 94 90 90 86 82 78 74 1.0 1.1 1.2 VOUT (V) 1.5 1.8 3.3 6 8 Output Current (A) 10 12 82 VIN = 5 V Skip Mode fSW = 500 kHz 74 70 4 86 78 VIN = 5 V FCCM fSW = 500 kHz 2 Figure 16. Efficiency vs Output Current, Inductors: VOUT ≤ 1.8 V: HCB1175-501, VOUT ≥ 3.3 V: IN06155 Efficiency (%) Efficiency (%) 1.0 1.1 1.2 1.0 1.1 1.2 VOUT (V) 1.5 1.8 3.3 70 0 2 4 6 8 Output Current (A) 10 12 0 Figure 17. Efficiency vs Output Current, Inductor: HCB1175-501 2 4 6 8 Output Current (A) 10 Figure 18. Efficiency vs Output Current, Inductor: HCB1175-501 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS53315 12 11 TPS53315 SLUSAE6 – DECEMBER 2010 www.ti.com TYPICAL CHARACTERISTICS FCCM VIN = 12 V IOUT= 10 A EN (5 V/div) FCCM VIN = 12 V IOUT= 0 A EN (5 V/div) VOUT (0.5 V/div) VOUT (0.5 V/div) 0.5 V pre-biased VREG (5 V/div) VREG (5 V/div) PGOOD (5 V/div) PGOOD (5 V/div) Time (1 ms/div) Time (1 ms/div) Figure 19. Start-Up Figure 20. Pre-Bias Start-Up EN (5 V/div) FCCM VIN = 12 V IOUT= 10 A FCCM VEN = 5 V IOUT= 10 A VDD = VIN VIN (5 V/div) VOUT (0.5 V/div) VOUT (0.5 V/div) VREG (5 V/div) VREG (5 V/div) PGOOD (5 V/div) PGOOD (5 V/div) Time (4 ms/div) Time (2 ms/div) Figure 21. Turn-Off 12 Figure 22. UVLO Start-Up Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS53315 TPS53315 www.ti.com SLUSAE6 – DECEMBER 2010 TYPICAL CHARACTERISTICS Skip Mode VIN = 12 V IOUT= 0 A FCCM VIN = 12 V IOUT = 0 A VOUT (20 mV/div) VOUT (20 mV/div) LL (5 V/div) LL (5 V/div) IL (2 A/div) IL (2 A/div) Time (2 µs/div) Time (1 µs/div) Figure 23. 1.1-V Output FCCM Steady-State Operation Skip Mode VIN = 12 V Figure 24. 1.1-V Output Skip Mode Steady-State Operation VOUT (20 mV/div) VOUT (20 mV/div) VOUT = 1.1 V Skip Mode VIN = 12 V LL (5 V/div) LL (5 V/div) VOUT = 1.1 V IL (2 A/div) Time (100 µs/div) IL (2 A/div) Time (100 µs/div) Figure 25. CCM to DCM Transition Figure 26. DCM to CCM Transition Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS53315 13 TPS53315 SLUSAE6 – DECEMBER 2010 www.ti.com TYPICAL CHARACTERISTICS Skip Mode VIN = 12 V FCCM VIN = 12 V VOUT = 1.1 V VOUT (20 mV/div) IOUT from 0 A to 5 A, 2.5A/µs VOUT = 1.1 V VOUT (20 mV/div) IOUT from 0 A to 5 A, 2.5A/µs IOUT (5 A/div) IOUT (5 A/div) Time (2 µs/div) Time (100 µs/div) Figure 27. FCCM Load Transient Figure 28. Skip Mode Load Transient VIN = 12 V VOUT (1 V/div) IOUT from 10 A to 15 A EN (5 V/div) LL (10 V/div) VOUT (1 V/div) IL (10 A/div) PGOOD (5 V/div) PGOOD (5 V/div) VIN = 12 V IOUT = 10 A Time (1 s/div) Time (10 ms/div) Figure 29. Overcurrent Protection 14 Submit Documentation Feedback Figure 30. Over-temperature Protection Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS53315 TPS53315 www.ti.com SLUSAE6 – DECEMBER 2010 TYPICAL CHARACTERISTICS Figure 31, shows the thermal signature of the TPS53315 EVM, VIN = 12 V, VOUT = 1.1 V, IOUT= 12 A, fSW = 500 kHz at room temperature with no airflow. Figure 32 shows the thermal signature of the TPS53315 EVM, VIN = 12 V, VOUT = 3.3 V, IOUT= 12 A, fSW = 650 kHz at room temperature with no airflow. Figure 31. Thermal Signature of TPS53315 EVM, fSW = 500 kHz Figure 32. Thermal Signature of TPS53315 EVM, fSW = 650 kHz Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS53315 15 TPS53315 SLUSAE6 – DECEMBER 2010 www.ti.com APPLICATION INFORMATION APPLICATION CIRCUIT DIAGRAM R9 0 W R10 100 kW VREG C5 0.1 mF 27 26 25 24 23 22 21 N/C VBST N/C LL LL LL LL LL LL LL LL L1 1 mH IN06155 N/C 34 N/C LL 19 35 TRIP LL 18 36 EN LL 17 37 VFB 38 RF VIN 15 39 MODE VIN 14 40 VDD VIN 13 TPS53315 PGND PGND PGND PGND VIN VIN 1 2 3 4 5 6 7 8 9 10 11 12 C3 1 mF C4 1 mF COUT 330 mF LL 16 PGND R4 187 kW VOUT LL 20 33 PGND R8 80.6 kW 28 GND2 R2 10 kW 29 VREG R5 PGOOD 100 kW 30 PGND EN 31 GND1 R1 8.06 kW 32 PGOOD PGOOD VIN 3 V to 15 V CIN 22 mF x 4 VDD 4.5 V to 25 V UDG-10201 Figure 33. Typical Application Circuit Diagram C2 1 nF R9 0 W R10 100 kW R7 1.5 kW VREG C5 0.1 mF 32 31 30 29 28 27 26 25 24 23 22 21 PGOOD N/C VBST N/C LL LL LL LL LL LL LL LL PGOOD R1 8.06 kW LL 19 35 TRIP LL 18 36 EN VFB 38 RF VIN 15 C4 1 mF C3 1 mF PGND PGND PGND VIN VIN 2 PGND VIN 13 PGND VIN 14 VDD PGND MODE 40 1 COUT 100 mF Ceramic LL 16 39 R4 187 kW COUT 100 mF Ceramic LL 17 TPS53315 GND2 R8 80.6 kW N/C VREG R2 10 kW 34 37 VOUT LL 20 N/C PGND R5 PGOOD 100 kW L1 1 mH IN06155 33 GND1 EN C1 0.1 mF 3 4 5 6 7 8 9 10 11 12 VIN 3 V to 15 V R12 0W CIN 22 mF x 4 VDD 4.5 V to 25 V UDG-10202 Figure 34. Typical Application Circuit Diagram with Ceramic Output Capacitors 16 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS53315 TPS53315 www.ti.com SLUSAE6 – DECEMBER 2010 General Description The TPS53315 is a high-efficiency, single channel, synchronous buck converter suitable for low output voltage point-of-load applications in computing and similar digital consumer applications. The device features proprietary D-CAP™ mode control combined with an adaptive on-time architecture. This combination is ideal for building modern low duty ratio, ultra-fast load step response DC-DC converters. The output voltage ranges from 0.6 V to 5.5 V. The conversion input voltage range is from 3 V up to 15 V. The D-CAP™ mode uses the ESR of the output capacitor(s) to sense the device current. One advantage of this control scheme is that it does not require an external phase compensation network. This allows a simple design with a low external component count. Eight preset switching frequency values can be chosen using a resistor connected from the RF pin to ground or the VREG pin. Adaptive on-time control tracks the preset switching frequency over a wide input and output voltage range while allowing the switching frequency to increase at the step-up of the load. The TPS53315 has a MODE pin to select between auto-skip mode and forced continuous conduction mode (FCCM) for light load conditions. The MODE pin also sets the selectable soft-start time ranging from 0.7 ms to 5.6 ms. Enable and Soft Start When the EN pin voltage rises above the enable threshold voltage (typically 1.2 V), the controller enters its start-up sequence. The internal LDO regulator starts immediately and regulates to 5 V at the VREG pin. The controller then uses the first 250 ms to calibrate the switching frequency setting resistance attached to the RF pin and stores the switching frequency code in internal registers. However, switching is inhibited during this phase. In the second phase, an internal DAC starts ramping up the reference voltage from 0 V to 0.6 V. Depending on the MODE pin setting, the ramping up time varies from 0.7 ms to 5.6 ms. Smooth and constant ramp-up of the output voltage is maintained during start-up regardless of load current. Table 1. Soft-Start and MODE MODE SELECTION Auto Skip Forced CCM (1) (1) ACTION Pull down to GND Connect to PGOOD SOFT-START TIME (ms) RMODE (kΩ) 0.7 39 1.4 100 2.8 200 5.6 475 0.7 39 1.4 100 2.8 200 5.6 475 The device transitions into FCCM after the PGOOD pin goes high. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS53315 17 TPS53315 SLUSAE6 – DECEMBER 2010 www.ti.com Adaptive On-Time D-CAP™ Control The TPS53315 does not have a dedicated oscillator to determine switching frequency. However, the device operates with pseudo-constant frequency by feed-forwarding the input and output voltages into the on-time one-shot timer. The adaptive on-time control adjusts the on-time to be inversely proportional to the input voltage æ VIN ö ç tON µ ÷ VOUT ø . and proportional to the output voltage è This makes the switching frequency fairly constant in steady state conditions over a wide input voltage range. The switching frequency is selectable from eight preset values by a resistor connected between the RF pin and GND or between the RF pin and the VREG pin as shown in Table 2. (Leaving the resistance open sets the switching frequency to 500 kHz.) Table 2. Resistor and Switching Frequency RESISTOR (RRF) CONNECTIONS SWITCHING FREQUENCY (kHz) 0 Ω to GND 250 187 kΩ to GND 300 619 kΩ to GND 400 Open 500 866 kΩ to VREG 600 309 kΩ to VREG 750 124 kΩ to VREG 850 0 Ω to VREG 970 The off-time is modulated by a PWM comparator. The VFB node voltage (the mid-point of resistor divider) is compared to the internal 0.6-V reference voltage added with a ramp signal. When the signal values match, the PWM comparator asserts a set signal to terminate the off-time (turn off the low-side MOSFET and turn on high-side MOSFET). The set signal is valid if the inductor current level is below the OCP threshold, otherwise the off-time is extended until the current level falls below the threshold. Figure 35 and Figure 36 show two on-time control schemes. VFB VFB VREF VREF tON tON tOFF UDG-10208 Figure 35. On-Time Control Without Ramp Compensation 18 Compensation Ramp PWM PWM tOFF UDG-10209 Figure 36. On-Time Control With Ramp Compensation Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS53315 TPS53315 www.ti.com SLUSAE6 – DECEMBER 2010 Small Signal Model From small-signal loop analysis, a buck converter using D-CAP™ mode can be simplified as shown in Figure 37. TPS53315 VIN Switching Modulator VIN R1 LL VFB PWM 37 + R2 + Control Logic and Divider L VOUT IIND IOUT IC 0.6 V ESR RLOAD Voltage Divider VC COUT Output Capacitor UDG-10203 Figure 37. Simplified Modulator Model The output voltage is compared with the internal reference voltage (ramp signal is ignored here for simplicity). The PWM comparator determines the timing to turn on the high-side MOSFET. The gain and speed of the comparator can be assumed high enough to keep the voltage at the beginning of each on-cycle substantially constant. 1 H (s ) = s ´ ESR ´ COUT (1) For the loop stability, the 0 dB frequency, ƒ0, defined in Equation 2 must be lower than ¼ of the switching frequency. f 1 £ SW f0 = 2p ´ ESR ´ COUT 4 (2) According to Equation 2, the loop stability of D-CAP™ mode modulator is mainly determined by the capacitor chemistry. For example, specialty polymer capacitors (SP-CAP) have COUT on the order of several 100 µF and ESR in range of 10 mΩ. These makes ƒ0 on the order of 100 kHz or less and the loop is stable. However, ceramic capacitors have an ƒ0 at more than 700 kHz, and need special care when used with this modulator. An application circuit using ceramic capacitors is described in External Parts Selection section under All Ceramic Output Capacitors. Ramp Signal The TPS53315 adds a ramp signal to the 0.6-V reference in order to improve jitter performance. The feedback voltage is compared with the reference information to keep the output voltage in regulation. By adding a small ramp signal to the reference, the signal-to-noise ratio at the onset of a new switching cycle is improved. Therefore the operation becomes less jittery and more stable. The ramp signal is controlled to start with –7 mV at the beginning of an on-cycle and becomes 0 mV at the end of an off-cycle in steady state. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS53315 19 TPS53315 SLUSAE6 – DECEMBER 2010 www.ti.com Auto-Skip Eco-mode™ Light Load Operation While the MODE pin is pulled low via RMODE, the TPS53315 automatically reduces the switching frequency at light-load conditions to maintain high efficiency. Detailed operation is described as follows. As the output current decreases from heavy load condition, the inductor current is also reduced and eventually comes to the point that its rippled valley touches zero level, which is the boundary between continuous conduction and discontinuous conduction modes. The synchronous MOSFET is turned off when this zero inductor current is detected. As the load current further decreases, the converter runs into discontinuous conduction mode (DCM). The on-time is maintained as it was in the continuous conduction mode so that it takes longer time to discharge the output capacitor with smaller load current to the level of the reference voltage. The transition point to the light-load operation IOUT(LL) (i.e., the threshold between continuous and discontinuous conduction mode) can be calculated as shown in Equation 3. IOUT(LL ) = (VIN - VOUT )´ VOUT 1 ´ 2 ´ L ´ fSW VIN where • ƒSW is the PWM switching frequency (3) Switching frequency versus output current in the light load condition is a function of L, VIN and VOUT, but it decreases almost proportionally to the output current from the IOUT(LL) given in Equation 3. For example, it is 60 kHz at IOUT(LL)/5 if the frequency setting is 300 kHz. Adaptive Zero Crossing The TPS53315 has an adaptive zero crossing circuit which performs optimization of the zero inductor current detection at skip mode operation. This function pursues ideal low-side MOSFET turning off timing and compensates inherent offset voltage of the Z-C comparator and delay time of the Z-C detection circuit. It prevents SW-node swing-up caused by postponed detection and minimizes diode conduction period caused by premature detection. As a result, better light-load efficiency is delivered. Forced Continuous Conduction Mode When the MODE pin is tied to PGOOD through a resistor, the controller keeps continuous conduction mode (CCM) during light-load conditions. In this mode, the switching frequency is maintained over the entire load range which is suitable for applications needing tight control of the switching frequency at a cost of lower efficiency. Power Good The TPS53315 has powergood output that indicates high when switcher output is within the target. The powergood function is activated after soft-start has finished. If the output voltage becomes within +10% or –5% of the target value, internal comparators detect the powergood state and the powergood signal becomes high after a 1-ms internal delay. If the output voltage goes outside of +15% or –10% of the target value, the power-good signal becomes low after two microsecond (2-ms) internal delay. The powergood output is an open drain output and must be pulled up externally. In order for the PGOOD logic to be valid, the VDD input must be higher than 1 V. To avoid invalid PGOOD logic before the TPS53315 is powered up, it is recommended the PGOOD be pull to VREG (either directly or through a resistor divider) because VREG remains low when the device is off. Current Sense and Overcurrent Protection TPS53315 has cycle-by-cycle overcurrent limiting control. The inductor current is monitored during the OFF state and the controller maintains the OFF state during the period in that the inductor current is larger than the overcurrent trip level. In order to provide both good accuracy and cost effective solution, TPS53315 supports temperature compensated MOSFET RDS(on) sensing. The TRIP pin should be connected to GND through the trip voltage setting resistor, RTRIP. The TRIP pin sources ITRIP current, which is 10 mA typically at room temperature, and the trip level is set to the OCL trip voltage VTRIP as shown in Equation 4. VTRIP (mV ) = RTRIP (kW )´ ITRIP (mA ) 20 (4) Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS53315 TPS53315 www.ti.com SLUSAE6 – DECEMBER 2010 The inductor current is monitored by the voltage between the GND pin and the SW pin so that the SW pin should be connected to the drain terminal of the low-side MOSFET properly. ITRIP has 4700 ppm/°C temperature slope to compensate the temperature dependency of the RDS(on). The GND pin is used as the positive current sensing node. The GND pin should be connected to the proper current sensing device, (for example, the source terminal of the low-side MOSFET.) As the comparison is done during the OFF state, VTRIP sets the valley level of the inductor current. Thus, the load current at the overcurrent threshold, IOCP, can be calculated as shown in Equation 5. IOCP = VTRIP (8 ´ RDS(on) ) IIND(ripple) + 2 = VTRIP (8 ´ RDS(on) ) + (VIN - VOUT )´ VOUT 1 ´ 2 ´ L ´ fSW VIN (5) In an overcurrent condition, the current to the load exceeds the current to the output capacitor, therefore the output voltage tends to decrease. Eventually, it crosses the undervoltage protection threshold and shuts down. After a hiccup delay (16 ms with 0.7-ms sort-start), the controller restarts. If the overcurrent condition remains, the procedure is repeated and the device enters hiccup mode. During CCM, the negative current limit (NCL) protects the internal FET from carrying too much current. The NCL detect threshold is set as the same absolute value as positive OCL but negative polarity. Note that the threshold continues to represent the valley value of the inductor current. Overvoltage and Undervoltage Protection The TPS53315 monitors a resistor divided feedback voltage to detect overvoltage and undervoltage. When the feedback voltage becomes lower than 70% of the target voltage, the UVP comparator output goes high and an internal UVP delay counter begins counting. After 1 ms, TPS53315 latches OFF both high-side and low-side MOSFETs drivers. The controller restarts after a hiccup delay (16 ms with 0.7-ms soft-start). This function is enabled 1.5 ms after the soft-start is completed. When the feedback voltage becomes higher than 120% of the target voltage, the OVP comparator output goes high and the circuit latches OFF the high-side MOSFET driver and latches ON the low-side MOSFET driver. The output voltage decreases. If the output voltage reaches the UV threshold, then both high-side MOSFET and low-side MOSFET driver is OFF and the device restarts after a hiccup delay. If the OV condition remains, both high-side MOSFET and low-side MOSFET driver remains OFF until the OV condition is removed. UVLO Protection The TPS53315 uses VREG undervoltage lockout protection (UVLO). When the VREG voltage is lower than the UVLO threshold voltage, the switch mode power supply shuts off. This is a non-latch protection. Thermal Shutdown TPS53315 includes a temperature monitoring feature. If the temperature exceeds the threshold value (typically 145°C), TPS53315 shuts off. When the temperature falls approximately 10°C below the threshold value, the device turns on again. This is a non-latch protection. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS53315 21 TPS53315 SLUSAE6 – DECEMBER 2010 www.ti.com External Parts Selection The external components selection is a simple process using D-CAP™ Mode. 1. CHOOSE THE INDUCTOR The inductance value should be determined to give the ripple current of approximately 1/4 to ½ of maximum output current. Larger ripple current increases output ripple voltage and improves signal-to-noise ratio and helps stable operation. L= 1 IIND(ripple ) ´ fSW ´ (V IN(max ) - VOUT )´ V OUT VIN(max ) = 3 IOUT(max ) ´ fSW ´ (V IN(max ) - VOUT VIN(max) )´ V OUT (6) The inductor requires a low DCR to achieve good efficiency. It also requires enough room above peak inductor current before saturation. The peak inductor current can be estimated in Equation 7. IIND(peak ) = ) ( VIN(max ) - VOUT ´ VOUT VTRIP 1 + ´ 8 ´ RDS(on ) L ´ fSW VIN(max ) (7) 2. CHOOSE THE OUTPUT CAPACITOR(S) When organic semiconductor capacitor(s) or specialty polymer capacitor(s) are used, for loop stability, capacitance and ESR should satisfy Equation 2. For jitter performance, Equation 8 is a good starting point to determine ESR. ESR = VOUT ´ 10 (mV )´ (1 - D) 0.6 (V )´ IIND(ripple ) = 10 (mV )´ L ´ fSW 0.6 (V ) = L ´ fSW (W ) 60 where • • • D is the duty factor tSW is the switching period the required output ripple slope is approximately 20 mV per tSW in terms of VVFB (8) 3. DETERMINE THE VALUE OF R1 AND R2 The output voltage is programmed by the voltage-divider resistor, R1 and R2 shown in Figure 37. R1 is connected between VFB pin and the output, and R2 is connected between the VFB pin and GND. Recommended R2 value is from 10kΩ to 20kΩ. Determine R1 using Equation 9. IIND(ripple ) ´ ESR - 0.6 VOUT 2 ´ R2 R1 = 0.6 (9) 22 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS53315 TPS53315 www.ti.com SLUSAE6 – DECEMBER 2010 External Parts Selection with All Ceramic Output Capacitors When ceramic output capacitors are used, the stability criteria in Equation 2 cannot be satisfied. The ripple injection approach as shown in Equation 10 is implemented to increase the ripple on the VFB pin and make the system stable. C2 can be fixed at 1 nF. The value of C1 can be selected between 10 nF to 200 nF. The increased ripple on the VFB pin causes the increase of the VFB DC value. The AC ripple coupled to the VFB pin has two components, one coupled from SW node and the other coupled from VOUT and they can be calculated using Equation 10 and Equation 11. V - VOUT D ´ VINJ _ SW = IN R7 ´ C1 fSW (10) VINJ _ OUT = ESR ´ IIND(ripple ) + IIND(ripple ) 8 ´ COUT ´ fSW (11) The DC value of VFB can be calculated by Equation 12: VINJ _ SW + VINJ _ OUT VVFB = 0.6 + 2 (12) And the resistor divider value can be determined by Equation 13: - VFB V ´ R2 R1 = OUT VFB (13) LAYOUT CONSIDERATIONS Certain points must be considered before starting a layout work using the TPS53315. • The power components (including input/output capacitors, inductor and TPS53315) should be placed on one side of the PCB (solder side). Other small signal components should be placed on another side (component side). At least one inner plane should be inserted, connected to ground, in order to shield and isolate the small signal traces from noisy power lines. • All sensitive analog traces and components such as VFB, PGOOD, TRIP, MODE and RF should be placed away from high-voltage switching nodes such as LL, VBST to avoid coupling. Use internal layer(s) as ground plane(s) and shield feedback trace from power traces and components. • Place the VIN decoupling capacitors as close to the VIN and PGND pins as possible to minimize the input AC current loop. • Since the TPS53315 controls output voltage referring to voltage across the VOUT capacitor, the top-side resistor of the voltage divider should be connected to the positive node of VOUT capacitor. In a same manner both bottom side resistor and GND pad of the device should be connected to the negative node of VOUT capacitor. The trace from these resistors to the VFB pin should be short and thin. Place on the component side and avoid via(s) between these resistors and the device. • Connect the overcurrent setting resistors from TRIP pin to ground and make the connections as close as possible to the device. The trace from TRIP pin to resistor and from resistor to ground should avoid coupling to a high-voltage switching node. • Connect the frequency setting resistor from RF pin to ground, or to the VREG pin, and make the connections as close as possible to the device. The trace from the RF pin to the resistor and from the resistor to ground should avoid coupling to a high-voltage switching node. • Connect the MODE setting resistor from MODE pin to ground, or to the PGOOD pin, and make the connections as close as possible to the device. The trace from the MODE pin to the resistor and from the resistor to ground should avoid coupling to a high-voltage switching node. • The PCB trace defined as switch node, which connects the LL pins and high-voltage side of the inductor, should be as short and wide as possible. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS53315 23 PACKAGE OPTION ADDENDUM www.ti.com 27-Dec-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) TPS53315RGFR ACTIVE VQFN RGF 40 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Purchase Samples TPS53315RGFT ACTIVE VQFN RGF 40 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 10-Jan-2011 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS53315RGFR VQFN RGF 40 3000 330.0 16.4 5.25 7.25 1.45 8.0 16.0 Q1 TPS53315RGFT VQFN RGF 40 250 180.0 16.4 5.25 7.25 1.45 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 10-Jan-2011 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS53315RGFR VQFN RGF 40 3000 346.0 346.0 33.0 TPS53315RGFT VQFN RGF 40 250 190.5 212.7 31.8 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety-critical applications. TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Audio www.ti.com/audio Communications and Telecom www.ti.com/communications Amplifiers amplifier.ti.com Computers and Peripherals www.ti.com/computers Data Converters dataconverter.ti.com Consumer Electronics www.ti.com/consumer-apps DLP® Products www.dlp.com Energy and Lighting www.ti.com/energy DSP dsp.ti.com Industrial www.ti.com/industrial Clocks and Timers www.ti.com/clocks Medical www.ti.com/medical Interface interface.ti.com Security www.ti.com/security Logic logic.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Power Mgmt power.ti.com Transportation and Automotive www.ti.com/automotive Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com Wireless www.ti.com/wireless-apps RF/IF and ZigBee® Solutions www.ti.com/lprf TI E2E Community Home Page e2e.ti.com Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2011, Texas Instruments Incorporated