SCBS023C − MARCH 1989 − REVISED APRIL 1994 • • • • • • • • NT PACKAGE (TOP VIEW) BiCMOS Process With CMOS Inputs and TTL Outputs Substantially Reduces Standby Current Input Has 50-Ω Pullup Resister Bus-Structured Pinout Functionally Equivalent to SN74ALS29846 and AMD Am29846 Provides Extra Data Width Necessary For Wider Address / Data Paths or Buses With Parity Power-Up High-Impedance State Buffered Control Inputs to Reduce DC Loading Effects Packaged in Standard Plastic 300-mil DIP (NT) OE1 OE2 1D 2D 3D 4D 5D 6D 7D 8D CLR GND 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC OE3 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q PRE LE description The SN74BCT29846 features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight latches of the SN74BCT29846 are transparent D-type latches. The SN74BCT29846 has inverting data (D) inputs. Since clear (CLR) and preset (PRE) are independent of the clock, taking the CLR input low will cause the eight Q outputs to go low. Taking the PRE input low will cause the eight Q outputs to go high. When both PRE and CLR are taken low, the outputs will follow the preset condition. The buffered output-enable (OE1, OE2, and OE3) inputs can be used to place the eight outputs in either a normal logic state (high or low levels) or a high-impedance state. The outputs are also in the high-impedance state during power-up and power-down conditions. The outputs remain in the high-impedance state while the device is powered-down. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive the bus lines in a bus-organized system without need for interface or pull-up components. The output enables do not affect the internal operation of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The SN74BCT29846 is characterized for operation from 0°C to 70°C. FUNCTION TABLE INPUTS PRE CLR OE1 OE2 OE3 LE D OUTPUT Q H L X L L L X X H L L L L X X L H H L L L H L H H H L L L H H L H H L L L L X Q0 X X X X H X X Z X X X H X X X Z X X H X X X X Z Copyright 1994, Texas Instruments Incorporated !"#$ % &'!!($ #% )'*+&#$ ,#$(!,'&$% &!" $ %)(&&#$% )(! $.( $(!"% (/#% %$!'"($% %$#,#!, 0#!!#$1- !,'&$ )!&(%%2 ,(% $ (&(%%#!+1 &+',( $(%$2 #++ )#!#"($(!%- • DALLAS, TEXAS 75265 • HOUSTON, TEXAS 77251−1443 POST OFFICE BOX 655303 POST OFFICE BOX 1443 1 SCBS023C − MARCH 1989 − REVISED APRIL 1994 logic symbol† logic diagram (positive logic) 1 OE1 OE2 OE3 PRE CLR LE 1D 2D 3D 4D 5D 6D 7D 8D OE1 OE2 OE3 & 2 EN 23 14 11 13 3 4 PRE S2 R LE C1 1D 2 22 21 5 20 6 19 7 18 8 17 9 16 10 15 14 13 3 S2 C1 1D R 4 S2 C1 1D R 5 S2 C1 1D R 6 S2 C1 1D R 7 S2 C1 1D R 8 S2 C1 1D R 9 S2 C1 1D R 10 S2 C1 1D R 1Q 2Q 1D 3Q 2 22 1Q 4Q 5Q 6Q 2D 7Q 2 21 2Q 8Q † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 3D 4D 5D 6D 7D 8D CLR 2 1 2 23 • 11 POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 2 2 2 2 2 2 20 19 18 17 16 15 3Q 4Q 5Q 6Q 7Q 8Q SCBS023C − MARCH 1989 − REVISED APRIL 1994 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions MIN MAX 4.5 5.5 UNIT VCC VIH Supply voltage VIL IOH Low-level input voltage 0.8 V High-level output current −24 mA IOL TA Low-level output current 48 mA 70 °C High-level input voltage 2 Operating free-air temperature 0 V V electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK TEST CONDITIONS VCC = 4.5 V, VOH VCC = 4.5 V VOL IOZH VCC = 4.5 V, VCC = 5.5 V, IOZL II VCC = 5.5 V, VCC = 5.5 V, IIH IIL VCC = 5.5 V, VCC = 5.5 V, IOS§ VCC = 5.5 V, ICC VCC = 5.5 V II = − 18 mA IOH = − 15 mA IOH = − 24 mA IOL = 48 mA MIN TYP‡ 2.4 VI = 0.4 V VO = 0 UNIT −1.2 V 3.2 V 2 0.35 VO = 2.7 V VO = 0.4 V VI = 7 V VI = 2.7 V MAX −10 −75 0.5 V 20 mA −20 mA 0.1 mA −75 µA −0.2 mA −275 mA Outputs high 3 7 Outputs low 24 35 3 7 Outputs disabled mA ‡ All typical values are at VCC = 5 V, TA = 25°C. § Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • 3 SCBS023C − MARCH 1989 − REVISED APRIL 1994 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) MIN tw Pulse duration PRE low 7 CLR low 5 LE high 4 Data tsu Setup time before LE↓ th Hold time, data after LE↓ MAX UNIT ns 1.5 PRE or CLR, inactive state ns 2 3.5 ns switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Note 1) FROM (INPUT) TO (OUTPUT) tPLH tPHL D Any Q tPLH tPHL LE Any Q tPLH tPHL PRE Any Q tPLH tPHL CLR Any Q tPZH tPZL OE Any Q tPHZ tPLZ OE Any Q PARAMETER VCC = 5 V, TA = 25°C MIN MAX 8 1.5 9 7 1.5 8 6 8 1.5 10 1.5 6 8 1.5 10 1.5 6 11 1.5 12 1.5 6 11 1.5 12 1.5 6 11 1.5 12 1.5 6 11 1.5 12 2 10 13 2 15 2 10 13 2 15 2 6 8 2 10 2 6 8 2 10 MIN TYP MAX 1.5 5.7 1.5 4.5 1.5 NOTE 1: Load circuits and voltage waveforms are shown in Section 1. 4 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 • UNIT ns ns ns ns ns ns IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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