SDAS127 − APRIL 1987
•
•
•
•
•
•
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•
NT Package
(Top View)
Center VCC and GND Configuration
Provides Minimum Lead Inductance in High
Current Switching Applications
3-State Buffer-Type Outputs Drive
Bus-Lines Directly
Bus-Structured Pinout
Provide Extra Bus Driving Latches
Necessary for Wider Address/Data Paths or
Buses With Parity
Buffered Control Inputs to Reduce DC
Loading
5Q
4Q
3Q
2Q
1Q
1
24
2
23
3
22
4
21
5
20
VCC
OC
1D
2D
3D
4D
5D
6
19
7
18
8
17
9
16
10
15
11
14
12
13
6Q
7Q
8Q
9Q
PRE
C
GND
CLR
9D
8D
7D
6D
Power-Up High Impedance
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description
This 9-bit latch device features three-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. It is particularly
suitable for implementing buffer registers, I/O
ports, bidirectional bus drivers, and working
registers.
The nine latches are transparent D-type and have
noninverting data (D) inputs.
A buffered output control (OC) input can be used
to place the nine outputs in either a normal logic
state (high or low levels) or a high-impedance
state. In the high-impedance state, the outputs
neither load nor drive the bus lines significantly.
The high-impedance state and increased drive
provide the capability to drive the bus lines in a
bus-organized system without need for interface
or pullup components.
The output control (OC) does not affect the
internal operation of the flip-flops. Old data can be
retained or new data can be entered while the
outputs are off.
The SN74AS1843 is characterized for operation
from 0°C to 70°C.
FUNCTION TABLE
INPUTS
OUTPUT
PRE
CLR
OC
C
D
Q
L
H
H
H
H
X
L
H
H
H
L
L
L
L
L
X
X
H
H
L
X
X
L
H
X
H
L
L
H
QO
X
X
H
X
X
Z
logic symbol †
OC
PRE
CLR
C
1D
2D
3D
4D
5D
6D
7D
8D
9D
7
20
17
19
8
EN
S2
R
C1
1D
2
5
9
4
10
3
11
2
12
1
13
24
14
23
15
22
16
21
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
9Q
† This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12,
Copyright 1987, Texas Instruments Incorporated
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POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SDAS127 − APRIL 1987
logic diagram (positive logic)
OC
PRE
CLR
C
1D
2D
3D
4D
5D
6D
7D
8D
9D
7
20
17
19
8
S
C1
1D
R
9
S
C1
1D
R
10
S
C1
1D
R
11
S
C1
1D
R
12
S
C1
1D
R
13
S
C1
1D
R
14
S
C1
1D
R
15
S
C1
1D
R
16
S
C1
1D
R
5
1Q
4
2Q
3
3Q
2
4Q
1
5Q
24
6Q
23
7Q
22
8Q
21
9Q
absolute maximum ratings over operating free-air temperature range (unless otherwise noted) †
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 65°C to 150°C
† Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the “Recommended Operating Conditions” section
of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
2
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• DALLAS, TEXAS 75265
SDAS127 − APRIL 1987
recommended operating conditions
MIN
NOM
MAX
4.5
5
5.5
UNIT
VCC
VIH
Supply voltage
VIL
IOH
Low-level input voltage
0.8
V
High-level output current
−24
mA
IOL
Low-level output current
48
mA
High-level input voltage
2
CLR or PRE low
4
C high
4
V
V
tw
Pulse duration, enable C high
tsu
th
Setup time, data before enable C ↓
2.5
ns
Hold time, data after enable C ↓
2.5
ns
tr
Recovery time
TA
Operating free-air temperature
PRE
15
CLR
14
ns
ns
0
70
°C
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
PARAMETER
VIK
TEST CONDITIONS
VCC = 4.5 V,
VCC = 4.5 V,
II = − 18 mA
IOH = − 2 mA
VCC = 4.5 V,
VCC = 4.5 V,
IOH = − 15 mA
IOH = − 24 mA
VOL
VCC = 4.5 V,
VCC = 4.5 V,
IOL = 32 mA
IOL = 48 mA
IOZH
IOZL
VCC = 5.5 V,
VCC = 5.5 V,
VO = 2.7 V
VO = 0.4 V
II
IIH
VCC = 5.5 V,
VCC = 5.5 V,
VI = 7 V
VI = 2.7 V
IIL
IO‡
VCC = 5.5 V,
VCC = 5.5 V,
VI = 0.4 V
VO = 2.25 V
VOH
ICC
VCC = 5.5 V,
MIN
VCC − 2
2.4
TYP†
MAX
UNIT
−1.2
V
3.2
V
2
0.35
−30
0.5
V
50
µA
−50
µA
0.1
mA
20
µA
−.05
mA
−112
mA
Output high
37
62
Output low
56
92
Outputs disabled
56
92
mA
† All typical values are at VCC = 5 V, TA = 25°C.
‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SDAS127 − APRIL 1987
switching characteristics over recommended ranges of supply voltage and free-air temperature
(see Note 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MAX
1
6.5
1
9
2
12
2
12
Q
2
10
ns
Q
2
13
ns
2
10.5
2
13.5
1
8
1
8
D
Q
tPLH
tPHL
C
Q
PRE
CLR
tPZH
tPZL
OC
Q
tPHZ
tPLZ
OC
Q
NOTE 2: Load circuit and voltage waveforms are shown in Section 1 of the ALS/AS Logic Data Book, 1986.
4
POST OFFICE BOX 655303
UNIT
MIN
tPLH
tPHL
tPLH
tPHL
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
R1 = 500 Ω,
R2 = 500 Ω,
TA = MIN to MAX
• DALLAS, TEXAS 75265
ns
ns
ns
ns
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