CY25822-2 CK-SSC Spread Spectrum Clock Generator Features • • • • • • • 3.3V operation 48- and 66-MHz frequency support Selectable slew rate control 350-pS jitter I2C programmability 500-µA power-down current Spread Spectrum for best electromagnetic interference (EMI) reduction • 8-pin SOIC package Block Diagram VDD REFOUT Clock Input Freq. Divider M Phase Detector Charge Pump Post Dividers VCO CLKOUT (SSCG Output) Modulating Waveform SDATA SCLOCK PWRDWN# Σ Logic Control Feedback Divider N PLL GND Pin Configuration C L K IN 1 8 *P W R D W N # VDD 2 7 SC LO C K C Y 2 5 8 2 2 -2 6 SDATA GND 3 C LKO U T 4 5 REFOUT * 1 5 0 K Ω P u ll-u p Cypress Semiconductor Corporation Document #: 38-07531 Rev. ** • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised March 18, 2003 CY25822-2 Pin Description Pin No. Pin Name Pin Type 1 CLKIN Input Pin Description 48-MHz or 66-MHz Clock Input. 2 VDD Power Power Supply for PLL and Outputs. 3 GND Ground Ground for Outputs. 4 CLKOUT Output 48-MHz or 66-MHz Spread Spectrum Clock Output. 5 REFOUT Output Non-spread Spectrum Reference Clock Output. 6 SDATA I/O 7 SCLOCK Input 8 PWRDWN# Output I2C-compatible SDATA. I2C-compatible SCLOCK. LVTTL Input for PowerDown# Active Low. Serial Data Interface Data Protocol To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions such as individual clock output buffers, etc., can be individually enabled or disabled. The clock driver serial protocol accepts byte write, byte read, block write, and block read operation from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individual indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 1. The registers associated with the Serial Data Interface initializes to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface can also be used during system operation for power management functions. The block write and block read protocol is outlined in Table 2 while Table 3 outlines the corresponding byte write and byte read protocol.The slave receiver address is 11010100 (D4h). Table 1. Command Code Definition Bit 7 Description 0 = Block read or block write operation 1 = Byte read or byte write operation (6:0) Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be ’0000000’ Table 2. Block Read and Block Write Protocol Block Write Protocol Bit 1 2:8 Description Start Slave address – 7 bits Block Read Protocol Bit 1 2:8 Description Start Slave address – 7 bits 9 Write = 0 9 Write = 0 10 Acknowledge from slave 10 Acknowledge from slave 11:18 19 20:27 28 29:36 37 38:45 Command Code – 8 bits '00000000' stands for block operation 11:18 Command Code – 8 bits '00000000' stands for block operation Acknowledge from slave 19 Acknowledge from slave Byte Count – 8 bits 20 Repeat start Acknowledge from slave Data byte 1 – 8 bits Acknowledge from slave Data byte 2 – 8 bits 21:27 28 29 30:37 46 Acknowledge from slave .... ...................... .... Data Byte (N–1) –8 bits 47 .... Acknowledge from slave 48:55 Document #: 38-07531 Rev. ** 38 39:46 Slave address – 7 bits Read = 1 Acknowledge from slave Byte count from slave – 8 bits Acknowledge Data byte from slave – 8 bits Acknowledge Data byte from slave – 8 bits Page 2 of 9 CY25822-2 Table 2. Block Read and Block Write Protocol (continued) .... Data Byte N –8 bits 56 Acknowledge .... Acknowledge from slave .... Data bytes from slave/Acknowledge .... Stop .... Data byte N from slave – 8 bits .... Not Acknowledge .... Stop Table 3. Byte Read and Byte Write Protocol Byte Write Protocol Bit Byte Read Protocol Description 1 Bit Start 2:8 1 Slave address – 7 bits 2:8 Description Start Slave address – 7 bits 9 Write = 0 9 Write = 0 10 Acknowledge from slave 10 Acknowledge from slave 11:18 Command Code – 8 bits '1xxxxxxx' stands for byte operation, bits[6:0] of the command code represents the offset of the byte to be accessed 19 20:27 11:18 Command Code – 8 bits '1xxxxxxx' stands for byte operation, bits[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave 19 Acknowledge from slave Data byte from master – 8 bits 20 Repeat start 28 Acknowledge from slave 29 Stop 21:27 28 29 30:37 Slave address – 7 bits Read = 1 Acknowledge from slave Data byte from slave – 8 bits 38 Not Acknowledge 39 Stop Byte 0: Control Register Bit @Pup Pin# Name Pin Description 7 1 4 SS0 – 6 0 4 SS1 – 5 0 4 SS2 – 4 0 4 SS3 – 3 1 Not Applicable Reserved, must be written as 1 2 1 4, 5 CLKOUT, REFOUT Power-down three-state enable 0 = three-state outputs, 1 = drive outputs low (Applies only in Power Down State) 1 1 4 CLKOUT Spread Spectrum enable 0 = spread off, 1 = spread on 0 0 Not Applicable No Pins Table 4. Spread Spectrum Select SS3 SS2 SS1 SS0 Spread Mode Spread Amount% 0 0 0 0 Down 0.8 0 0 0 1 Down 1.0 0 0 1 0 Down 1.25 0 0 1 1 Down 1.5 0 1 0 0 Down 1.75 Document #: 38-07531 Rev. ** Page 3 of 9 CY25822-2 Table 4. Spread Spectrum Select (continued) SS3 SS2 SS1 SS0 Spread Mode Spread Amount% 0 1 0 1 Down 2.0 0 1 1 0 Down 2.5 0 1 1 1 Down 3.0 1 0 0 0 Center ±0.3 1 0 0 1 Center ±0.4 1 0 1 0 Center ±0.5 1 0 1 1 Center ±0.6 1 1 0 0 Center ±0.8 1 1 0 1 Center ±1.0 1 1 1 0 Center ±1.25 1 1 1 1 Center ±1.5 Byte 1: Control Register Bit @Pup Pin# Name Pin Description 7 1 5 REFEN REFOUT enable 0 = disabled, 1 = enabled 6 1 5 REFSLEW REFOUT edge rate control 0 = slow, 1 = nominal 5 0 Not Applicable Reserved. 4 0 Not Applicable Reserved 3 1 4 CLKSLEW CLKOUT edge rate control 0 = slow, 1 = nominal 2 1 4 CLKEN CLKOUT enable 0 =disabled, 1 = enabled 1 0 Not Applicable Reserved 0 0 Not Applicable Reserved Bytes 2 through 5: Reserved Registers PWRDWN# (Power-down) Clarification Byte 6: Vendor/Revision ID Register The PWRDWN# (Power-down) pin is used to shut off ALL clocks prior to shutting off power to the device. PWRDWN# is an asynchronous active LOW input. This signal is synchronized internally to the device powering down the clock synthesizer. PWRDWN# is an asynchronous function for powering up the system. When PWRDWN# is low, all clocks are driven to a LOW value and held there and the VCO and PLLs are also powered down. All clocks are shut down in a synchronous manner so has not to cause glitches while transitioning to the low ‘stopped’ state. When PWRDWN# is deasserted the clocks should remain stopped until the VCO is stable and within specification (tSTABLE). A stopped clock is either tri-stated or driven low depending on the state of the tri-state enable I2C register bit. CY25822 clocks that are stopped in the driven state are driven low. Bit @Pup Pin# Name 7 0 – – Revision ID Bit 3 Pin Description 6 0 – – Revision ID Bit 2 5 0 – – Revision ID Bit 1 4 0 – – Revision ID Bit 0 3 1 – – Vendor ID Bit 3 2 0 – – Vendor ID Bit 2 1 0 – – Vendor ID Bit 1 0 0 – – Vendor ID Bit 0 The CLKIN input must be on and within specified operating parameters before PWRDWN# is asserted and it must remain in this state while PWRDWN# is asserted. Document #: 38-07531 Rev. ** Page 4 of 9 CY25822-2 PWRDWN# CLKOUT REFOUT Figure 1. Power-down Assertion PD# <3.0m s C LK O U T R E FO U T Figure 2. Power-down Deassertion CLKOUT and REFOUT Enable Clarification The CLKOUT enable and REFOUT enable I2C register bits are used to shot-off the CLKOUT and REFOUT clocks individually. The VCO and crystal oscillator must remain on. A shutdown clock is driven low. ALL clocks need to be stopped in a predictable manner. All clocks need to be shutdown without any glitches or other abnormal behavior while transitioning to a stopped state. Similarly when CLKOUT or REFOUT is enabled the clock must start in a predictable manner without any glitches or abnormal behavior. Document #: 38-07531 Rev. ** Page 5 of 9 CY25822-2 Table 5. Absolute Maximum Ratings Parameter Description Condition Min. Max. Unit VDD Core Supply Voltage –0.5 4.6 V VDD_A Analog Supply Voltage –0.5 4.6 V VIN Input Voltage Relative to V SS –0.5 VDD + 0.5 VDC TS Temperature, Storage Non Functional –65 +150 °C TA Temperature, Operating Ambient Functional 0 70 °C TJ Temperature, Junction Functional – 150 °C ESDHBM ESD Protection (Human Body Model) MIL-STD-883, Method 3015 – Volts UL–94 Flammability Rating @1/8 in. MSL Moisture Sensitivity Level 2000 V–0 1 Table 6. DC Parameters (TA = 0°C to +70°C, VDD = 3.3V ± 5%) Parameter Description Condition Min. Max Unit VDD Supply Voltage – 3.135 3.465 V VIH Input High Voltage – 2.0 VDD + 0.3 V Notes VDD = 3.3 ± 5% VIL Input Low Voltage – VSS – 0.3 0.8 V IIL1 Input Leakage Current SCLOCK or SDATA –25 +25 µA IIL2 Input Leakage Current PWRDWN# –75 –15 µA VOH Output High Voltage IOH = –4 mA 2.4 – V Single edge is required to be monotonic when transitioning through this region. VOL Output Low Voltage IOL = 4 mA – 0.4 V Single edge is required to be monotonic when transitioning through this region. CIN Input Pin Capacitance – – 5 pF COUT Output Pin Capacitance – – 6 pF LIN Pin Inductance – – 7 nH TA Ambient Temperature – 0 70 °C IDD1 Supply Current @ 66 MHz – 50 mA IDD2 Supply Current @ 48 MHz – 40 mA IPD Power Down Supply Current – – 500 µA No air flow Table 7. AC Parameters (TA = 0°C to +70°C, VDD = 3.3V ± 5%) Parameter Min. Max. Unit tHIGH CLK High Time, 48MHz Description Measured @2.4V 9.45 10.95 ns Specification applies to 48MHz output mode. tLOW CLK, Low Time, 48MHz Measured @0.4V 8.50 10.10 ns Specification applies to 48MHz output mode. tHIGH CLK High Time, 66MHz Measured @2.4V 6.85 7.90 ns Specification applies to 66.7MHz output mode. tLOW CLK Low Time, 66MHz Measured @0.4V 5.95 6.95 ns Specification applies to 66.7MHz output mode. tRISEH1 Rising Edge Rate Measured from 0.4V to 2.4V REFOUT and CLOCKOUT 2.0 5.0 V/ns High Buffer Strength Refer to I2C Control tFALLH1 Falling Edge Rate Measured from 2.4V to 0.4V REFOUT and CLOCKOUT 2.0 5.0 V/ns High Buffer Strength Refer to I2C Control tRISEL1 Rising Edge Rate Measured from 0.4V to 2.4V REFOUT and CLOCKOUT 1.33 4.0 V/ns Low Buffer Strength Refer to I2C Control Document #: 38-07531 Rev. ** Conditions Notes Page 6 of 9 CY25822-2 Table 7. AC Parameters (TA = 0°C to +70°C, VDD = 3.3V ± 5%) (continued) Parameter Conditions Min. Max. tFALLL1 Falling Edge Rate Description Measured from 2.4V to 0.4V REFOUT and CLOCKOUT 1.33 4.0 tRISEH2 Rise Time Measured from 0.4V to 2.4V REFOUT and CLOCKOUT 0.4 1.0 ns High Buffer Strength Refer to I2C Control tFALLH2 Fall Time Measured from 2.4V to 0.4V REFOUT and CLOCKOUT 0.4 1.0 ns High Buffer Strength Refer to I2C Control tRISEL2 Rise Time Measured from 0.4V to 2.4V REFOUT and CLOCKOUT 0.5 1.5 ns Low Buffer Strength Refer to I2C Control tFALLL2 Fall Time Measured from 2.4V to 0.4V REFOUT and CLOCKOUT 0.5 1.5 ns Low Buffer Strength Refer to I2C Control TCYC1 Cycle to Cycle Jitter REFOUT – 500 ps SSCG is ON Cycle to Cycle Jitter CLOCKOUT TCYC2 LTJ tSTART Unit Notes V/ns Low Buffer Strength Refer to I2C Control – 250 ps SSCG is ON 10µS Period Jitter Applies to REFOUT at all (100KHz, Frequency Mod- times and CLOCKOUT when ulation Amplitude) SSCG is Off – 2.0 ns – Start up time – 3.0 ms From VDD = 2.0 V All outputs disabled Table 8. Signal Loading Table Clock Name Max Load (pF) CLKOUT, REFOUT 15 Ordering Information Part Number Package Type Product Flow CY25822SC–2 8-pin SOIC Commercial, 0°C to 70°C CY25822SC–2T 8-pin SOIC – Tape and Reel Commercial, 0°C to 70°C Document #: 38-07531 Rev. ** Page 7 of 9 CY25822-2 Package Diagram 8-lead (150-Mil) SOIC – S8 51-85066-*B Purchase of I2C components from Cypress, or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.All product and company names mentioned in this document are trademarks of their respective holders. Document #: 38-07531 Rev. ** Page 8 of 9 © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY25822-2 Document History Page Document Title: CY25822-2 CK-SSC Spread Spectrum Clock Generator Document Number: 38-07531 REV. ECN NO. Issue Date Orig. of Change ** 124462 03/19/03 RGL Document #: 38-07531 Rev. ** Description of Change New Data Sheet Page 9 of 9