MSP53C691 MIXED-SIGNAL PROCESSOR SPSS030A – DECEMBER 2000 – REVISED FEBRUARY 2001 D D D D D D Advanced, Catalog Speech Processor for High-Quality Sound, Capable of Unlimited Speech Duration Using External Memory Operates up to 12.32 MIPS Supports High-Quality Algorithms Such as MELP (1.0 Kbps – 3.5 Kbps at 8 kHz), CELP (3.0 Kbps – 11.2 kHz at 8 kHz Sampling Rate), ADPCM, Single Channel FM With CELP or MELP Speed and Pitch Shifting in MELP for Various Voice Effects Six Level Digital Gain Control 4 User Configurable I/O’s D D D D D D D Very Low-Power Operation, Ideal for Hand-Held Devices Low-Voltage Operation, Sustainable by Three (3) Batteries Three Reduced Power Standby Modes, Less Than 10 µA in Deep-Sleep Mode Resistor-Trimmed Oscillator or 32.768-kHz Crystal Reference Oscillator Direct Speaker Drive (32 Ω) (PDM) Interrupt Driven, 4- or 8-Bit Parallel Data Transfer Protocol Available in Die Form or 64-Pin PM Package description The MSP53C691 is a standard slave synthesizer from Texas Instruments that accepts compressed speech data from other microprocessors/microcontrollers and converts it to speech. This allows the TI MSP53C691 to be used with a master microprocessor/microcontroller in various speech-related products such as security systems, learning aids, games, and toys. High quality, low bit-rate coders, easy interface with the master microcontroller, digital gain control, low power sleep mode, and low voltage operation makes this device ideal for products requiring long duration speech, less development cycle times, and peripheral device control through the slave device. This device supports several speech synthesis algorithms that permit tradeoffs to meet the price performance requirements of various markets. The MSP53C691 implements a unique feature of playing a single channel FM music along with CELP or MELP speech data concurrently. This feature allows the user to speak a certain phrase in MELP or CELP with single channel music in the background. The MSP53C691 is optimized to support a 4-bit wide data transfer protocol. The device has two status bits and three control bits that control the communication protocol between the master and the slave. The MSP53C691 also has 1 bit (command/data) which differentiates between a command or speech data feeding into the slave. In 4-bit mode, various commands are sent to the slave during speech to perform various tasks. The MSP53C691 also supports the 8-bit wide data transfer but the support for commands is disabled during speaking-a-phrase. When speaking-a-phrase in 8-bit mode is complete, the MSP53C691 switches back to the 4-bit mode to receive the next command. Switching between 4-bit mode or 8 bit mode is permitted between speech data files. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2001, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 MSP53C691 MIXED-SIGNAL PROCESSOR SPSS030A – DECEMBER 2000 – REVISED FEBRUARY 2001 pin assignments NC V SS V SS NC NC NC NC NC NC NC NC NC NC NC NC NC MSP53C691 PM PACKAGE (TOP VIEW) VDD VDD 1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 2 47 R/W 3 46 STROBE 4 45 OUTRDY 5 44 INRDY 6 43 TEST SCANOUT SYNC SCANCLK SCANIN RESET PLL OSCIN OSCOUT VSS 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 DATA7 NC NC NC NC NC NC NC NC NC NC NC NC NC NC V DD 33 16 1718 19 20 21 22 23 24 25 26 27 28 29 30 31 32 NC – No internal connection NOTE: Pin 35 is DATA4 in 8-bit mode, or DATA/COMMAND in 4-bit mode. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 VSS DACP VDD DACM VDD PD4 PD5 PD6 PD7 DATA0 DATA1 DATA2 DATA3 DATA/COMMAND (DATA4) DATA5 DATA6 MSP53C691 MIXED-SIGNAL PROCESSOR SPSS030A – DECEMBER 2000 – REVISED FEBRUARY 2001 functional block diagram VSS VDD 4 5 PG0 SCANOUT SCANCLK Scan Interface Break Point Emulation OTP Program Serial Comm. SYNC Power G port O (EP)ROM 32k x (16 + 1) bit Test-Area (reserved) 0x0000 to 0x07FF User ROM 0x0800 to 0x7FEF INT vectors 0x7FF0 to 0x7FFF TEST Data MASTER/SLAVE 0x2C Comparator 1 Bit: PD5 vs PD4 – + PD0 Core DACP DAC DACM 32 Ω PDM 0x30 PD1 PCU RESET OSC Reference Resistor Trimmed 32 kHz nominal OSCIN or or OSCOUT Crystal Referenced 32.768 kHz PLL Prog. Counter Unit CU Initialization Logic PLL Filter D port I/O Instr. Decoder 0x18 PD2 Int 3 PD3 Int 4 Control 0x1C Computational Unit TIMER1 PRD1 0x3A TIM1 0x3B TIMER2 PRD2 0x3E TIM2 0x3F Clock Control 0x3D Gen. Control 0x38 Interrupt Processor FLAG MASK 0x39 0x38 DMAU Data C port I/O POST OFFICE BOX 655303 STROBE R/W PC0–7 BUS DRIVER Data 0x10 Control 0x14 A port I/O 0x000 to 0x027F OUTRDY PD4–7 Data Mem. Addr. RAM 640 x 17 bit (data) INRDY SLAVE LOGIC SCANIN Data 0x00 Control 0x04 • DALLAS, TEXAS 75265 DATA0–7 PA0–7 LATCH 3 MSP53C691 MIXED-SIGNAL PROCESSOR SPSS030A – DECEMBER 2000 – REVISED FEBRUARY 2001 Terminal Functions PIN NO. PAD NO. I/O 39–36 25–22 I/O Data bits 0 through 3 (in 4-bit or 8-bit mode) 35 21 I/O Data bit 4 (in 8-bit mode) Data/command control bit (in 4-bit mode). Low signal indicates command and high signal indicates data. 34–32 20–18 I/O Data bits 5 through 7 (8-bit mode only) Not used (4-bit mode only) INRDY 6 6 O An output signal from the slave to the microcontroller. A low signal indicates that the MSP53C691 is ready to accept data or command. A high signal indicates that the MSP53C691 is busy and the microcontroller must not write any data or command to it. OUTRDY 5 5 O An output signal from the slave to the microcontroller. A low signal indicates that the MSP53C691 is ready to send data or command to the microcontroller. PD4–PD7 General-purpose I/O bus NAME DATA0–DATA3 DATA4 or DATA/COMMAND DATA5–DATA7 DESCRIPTION 43–40 29–26 I/O R/W 3 3 I An input signal to the slave from the microcontroller. Read/write select signal which is set high for read operations or set low for write operations by the microcontroller. STROBE 4 4 I An input signal to the slave from the microcontroller. STROBE sequences read or write operations in conjunction with the R/W signal. This signal is pulsed high-low-high for read or write operations sequencing. OSCOUT 15 15 O Output of resistor/crystal oscillator OSCIN 14 14 I Input to resistor/crystal oscillator PLL 13 13 O Output of phase-lock-loop filter SCANIN† 11 39 I Scan port data input SCANOUT† SCANCLK† 8 35 O Scan port data output Reference Oscillator Signals Scan Port Control Signals 10 38 I Scan port clock SYNC† TEST† 9 37 I Scan port synchronization 7 36 I C604: test modes DACP 47 33 O Digital-to-analog plus output (+) DACM 45 31 O Digital-to-analog minus output(–) Digital-to-Analog Sound Output Initialization RESET 12 12 I Device initialization Power Signals‡ VDD 1, 2, 31, 44, 46‡ VSS 16, 48, 49‡, 64 1, 2, 17, 30, 32‡ 16, 34‡, 35, 36 — Processor power, 5 V nominal supply voltage — Ground pin † All pins must be N.C. ‡ Marked pins are VDD and VSS connections which service the DAC circuitry. These pins tend to sustain a higher current draw. A dedicated decoupling capacitor across these pins is therefore required. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP53C691 MIXED-SIGNAL PROCESSOR SPSS030A – DECEMBER 2000 – REVISED FEBRUARY 2001 MSP53C691 (4-bit mode) MSP53C691 (8-bit mode) 4 8 Number of data lines Number of control lines 3 (strobe, R/W, data/command) 2 (strobe, R/W) Number of status lines 2 (INRDY, OUTRDY) 2 (INRDY, OUTRDY) 4 4 Yes No Number of general-purpose I/O lines Support for commands (while speaking) VDD VDD 100 kΩ (each) 4.7 kΩ 100 kΩ 4.7 kΩ 4.7 kΩ Master MSP53C691 INRDY OUTRDY R/W STROBE DATA(0–3) DATA(0–3) 4 DATA/COMMAND RESET NOTE: STROBE R/W RESET DATA0–DATA3 PD4–PD7 DACP DACM DATA/COMMAND Active low strobe signal from microcontroller Read/write signal from microcontroller Active low reset signal from microcontroller Data bits 0 through 3 General-purpose I/O bus Output to speaker/amplifier Output to speaker/amplifier This bit determines if the data sent by the microcontroller is data or command. Figure 1. MSP53C691 Interfacing Diagram—4-Bit Mode POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 MSP53C691 MIXED-SIGNAL PROCESSOR SPSS030A – DECEMBER 2000 – REVISED FEBRUARY 2001 VDD VDD 4.7 kΩ 100 kΩ (each) 4.7 kΩ 4.7 kΩ Master MSP53C691 INRDY OUTRDY R/W STROBE DATA (0–7) DATA (0–7) 8 RESET NOTE: STROBE: R/W: RESET INRDY: OUTRDY: DATA0–DATA7 PD4–PD7 DACP DACM Active low strobe signal from microcontroller Read/write signal from microcontroller Active low reset signal from microcontroller. Active low indicates that the MSP53C691 is ready to accept data. Active low indicates that the MSP53C691 is ready to send data. Data bits 0 through 7 General-purpose I/O bus Output to speaker/amplifier Output to speaker/amplifier Figure 2. MSP53C691 Interfacing Diagram—8-Bit Mode read operation by the master The process for the read operation by the master is the same in either 4-bit or 8-bit mode. The read operation by the master happens when the slave wants to send something to the master. The read process is initiated by the slave by pulling OUTRDY low when it is ready. The following events take place during the read operation: D D D D D D D The MSP53C691 puts the data to be sent to the master on the internal bus. The MSP53C691 sets OUTRDY low to indicate that it is ready to send data to the microcontroller. The microcontroller sets R/W high to indicate a read operation. The microcontroller sets STROBE low. The data is available on the external data-bus at this point. The microcontroller reads the data from the bus. The microcontroller sets STROBE high. The MSP53C691 also pulls OUTRDY high at the rising edge of STROBE. The data is taken from the external data-bus after STROBE goes high. The microcontroller should latch or read in the data while STROBE is low. When the microcontroller sets STROBE high, the MSP53C691 sets OUTRDY high to indicate that the data has been successfully transferred. Figure 3 shows the sequence of events of the read operation. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP53C691 MIXED-SIGNAL PROCESSOR SPSS030A – DECEMBER 2000 – REVISED FEBRUARY 2001 read operation by the master (continued) a) Sequence of events for a single read operation: OUTRDY R/W STROBE DATA COMMAND/DATA b) Read—Two speech data transfer sequences: OUTRDY R/W STROBE DATA COMMAND/DATA Figure 3. Data Transfer – Read write operation by the master The process for the write operation by the master is the same in either 4-bit or 8-bit mode. The write operation by the master happens when the slave is ready to request data or command from the master. The write process is initiated by the slave by pulling INRDY low when the slave is ready to receive data. The following events take place during the write operation: D D D D D D The MSP53C691 sets INRDY low to indicate that it is ready to receive data from the microcontroller. The microcontroller sets R/W low to indicate a write operation. The microcontroller puts the data in the external data-bus. The microcontroller sets STROBE low after the data is valid. The microcontroller sets STROBE high after a minimum of 300 ns. The MSP53C691 also pulls INRDY high at the rising edge of STROBE. The data is latched in the MSP53C691 at the rising edge of STROBE. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 MSP53C691 MIXED-SIGNAL PROCESSOR SPSS030A – DECEMBER 2000 – REVISED FEBRUARY 2001 write operation by the master (continued) When the microcontroller sets STROBE high, the MSP53C691 sets INRDY high to indicate that the MSP53C691 is not ready to receive any more data. a) Sequence of events for a single write operation R/W STROBE INRDY DATA COMMAND/DATA b) Write—Two speech data transfer sequences R/W STROBE INRDY DATA COMMAND/DATA Figure 4. Data Transfer – Write 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP53C691 MIXED-SIGNAL PROCESSOR SPSS030A – DECEMBER 2000 – REVISED FEBRUARY 2001 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V Supply current, IDD (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 mA Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VDD + 0.3 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VDD + 0.3 V Storage temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 30°C to 125°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Unless otherwise noted, all voltages are measured with respect to VSS . 2. The total supply current includes the current out of all the I/O pins as well as the operating current of the device. recommended operating conditions MIN Supply voltage, VDD (with respect to VSS) MAX 3 5.2 CPU clock rate, f(CPU) (as programmed) 64 12,320 Load resistance between DACP and DACM, R(DAC) 32 Operating free-air temperature, TA Device functionality UNIT V kHz Ω 0 70 MIN MAX °C timing requirements t(RESET) tw1 Reset pulsed low, while ’C691 has power applied Pulse width required prior to a negative transition at pin (PD3 or PD5 interrupt) 100 2 tw2 Pulse width required prior to a positive transition at pin (PD2 or PD4 interrupt) 2 UNIT ns 1/FCPU 1/FCPU RESET t(RESET) Figure 5. Initialization Timing Diagram tw1 (PD3, PD5, or F port) tw1 tw2 (PD2, or PD4) tw2 Figure 6. MSP53C691 External Interrupt Pin Pulse Width Requirements tw1 and tw2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 MSP53C691 MIXED-SIGNAL PROCESSOR SPSS030A – DECEMBER 2000 – REVISED FEBRUARY 2001 dc electrical characteristics over recommended operating free-air temperature range, TA = 0°C – 70°C (unless otherwise noted) PARAMETER TEST CONDITIONS VDD = 3 V Threshold changes RESET VDD = 5.2 V High-level High level input voltage VIH Low-level Low level input voltage VIL MIN TYP† Positive going threshold 2.4 Negative going threshold 1.8 Hysteresis 0.6 Positive going threshold 3.3 Negative going threshold 2.9 Hysteresis 0.4 MAX V V VDD = 3 V VDD = 4.5 V 2 3 3 4.5 VDD = 5.2 V VDD = 3 V 3.5 5.2 0 1 VDD = 4.5 V VDD = 5.2 V 0 1.5 0 1.7 IOH§ High-level output current per pin of I/O port IOL§ Low-level output current per pin of I/O port IOH (DAC) High-level output DAC current VOH = 4 V IOL (DAC) Low-level output DAC current VOL = 0.5 V Ilkg Input leakage current Excludes OSCIN Standby current RESET is low Operating current VDD = 4.5 V, VDD = 4.5 V, FCLOCK = 12.32 MHz DAC off, ARM set, OSC disabled 0.05 Supply current VDD = 4.5 V, VDD = 4.5 V, DAC off, ARM set, OSC enabled 40 60 DAC off, ARM clear, OSC enabled 60 100 Vref = 1 to 4.25 V 25 50 I(STANDBY) IDD I(SLEEP-deep) I(SLEEP-mid) VOH = 4 V VDD = 4.5 V I(SLEEP-light) VIO Input offset voltage VDD = 4.5 V, R(PULLUP) F port pullup resistance VDD = 5 V ∆f(RTO ti ) (RTO–trim) Trim deviation ∆f(RTO lt) (RTO–volt) Voltage deviation ∆f(RTO t ) (RTO–temp) Temperature deviation ∆f(RTO (RTO–res)) Resistance deviation VOL = 0.5 V 0.05 R(RTO) = 470 kΩ, VDD = 4.5 V, TA = 25°C, f(RTO) = 8.192 MHz (PLL setting = 7 Ch)‡ RRTO = 470 kΩ, VDD = 3.5 to 5.2 V, f(RTO) = 8.192 MHz (PLL setting = 7 Ch)‡ TA = 25°C, R(RTO) = 470 kΩ, VDD = 4.5 V, TA = 0 to 70°C, f(RTO) = 8.192 MHz (PLL setting = 7 Ch)‡ VDD = 4.5 V, TA = 25°C, ROSC = 470 kΩ at ± 1%, f(RTO) = 8.192 MHz (PLL setting = 7 Ch)‡ V mA 5 mA –10 mA 20 mA 1 µA 10 µA mA 10 150 ± 1% V –2 15 70 UNIT µA mV kΩ ± 3% ± 1.5 15 %/V 0 03 ± 0.03 %/°C ±1 %/R † Typical voltage and current measurements taken at 25°C, ‡ The best trim value is selected at nominal temperature and voltage but the deviation due to the trim error is ignored. § This parameter cannot exceed 15 mA total per internal VDD pin. Port C and port D share 1 internal VDD. Ports A and G0 are used internally. external component absolute values PARAMETER R(RTO) RTO external resistance C(PLL) PLL external capacitance 10 TEST CONDITIONS TA = 25°C, TA = 25°C, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MAX UNIT 1% tolerance MIN 470 kΩ 10% tolerance 3300 pF MSP53C691 MIXED-SIGNAL PROCESSOR SPSS030A – DECEMBER 2000 – REVISED FEBRUARY 2001 MECHANICAL DATA PM (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 0,08 M 33 48 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 SQ 11,80 0,25 0,05 MIN 0°– 7° 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040152 / C 11/96 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Falls within JEDEC MS-026 May also be thermally enhanced plastic with leads connected to the die pads. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 PACKAGE OPTION ADDENDUM www.ti.com 30-Mar-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing MSP53C691PM OBSOLETE LQFP PM Pins Package Eco Plan (2) Qty 64 TBD Lead/Ball Finish Call TI MSL Peak Temp (3) Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996 PM (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 0,08 M 33 48 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 SQ 11,80 0,25 0,05 MIN 0°– 7° 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040152 / C 11/96 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Falls within JEDEC MS-026 May also be thermally enhanced plastic with leads connected to the die pads. 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