MSP50C604 MIXED-SIGNAL PROCESSOR SPSS028B – MAY 2000 – REVISED FEBRUARY 2001 D D D D D D D D D Advanced, Integrated Speech Synthesizer for High-Quality Sound Operates up to 12.32 MHz (Performs up to 12 MIPS) Slave Mode Enables Hours of Speech Using an External Processor and Memory Master Mode Allows 6.8 Mins of Speech Onboard Supports High-Quality Synthesis Algorithms such as MELP, CELP, LPC, ADPCM, and Polyphonic Music Simultaneous Speech Plus Music Capabilities Very Low-Power Operation, Ideal for Hand-Held Devices Low-Voltage Operation, Sustainable by Three (3) Batteries Reduced Power Standby Modes, Less Than 10 µA in Deep-Sleep Mode D D D D D D D D D D 16 General-Purpose I/O Pins (in Master Mode) or 4 General-Purpose I/O Pins (in Slave Mode) Resistor-Trimmed Oscillator or 32.768-kHz Crystal Reference Oscillator Slave Interface Logic Contains 64K Bytes-Words Onboard ROM (2K Words Reserved) 640-Word RAM Direct Speaker Drive (32 Ω) (PDM) One-Bit Comparator With Edge Detection Interrupt Service Serial Scan Port for In-Circuit Emulation, Monitor, and Test Available in Die Form or 64-Pin PM Package An Emulator Board (EPC50C604) Is Available for Code Development in Slave Mode description The MSP50C604 is a low-cost, mixed-signal processor that combines a speech synthesizer with a dedicated slave interface logic, general-purpose I/O, onboard ROM, and direct speaker-drive in a single package. The computational unit uses a powerful new DSP that gives the MSP50C604 unprecedented speed and computational flexibility compared with previous devices of its type. The MSP50C604 supports a variety of speech and audio coding algorithms, providing a range of options with respect to speech duration and sound quality. The device consists of a micro-DSP core, embedded program and data memory, and a self-contained clock generation system. General-purpose periphery is comprised of 16 bits of partially configurable I/O. The core processor is a general-purpose 16-bit microcontroller with DSP capability. The basic core block includes a computational unit (CU), data address unit, program address unit, two timers, eight-level interrupt processor, and several system and control registers. The core processor gives the MSP50C604 break-point capability in emulation. The processor is a Harvard type for efficient DSP algorithm execution, separating program and data memory blocks to permit simultaneous access. The ROM has a protection scheme to prevent third-party pirating. It is configured in 32K 17-bit words. The total ROM space is divided into two areas: 1) The lower 2K words are reserved by Texas Instruments for a built-in self-test 2) The upper 30K is for user program and data space. The data memory is internal static RAM. The RAM is configured in 640 17-bit words. All memories are designed to consume minimum power at a given system clock and algorithm acquisition frequency. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2001, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 MSP50C604 MIXED-SIGNAL PROCESSOR SPSS028B – MAY 2000 – REVISED FEBRUARY 2001 description (continued) A flexible clock generation system enables the software to control the clock over a wide frequency range. The implementation uses a phase-locked loop (PLL) circuit that drives the processor clock at a selectable frequency between the minimum and maximum achievable. Selectable frequencies for the processor clock are spaced apart in 65.536-kHz steps. The PLL clock-reference is also selectable; either a resistor-trimmed oscillator or a crystal-referenced oscillator may be used. Internal and external clock sources are controlled separately to provide different levels of power management. The periphery consists of two 8-bit-wide general-purpose I/O ports when operating in master mode, or four general-purpose I/O pins in slave mode. In the master mode, the bidirectional I/O can be configured under software control as either high-impedance inputs or as totem-pole output. They are controlled via addressable I/O registers. These features make the input port especially useful as a key-scan interface. Slave mode consists of four general-purpose I/O, four control pins, and eight bidirectional data pins. A simple one-bit comparator is also included in the periphery. The comparator is enabled by a control register, and its access is shared with two pins in one general-purpose I/O port. Rounding out the MSP50C604 periphery is a built-in pulse-density-modulated DAC (digital-to-analog converter) with direct speaker-drive capability. The following block diagram gives an overview of the MSP50C604 functionality. functional block diagram VSS VDD 4 5 PG0 SCANOUT SCANCLK Scan Interface Break Point Emulation OTP Program Serial Comm. SYNC Power G port O (EP)ROM 32k x (16 + 1) bit Test-Area (reserved) 0x0000 to 0x07FF User ROM 0x0800 to 0x7FEF INT vectors 0x7FF0 to 0x7FFF TEST Data MASTER/SLAVE 0x2C Comparator 1 Bit: PD5 vs PD4 – + PD0 Core DACP DAC DACM 32 Ω PDM 0x30 PCU RESET CU Initialization Logic OSC Reference Resistor Trimmed 32 kHz nominal OSCIN or or OSCOUT Crystal Referenced 32.768 kHz PLL 2 PLL Filter PD1 D port I/O Instr. Decoder Prog. Counter Unit 0x18 PD2 Int 3 PD3 Int 4 Control 0x1C Computational Unit TIMER1 PRD1 0x3A TIM1 0x3B TIMER2 PRD2 0x3E TIM2 0x3F Clock Control 0x3D Gen. Control 0x38 Interrupt Processor FLAG MASK 0x39 0x38 DMAU Data C port I/O POST OFFICE BOX 655303 STROBE/PD2 R/W/PD3 PC0–7 BUS DRIVER Data 0x10 Control 0x14 A port I/O 0x000 to 0x027F OUTRDY/PD1 PD4–7 Data Mem. Addr. RAM 640 x 17 bit (data) INRDY/PD0 SLAVE LOGIC SCANIN Data 0x00 Control 0x04 • DALLAS, TEXAS 75265 PC0–7 PA0–7 LATCH MSP50C604 MIXED-SIGNAL PROCESSOR SPSS028B – MAY 2000 – REVISED FEBRUARY 2001 functional description The MSP50C604 is a member of the MSP50C6xx family, which is based on the MSP50C614 core. For specific details about the core operations, instruction sets, register definitions, port configuration, etc., consult the MSP50C614 user’s guide (SPSU014). The MSP50C604 can be used as a slave synthesizer in slave mode or can operate stand-alone in master mode. The slave mode activates logic circuitry internal to the device that gives the device a dedicated slave interface. The slave or master mode is controlled by the bit 0 of the Port G (PG0). By default the device initially starts in slave mode. To change to master mode write a 0x01 to G port 0 (0x2C). To change back to slave mode write a 0x00 to port G bit 0 (0x2C). master mode In master mode, the slave logic circuitry is disabled and MSP50C604 has 16 general-purpose I/Os. These 16 input/output pins are organized as 2-byte-wide ports (C and D), initialized as inputs. Each of the pins can be configured as a totem-pole output or as a high-impedance input by setting or clearing the appropriate bit in the appropriate control register (0x14, 0x1C). When configured as an output, the data driven by the output pin can be controlled by setting or clearing the appropriate bit in the appropriate data register (0x10, 0x18). Whether configured as input or as output, reading the data port reads the actual state of the pin. External interrupts can be caused by transitions on pins PD2, PD3, PD4, and PD5 in the master mode. These interrupts are supported whether the pins are programmed as inputs or outputs. slave mode In slave mode, the slave logic circuitry is enabled allowing the device to have a dedicated slave interface. In this mode, only four pins of port D (PD4–PD7) are available as general-purpose I/O while the remaining pins (PD0–PD3) are redefined as INRDY, OUTRDY, STROBE and R/W. These pins are used to operate the slave interface. The MSP50C604 controls the INRDY and OUTRDY pins to let the external microcontroller know when the slave is ready to accept or transmit data. The external microcontroller controls the R/W and STROBE pins of MSP50C604 to sequence the read/write data flow. Each read or write sequence generates an interrupt that needs to be serviced by an interrupt service routine. These interrupt service routines need to be written by the code developer. The INT3 interrupt service routine indicates that the host has completed the write sequence, and the slave should read the data from port A. The INT4 interrupt service routine indicates the host has completed the read sequence. An interrupt is not generated when a read/write is done on port G bit 0 (PG0). The slave interface consists of: D D D D 8-bit bidirectional data bus (PC0 – PC7) 2 status outputs: INRDY/PD0, and OUTRDY/PD1 2 control inputs: STROBE/PD2, and R/W/PD3 4 general-purpose I/Os (PD4–PD7) Port C is used as an 8-bit bidirectional data bus. When data is to be sent to the host, it needs to be written to port C data register (0x10). When data is read from the host, it needs to be read from port A data register (0x00). Port A pins are not physically brought outside the device but are internally connected with the pins of port C. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 MSP50C604 MIXED-SIGNAL PROCESSOR SPSS028B – MAY 2000 – REVISED FEBRUARY 2001 pin assignments NC V SS2 V SS NC NC NC NC NC NC NC NC NC NC NC NC NC PM PACKAGE (TOP VIEW) VDD VDD3 1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 2 47 R/W 3 46 STROBE 4 45 OUTRDY 5 44 INRDY 6 43 TEST SCANOUT SYNC SCANCLK SCANIN RESET PLL OSCIN OSCOUT VSS 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 NC – No internal connection 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PC7 NC NC NC NC NC NC NC NC NC NC NC NC NC NC V DD 33 16 1718 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VSS1 DACP VDD2 DACM VDD1 PD4 PD5 PD6 PD7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 MSP50C604 MIXED-SIGNAL PROCESSOR SPSS028B – MAY 2000 – REVISED FEBRUARY 2001 Terminal Functions NAME PIN NO. PAD NO. I/O DESCRIPTION Input/Output Ports PC0 – PC7 39 → 32 25 → 18 I/O Port C general-purpose I/O (1 Byte) PD4– PD7 43 → 40 29 → 26 I/O Port D general-purpose I/O (1 Nibble) I/O (Master) Port D general-purpose I/O O (Slave) INRDY output to host I/O (Master) Port D general-purpose I/O O (Slave) OUTRDY output to host I/O (Master) Port D general-purpose I/O PD0/INRDY 6 6 PD1/OUTRDY 5 5 PD2/STROBE 4 4 PD3/R/W 3 3 I I/O I (Slave) STROBE input from host (Master) Port D general-purpose I/O (Slave) Read/write input from host Pins PD4 and PD5 may be dedicated to the comparator function, if the comparator enable bit is set. Please refer to Section 3.3, Comparator, in the MSP50C614 User’s Guide (SPSU014) for details. Scan Port Control Signals SCANIN 11 11 I Scan port data input SCANOUT 8 8 O Scan port data output SCANCLK 10 10 I Scan port clock SYNC 9 9 I Scan port synchronization TEST 7 7 I ’C604 test modes The Scan Port pins must be bonded out on any MSP50C604 production board. Please consult the Important Note regarding Scan Port Bond Out, see Chapter 7 in the MSP50C614 User’s Guide (SPSU014). Reference Oscillator Signals OSCOUT 15 15 O Resistor/crystal reference out OSCIN 14 14 I Resistor/crystal reference in PLL 13 13 O Phase-lock-loop filter DACP 47 33 O Digital-to-analog plus output (+) DACM 45 31 O Digital-to-analog minus output(–) Digital-to-Analog Sound Output Initialization RESET 12 12 I Initialization Power Signals† VSS 16, 48, 49†, 64 16, 34†, 35, 36 Ground VDD 1, 2, 31, 44, 46† 1, 2, 17, 30, 32† Processor power (+) † VSS and VDD connections service the DAC circuitry. Their pins tend to sustain a higher current draw. A dedicated decoupling capacitor across these pins is therefore required. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 MSP50C604 MIXED-SIGNAL PROCESSOR SPSS028B – MAY 2000 – REVISED FEBRUARY 2001 system initialization sequence in the slave mode D D Initialize the host processor first. The host must hold the slave RESET pin low until the slave STROBE pin can be held high by the host throughout the slave initialization process. The INRDY and OUTRDY pins are set high by the slave on the rising edge of the slave RESET pin. slave mode software initialization D D D D Write 0x00 to port A (0x00), port C (0x10), port D (0x18) data registers. Configure the port C (PC0–PC7), port D0, and port D1 as output ports. (Write 0xFF to port C (0x14) and 0x03 to port D (0x1C) control registers) Configure port A (PA0–PA7), PORT D2, and port D3 as input ports (default at reset). Write 0x00 to port A (0x04) and 0x03 to port D (0x1C) control registers. After the slave completes its initialization, the slave needs to inform the host that it is ready to read or write data. NOTE: The default mode for the MSP50C604 is the slave mode. The MSP50C604 can be set to master mode by writing a 1 to port G bit 0. This is an internal bit that is not available on the MSP50C604 external pins. NOTE: The initialization sequence given previously is a specific requirement for setting up the MSP50C604 in slave mode. For the basic initialization requirements of the device, please refer to the MSP50C614 user’s guide (SPSU014). write to slave in the slave mode D D D D D D The slave indicates it is ready to receive data from the host by dropping INRDY low. This is done by writing low-high-low to port D (0x18) bit 0 (PD0). On the falling edge of the internal PD0 pulse, INRDY toggles low, notifying the host that the slave is ready to receive data. The host writes data to the slave by setting R/W low and then pulsing the STROBE high-low-high. The slave latches the data on the rising edge of the STROBE pulse and sets INRDY high. An INT3 interrupt is generated as INRDY goes high completing the write cycle. The latched data is read by the slave through port A (0x00) data register. read from slave in the slave mode D D D D D D D 6 When the slave has data for the host, it places the data in port C (0x10). The slave then indicates that the data is ready by dropping OUTRDY low. This is done by writing low-high-low to port D (0x18) bit 1 (PD1). On the falling edge of the internal PD1 pulse, OUTRDY toggles low notifying the host that the slave is ready to send data. The host responds by setting R/W high and then pulsing STROBE high-low-high. The host should latch the data before raising STROBE high. This informs the slave that the data has been written to the host. The OUTRDY is pulled high by the slave at the rising edge of STROBE. An INT4 interrupt is generated as OUTRDY goes high completing the read cycle. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP50C604 MIXED-SIGNAL PROCESSOR SPSS028B – MAY 2000 – REVISED FEBRUARY 2001 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V Supply current, IDD (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 mA Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VDD + 0.3 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VDD + 0.3 V Storage temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 30°C to 125°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Unless otherwise noted, all voltages are measured with respect to VSS . 2. The total supply current includes the current out of all the I/O pins as well as the operating current of the device. recommended operating conditions MIN MAX Supply voltage (with respect to VSS), VDD 3.0 5.2 CPU clock rate (as programmed), f(CPU) 64 12,320 Load Resistance between DACP and DACM, R(DAC) 32 Operating free-air temperature, TA Device functionality 0 UNIT V kHz Ω °C 70 timing requirements MIN t(RESET) t1(WIDTH) Reset pulsed low, while ’C604 has power applied Pulse width required prior to a negative transition at pin (PD3, PD5, or PF0...PF7 interrupt) 2 t2(WIDTH) Pulse width required prior to a positive transition at pin (PD2 or PD4 interrupt) 2 MAX UNIT 100 ns 1/FCPU 1/FCPU RESET tRESET Figure 1. Initialization Timing Diagram t1WIDTH (PD3, PD5, or F port) t1WIDTH t2WIDTH (PD2, or PD4) t2WIDTH Figure 2. MSP50C604 External Interrupt Pin Pulse Width Requirements t1WIDTH and t2WIDTH POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 MSP50C604 MIXED-SIGNAL PROCESSOR SPSS028B – MAY 2000 – REVISED FEBRUARY 2001 dc electrical characteristics, TA = 0°C – 70°C PARAMETER TEST CONDITIONS VDD = 3 V RESET Threshold changes VDD = 5.2 V VIH VIL High level input High-level voltage Low-level Low level input voltage MIN TYP† Positive going threshold 2.4 Negative going threshold 1.8 Hysteresis 0.6 Positive going threshold 3.3 Negative going threshold 2.9 Hysteresis 0.4 MAX V V VDD = 3 V VDD = 4.5 V 2 3 3 4.5 VDD = 5.2 V VDD = 3 V 3.5 5.2 0 1 VDD = 4.5 V VDD = 5.2 V 0 1.5 0 1.7 IOH¶ High-level output current per pin of I/O port IOL¶ Low-level output current per pin of I/O port IOH (DAC) High-level output DAC current IOL (DAC) Low-level output DAC current Ilkg Input leakage current Excludes OSCIN Standby current RESET is low Operating current VDD = 4.5 V, VDD = 4.5 V, FCLOCK = 12.32 MHz DAC off, ARM set, OSC disabled 0.05 VDD = 4.5 V, VDD = 4.5 V, DAC off, ARM set, OSC enabled 40 60 DAC off, ARM clear, OSC enabled 60 100 Vref = 1 to 4.25 V 25 50 I(STANDBY) IDD‡ I(SLEEP-deep) I(SLEEP-mid) Supply current I(SLEEP-light) VDD = 4.5 V VOH = 4 V VOL = 0.5 V VDD = 4.5 V VOH = 4 V VOL = 0.5 V VIO Input offset voltage VDD = 4.5 V, R(PULLUP) F port pullup resistance VDD = 5 V ∆f(RTO ti ) (RTO-trim) Trim deviation ∆f(RTO lt) (RTO-volt) Voltage deviation ∆f(RTO t ) (RTO-temp) Temperature deviation ∆f(RTO (RTO-res)) Resistance deviation 0.05 RRTO = 470 kΩ, VDD = 4.5 V, TA = 25°C, fRTO = 8.192 MHz (PLL setting = 7 Ch)§ RRTO = 470 kΩ, VDD = 3.5 to 5.2 V, fRTO = 8.192 MHz (PLL setting = 7 Ch)§ RRTO = 470 kΩ, TA = 25°C, VDD = 4.5 V, TA = 0 to 70°C, fRTO = 8.192 MHz (PLL setting = 7 Ch)§ VDD = 4.5 V, TA = 25°C, ROSC = 470 kΩ at ± 1%, fRTO = 8.192 MHz (PLL setting = 7 Ch)§ V mA 5 mA –10 mA 20 mA 1 µA 10 µA mA 10 150 ± 1% V –2 15 70 UNIT µA mV kΩ ± 3% ± 1.5 15 %/V 0 03 ± 0.03 %/°C ±1 %/R † Typical voltage and current measurements taken at 25°C ‡ Operating current assumes all inputs are tied to either VSS or VDD with no input currents due to programmed pullup resistors. The DAC output and other outputs are open circuited. § The best trim value is selected at nominal temperature and voltage but the deviation due to the trim error is ignored. ¶ This parameter cannot exceed 15 mA total per internal VDD pin. Port C and port D share 1 internal VDD. Ports A and G0 are used internally. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MSP50C604 MIXED-SIGNAL PROCESSOR SPSS028B – MAY 2000 – REVISED FEBRUARY 2001 external component absolute values PARAMETER R(RTO) RTO external resistance C(PLL) PLL external capacitance TEST CONDITIONS TA = 25°C, TA = 25°C, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MAX UNIT 1% tolerance MIN 470 kΩ 10% tolerance 3300 pF 9 MSP50C604 MIXED-SIGNAL PROCESSOR SPSS028B – MAY 2000 – REVISED FEBRUARY 2001 timing diagram D0 1 D1 1 2 INRDY 7 tIS tSI 2 OUTRDY R/W ÇÇÇÇ ÇÇÇÇ 7 ÉÉÉÉÉÉ ÉÉÉÉÉÉ ÇÇÇ ÇÇÇ tOS 3 3 tSR tRS tSR tRS 6 4 STROBE tSO 6 4 tST tST 8 INT3 8 INT4 tS tDV ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ tH Data tDZ New Data Valid Data 5 5 Write to Slave Read from Slave 1. Slave signals readiness to receive data from host. 2. Slave drops INRDY. 3. Host drops R/W to indicate a write. 4. Host drops STROBE. 5. Host places data on the bus. 6. Host raises STROBE indicating data is valid. 7. Slave raises INRDY, latching the data. 8. INT3 is triggered when INRDY rises. 1. Slave signals readiness to send data to host. 2. Slave drops OUTRDY. 3. Host raises R/W to indicate a read. 4. Host drops STROBE. 5. Slave places data on the bus. 6. Host raises STROBE after reading the data. 7. Slave raises OUTRDY. 8. INT4 is triggered when OUTRDY rises. Table 1. Timing Constrains Write to Slave INRDY low to STROBE low tIS (min) = 5 ns tRS (min) = 75 ns OUTRDY low to STROBE low tST (min) = 100 ns tSR (min) = 25 ns STROBE low STROBE high to OUTRDY high Data setup tSI (max) = 75 ns tS (min) = 15 ns STROBE Low to data valid tSO (max) = 75 ns tDV (max) = 90 ns Data hold tH (min) = 80 ns STROBE High to data high Z tDZ (min) = 90 ns R/W to STROBE low STROBE low STROBE high to R/W STROBE high to INRDY high 10 Read from Slave POST OFFICE BOX 655303 R/W to STROBE low STROBE high to R/W • DALLAS, TEXAS 75265 tOS (min) = 5 ns tRS (min) = 75 ns tST (min) = 100 ns tSR (min) = 25 ns MSP50C604 MIXED-SIGNAL PROCESSOR SPSS028B – MAY 2000 – REVISED FEBRUARY 2001 MECHANICAL DATA PM (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 0,08 M 33 48 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 SQ 11,80 0,25 0,05 MIN 0°– 7° 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040152 / C 11/96 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Falls within JEDEC MS-026 May also be thermally enhanced plastic with leads connected to the die pads. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this information with alteration voids all warranties provided for an associated TI product or service, is an unfair and deceptive business practice, and TI is not responsible nor liable for any such use. Resale of TI’s products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service, is an unfair and deceptive business practice, and TI is not responsible nor liable for any such use. Also see: Standard Terms and Conditions of Sale for Semiconductor Products. www.ti.com/sc/docs/stdterms.htm Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2001, Texas Instruments Incorporated