PD - 97597A
AUTOMOTIVE GRADE
AUIRFR4105
HEXFET® Power MOSFET
Features
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D
Advanced Planar Technology
Low On-Resistance
Dynamic dV/dT Rating
175°C Operating Temperature
Fast Switching
Fully Avalanche Rated
Repetitive Avalanche Allowed
up toTjmax
Lead-Free, RoHS Compliant
Automotive Qualified *
V(BR)DSS
55V
RDS(on) max.
G
S
ID (Silicon Limited)
45mΩ
27A
ID (Package Limited)
20A
g
D
S
Description
G
Specifically designed for Automotive applications,
this cellular design of HEXFET® Power MOSFETs
utilizes the latest processing techniques to achieve
low on-resistance per silicon area. This benefit
combined with the fast switching speed and
ruggedized device design that HEXFET power
MOSFETs are well known for, provides the designer
with an extremely efficient and reliable device for use
in Automotive and a wide variety of other applications.
D-Pak
AUIRFR4105
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These
are stress ratings only; and functional operation of the device at these or any other condition beyond those indicated in
the specifications is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions.
Ambient temperature (TA) is 25°C, unless otherwise specified.
Max.
Parameter
ID @ TC = 25°C
ID @ TC = 100°C
ID @ TC = 25°C
IDM
PD @TC = 25°C
VGS
EAS
IAR
EAR
dv/dt
TJ
TSTG
27
19
20
100
68
0.45
± 20
65
16
6.8
5.0
-55 to + 175
c
c
Units
g
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V (Package Limited)
Pulsed Drain Current
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy (Thermally Limited)
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds (1.6mm from case )
d
c
e
A
W
W/°C
V
mJ
A
mJ
V/ns
°C
300
Thermal Resistance
RθJC
RθJA
RθJA
h
Parameter
Junction-to-Case
Junction-to-Ambient (PCB mount) **
Junction-to-Ambient
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Typ.
Max.
Units
–––
–––
–––
2.2
50
110
°C/W
1
07/05/11
AUIRFR4105
Static Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter
V(BR)DSS
ΔV(BR)DSS/ΔTJ
RDS(on)
VGS(th)
gfs
IDSS
IGSS
Min. Typ. Max. Units
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Forward Transconductance
Drain-to-Source Leakage Current
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
55
–––
–––
2.0
6.5
–––
–––
–––
–––
–––
0.052
–––
–––
–––
–––
–––
–––
–––
–––
–––
45
4.0
–––
25
250
100
-100
Conditions
V VGS = 0V, ID = 250μA
V/°C Reference to 25°C, ID = 1mA
mΩ VGS = 10V, ID = 16A
V VDS = VGS, ID = 250μA
S VDS = 25V, ID = 16A
μA VDS = 55V, VGS = 0V
VDS = 44V, VGS = 0V, TJ = 150°C
nA VGS = 20V
VGS = -20V
f
Dynamic Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
Conditions
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
LD
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Internal Drain Inductance
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
7.0
49
31
40
4.5
34
6.8
14
–––
–––
–––
–––
–––
LS
Internal Source Inductance
–––
7.5
–––
6mm (0.25in.)
from package
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
–––
–––
–––
700
240
100
–––
–––
–––
and center of die contact
VGS = 0V
VDS = 25V
ƒ = 1.0MHz, See Fig. 5
nC
ns
nH
pF
ID = 16A
VDS = 44V
VGS = 10V, See Fig. 6 & 13
VDD = 28V
ID = 16A
RG = 18Ω
RD = 1.8Ω, See Fig. 10
Between lead,
f
f
D
G
S
Diode Characteristics
Parameter
Min. Typ. Max. Units
IS
Continuous Source Current
–––
–––
27g
ISM
(Body Diode)
Pulsed Source Current
–––
–––
100
VSD
trr
Qrr
ton
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Forward Turn-On Time
–––
–––
–––
–––
57
130
1.6
86
200
c
Conditions
MOSFET symbol
A
V
ns
nC
showing the
integral reverse
p-n junction diode.
TJ = 25°C, IS = 16A, VGS = 0V
TJ = 25°C, IF = 16A
di/dt = 100A/μs
f
f
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
VDD = 25V, starting TJ = 25°C, L = 410μH
RG = 25Ω, IAS = 16A. (See Figure 12)
ISD ≤ 16A, di/dt ≤ 420A/μs, VDD ≤ V(BR)DSS,
Pulse width ≤ 300μs; duty cycle ≤ 2%.
Calculated continuous current based on maximum allowable
junction temperature; Package limitation current = 20A.
Rθ is measured at Tj approximately 90°C.
TJ ≤ 175°C.
2
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AUIRFR4105
Qualification Information†
Automotive
(per AEC-Q101)
Qualification Level
Moisture Sensitivity Level
ESD
††
Comments: This part number(s) passed Automotive qualification. IR’s
Industrial and Consumer qualification level is granted by extension of the
higher Automotive level.
D-PAK
MSL1
†††
Machine Model
Class M2 (+/- 200V)
AEC-Q101-002
Human Body Model
Class H1B (+/- 900V)
AEC-Q101-001
Charged Device
Model
Class C5 (+/- 1125V)
AEC-Q101-005
RoHS Compliant
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†††
†††
Yes
3
AUIRFR4105
1000
1000
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
I , Drain-to-Source Current (A)
D
I , Drain-to-Source Current (A)
D
100
10
4.5V
1
20μs PULSE WIDTH
TC = 25°C
0.1
0.1
1
10
A
100
10
100
TJ = 175°C
10
V DS = 25V
20μs PULSE WIDTH
8
9
VGS , Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
4
R DS(on) , Drain-to-Source On Resistance
(Normalized)
I D , Drain-to-Source Current (A)
TJ = 25°C
7
10
100
A
Fig 2. Typical Output Characteristics
2.4
6
1
VDS , Drain-to-Source Voltage (V)
100
5
20μs PULSE WIDTH
TC = 175°C
0.1
0.1
Fig 1. Typical Output Characteristics
1
4.5V
1
VDS , Drain-to-Source Voltage (V)
4
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
TOP
TOP
10
A
I D = 26A
2.0
1.6
1.2
0.8
0.4
VGS = 10V
0.0
-60 -40 -20
0
20
40
60
A
80 100 120 140 160 180
TJ , Junction Temperature (°C)
Fig 4. Normalized On-Resistance
Vs. Temperature
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AUIRFR4105
1200
V GS , Gate-to-Source Voltage (V)
1000
C, Capacitance (pF)
20
V GS = 0V,
f = 1MHz
C iss = Cgs + C gd , Cds SHORTED
C rss = C gd
Ciss C oss = Cds + C gd
800
Coss
600
400
Crss
200
0
1
10
100
A
I D = 16A
V DS = 44V
V DS = 28V
16
12
8
4
FOR TEST CIRCUIT
SEE FIGURE 13
0
0
VDS , Drain-to-Source Voltage (V)
20
30
40
A
Q G , Total Gate Charge (nC)
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
1000
1000
OPERATION IN THIS AREA LIMITED
BY R DS(on)
I D , Drain Current (A)
ISD , Reverse Drain Current (A)
10
100
TJ = 175°C
TJ = 25°C
10
100
10μs
100μs
10
1ms
VGS = 0V
1
0.4
0.8
1.2
1.6
VSD , Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
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A
2.0
TC = 25°C
TJ = 175°C
Single Pulse
1
1
10
A
100
VDS , Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
5
AUIRFR4105
RD
V DS
30
VGS
LIMITED BY PACKAGE
25
D.U.T.
RG
+
ID , Drain Current (A)
-VDD
20
5.0V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
15
10
Fig 10a. Switching Time Test Circuit
5
VDS
0
25
50
75
100
125
150
90%
175
TC , Case Temperature ( °C)
10%
VGS
td(on)
Fig 9. Maximum Drain Current Vs.
Case Temperature
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
Thermal Response (Z thJC )
10
1
D = 0.50
0.20
0.10
0.05
0.1
0.01
0.00001
0.02
0.01
PDM
SINGLE PULSE
(THERMAL RESPONSE)
t1
t2
Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJC + TC
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
6
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15V
L
VDS
D.U.T
RG
IAS
10V
tp
DRIVER
+
V
- DD
A
0.01Ω
Fig 12a. Unclamped Inductive Test Circuit
E AS , Single Pulse Avalanche Energy (mJ)
AUIRFR4105
140
TOP
120
BOTTOM
ID
6.5A
11A
16A
100
80
60
40
20
0
VDD = 25V
25
50
75
100
125
150
A
175
Starting TJ , Junction Temperature (°C)
V(BR)DSS
tp
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
I AS
Fig 12b. Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.T.
50KΩ
5.0 V
QG
QGS
.2μF
.3μF
D.U.T.
QGD
+
V
- DS
VGS
VG
3mA
Charge
Fig 13a. Basic Gate Charge Waveform
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12V
IG
ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
7
AUIRFR4105
Peak Diode Recovery dv/dt Test Circuit
D.U.T
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
+
-
-
+
+
•
•
•
•
RG
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
Driver Gate Drive
Period
P.W.
D=
VDD
P.W.
Period
*
VGS=10V
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 14. For N-Channel HEXFETS
8
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AUIRFR4105
D-Pak Part Marking Information
Part Number
AUFR4105
YWWA
IR Logo
XX
or
Date Code
Y= Year
WW= Work Week
A= Automotive
XX
Lot Code
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9
AUIRFR4105
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR
TRR
16.3 ( .641 )
15.7 ( .619 )
12.1 ( .476 )
11.9 ( .469 )
FEED DIRECTION
TRL
16.3 ( .641 )
15.7 ( .619 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
13 INCH
16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
10
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