EV1380 8A Synchronous Highly Integrated DC-DC DDR2/3/QDRTM Memory Termination Power SoC Description Features The EV1380 is a Power System on a Chip (PowerSoC) DC to DC converter in a 68 pin QFN that is optimized for DDR2, DDR3, and QDRTM VTT applications. It requires a power supply (AVIN) for the controller and operates from an input supply (VDDQ). It provides a tightly regulated and very stable output voltage (VTT) which tracks VDDQ while sinking and sourcing up to 8A of output current. Enpirion’s integrated inductor technology significantly helps to reduce noise, and offers a high efficiency solution for VTT applications with a very low external component count. • • • Advanced circuit techniques, optimized switching frequency, and very advanced, high-density, integrated circuit and proprietary inductor technology deliver high-quality, ultra compact, non-isolated DC-DC conversion. Application The complete power converter solution enhances productivity by offering greatly simplified board design, layout and manufacturing requirements. High efficiency, up to 94%. Output voltage tracks VDDQ +/- 1% Nominal 1.5MHz operating frequency with ability to synchronize to an external clock source or serve as the primary source. Programmable soft-start time. Soft Shutdown. Master/slave configuration for parallel operation. Thermal shutdown, over current, short circuit, and under-voltage protection. RoHS compliant, MSL level 3, 260C reflow. • • • • • Bus Termination: DDR2, DDR3, & QDR™ memory SCHOTTKY VDDQ RFS 0402 CA 0402 RA 0402 VTT SW VDDQ CIN R1 0402 VCNTRL EV1380 RC ENABLE RB 0402 AVIN VFB PGND PGND VREF RD VOUT CSS CAVIN AGND FQADJ R1 RA RPD COUT CA RB RFS EV1380QI Output Cap 100uF/ 1206 Input Cap 47uF/ 0805 Output Cap 100uF/ 1206 Input Cap 47uF/ 0805 Figure 2: Typical Application Schematic (VDDQ is the memory core voltage; VTT is memory termination voltage that tracks VDDQ) Output Cap 100uF/ 1206 Figure 1: EV1380 Total Solution Size ~200mm2 (not to scale). Does not show back-side components. www.enpirion.com EV1380 Datasheet Rev A S_OUT M/S 49 PGND 34 ENABLE 50 PGND 33 AVIN1 51 32 PGND AGND1 52 31 PGND POK 53 30 VFB PGND 54 29 VREF VSENSE EAOUT PGND 55 28 PGND 56 27 SW 57 26 EN_PB SW 58 25 NC FQADJ 59 24 VOUT VDDQOK 60 23 VOUT NC(SW) 61 22 VOUT NC(SW) 62 21 VOUT NC 63 20 VOUT NC 64 19 VOUT NC 65 18 VOUT NC 66 17 VOUT NC 67 15 16 NC Temp Rating (°C) Package -40 to +85 68-pin QFN T&R QFN Evaluation Board Part Number EV1380QI EV1380QI-E 68 Pin Assignments (Top View) VOUT Ordering Information Figure 3: Pin Out Diagram (Top View) NOTE: NC pins are not to be electrically connected to each other or to any external signal, ground, or voltage. However, they must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage. Pin Description PIN 1-15, 25, 46-47, 64-68 16-24 NAME NC VOUT 26-27 SW 28-34 PGND 35-43 VDDQ 44 45, 52 AGND2 AVIN2, AVIN1 S_IN 48 FUNCTION NO CONNECT: These pins must be soldered to PCB but not be electrically connected to each other or to any external signal, voltage, or ground. These pins may be connected internally. Failure to follow this guideline may result in device damage. Regulated converter output. Connect to the load, and place output filter capacitor(s) between these pins and PGND pins 28-31. These pins are internally connected to the common switching node of the internal MOSFETs. The anode of a schottky diode needs to be connected to these pins. The cathode of the diode needs to be connected to VDDQ. Input/Output power ground. Connect these pins to the ground electrode of the input and output filter capacitors. See VOUT and PVIN descriptions for more details. In DDR applications the input to this pin is the DDR core voltage. This is the input power supply to the power train which will be divided by two to create an output voltage that tracks with the input voltage applied to this pin. Place input filter capacitor(s) between these pins and PGND pins 32-34. Ground for the gate driver supply. Connect to the ground plane with a via. Analog input voltage for the controller circuits. Each of these pins needs to be separately connected to the 3.3V input supply. Decouple with a capacitor to AGND1. Digital Input. Depending on the M/S pin, this pin accepts either an input clock to phase lock the internal switching frequency or a S_OUT signal from another Enpirion device. Leave this pin floating if it is not used. ©Enpirion 2010 all rights reserved, E&OE 2 www.enpirion.com EV1380 Datasheet Rev A 49 NAME S_OUT 50 M/S 51 53 54 ENABLE AGND POK 55 VFB 56 57 EAOUT VREF 58 59 VSENSE EN_PB 60 61 FQADJ Tie this pin to AGND through a 13kΩ resistor. VDDQOK This is an active high input pin that indicates the externally supplied VDDQ has reached its POK level. This pin should be tied to the VDDQ regulator POK output, or let float if unused. NC(SW) NO CONNECT: These pins are internally connected to the common switching node of the internal MOSFETs. They must be soldered to PCB but not be electrically connected to any external signal, ground, or voltage. Failure to follow this guideline may result in device damage. PGND Device thermal pad to be connected to the system GND plane for heatsinking purposes. See Layout Recommendations section. PIN 62-63 69 FUNCTION Digital Output. Depending on the M/S pin, either a clock signal synchronous with the internal switching frequency or the PWM signal is output on this pin. Leave this pin floating if it is not used. This is a Ternary Input put. Floating the pin disables parallel operation. A low level configures the device as Master and a High level configures the device as a slave. This is the Device Enable pin. Tie this pin to VDDQ with a 10kΩ resistor. This is the quiet ground for the control circuits. Connect to the ground plane with a via. POK is a logical AND of VDDQOK and the internally generated POK of the EV1380. POK is an open drain logic output that requires an external pull-up resistor. POK is logic high when VOUT is within -10% to +10% of VOUT nominal. This pin guarantees a logic low even when the EV1380 is completely un-powered. This pin can sink a maximum 4mA. The pull-up resistor may be connected to a power supply other than AVIN or VDDQ but the voltage should be <3.6Volts. This is the External Feedback input pin. A resistor divider connects from the output to AGND. The mid-point of the resistor divider is connected to VFB. (A feed-forward capacitor is required across the upper resistor.) The output voltage regulates so as to make the VFB node voltage = VREF. Optional Error Amplifier output. Allows for customization of the control loop. External voltage reference input. A resistor divider connects from VDDQ to AGND. The mid-point of the resistor divider is connected to VREF. The resistor divider has to be chosen to make the voltage applied to this pin ~0.4*VDDQ. An optional capacitor (for soft start) may be connected from VREF to AGND. Connect this pin to VOUT. This is the Enable Pre-Bias Input. When this pin is pulled high, the Device will support start-up under a pre-biased load. This pin is pulled high internally. ©Enpirion 2010 all rights reserved, E&OE 3 www.enpirion.com EV1380 Datasheet Rev A Absolute Maximum Ratings PARAMETER SYMBOL MIN MAX UNITS VIN -0.5 4.0 V Voltages on: EN, EN_PB, VDDQOK -0.5 VIN V Voltages on: VFB, VREF, EAOUT, M_S, S_IN, S_OUT, VDDQ, VOUT, VSENSE, FQADJ -0.5 2.7 V 3.6 V -0.5 VDDQ+0.5 V -65 150 °C 150 °C Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020A 260 °C ESD Rating (based on Human Body Model) – VREF pin 1500 V ESD Rating (based on Human Body Model) – All other pins 2000 V ESD Rating (based on CDM) 500 V MIN MAX UNITS Input Voltage Range: AVIN1, AVIN2 3.07 3.53 V Input Voltage Range: VDDQ 1.16 1.65* V 0.5 0.5 V 0 AVIN V Input Supply Voltage: AVIN1, AVIN2 Voltage on: POK Voltage on: SW Storage Temperature Range TSTG Maximum Operating Junction Temperature TJ-ABS Max Recommended Operating Conditions PARAMETER SYMBOL Input Voltage Range: VREF VEXTREF EN_PB, VDDQOK, M/S, S_IN, EN Operating Ambient Temperature TA - 40 +85 °C Operating Junction Temperature TJ - 40 +125 °C *: For DDR2 applications with VDDQ=1.8V, contact Enpirion applications support. Thermal Characteristics PARAMETER SYMBOL TYP UNITS Thermal Resistance: Junction to Ambient (0 LFM) (Note 1) θJA 16 °C/W Thermal Resistance: Junction to Case (0 LFM) θJC 1.5 °C/W Thermal Shutdown TSD 150 °C Thermal Shutdown Hysteresis TSDH 20 °C Note 1: Based on a 2oz. copper board and proper thermal design in line with JEDEC EIJ/JESD 51 Standards. ©Enpirion 2010 all rights reserved, E&OE 4 www.enpirion.com EV1380 Datasheet Rev A Electrical Characteristics NOTE: AVIN1, AVIN2 = 3.3V, over operating temperature range unless otherwise noted. Typical values are at TA = 25°C. PARAMETER SYMBOL TEST CONDITIONS MIN Input Power Supply Voltage VDDQ 1.16 Controller Supply Voltage AVIN 3.07 Output Voltage Accuracy – Initial ΔVOUT VOUT =1/2 VDDQ (e.g. @ VDDQ = 1.500V), 0.1% input and output resistor dividers) VFB Pin Voltage VVFB 3.07V ≤ AVIN ≤ 3.53V, VDDQ = 1.5V, 0A ≤ ILOAD ≤ 8A VFB Pin Input Leakage Current IVFB VFB pin input leakage current 3.3 0.740 591 600 -5 MAX UNITS 1.65 V 3.53 V 0.760 V 609 mV 5 nA Power Supply current with Enable=0 450 μA VUVLOR Voltage above which UVLO is not asserted 2.2 V VUVLOF Voltage below which UVLO is asserted 2.05 V VDDQ = 1.5V, VOUT = 0.75V, IOUT = 8A, COUT = 3x100 µF (1206) <10 mV Shut-Down Supply Current IS Under Voltage Lock-out – AVIN Rising Under Voltage Lock-out – AVIN Falling Peak-to-Peak Ripple TYP RPP Maximum Continuous Output Sourcing Current IOUT_Max_SRC Maximum load current. See Note 1. 8 A Maximum Continuous Output Sinking Current IOUT_Max_SNK Maximum load current. See Note 1. 8 A Over Current Trip Level IOCPH Sourcing. VDDQ = 1.5V 18 A Switching Frequency FSW RFQADJ = 13kOhms 1.5 MHz External SYNC Clock Frequency Lock Range FPLL_LOCK SYNC clock input frequency range RFQADJ = 13kOhms S_IN Clock Amplitude – Low VS_IN_LO SYNC Clock Logic Level S_IN Clock Amplitude – High VS_IN_HI SYNC Clock Logic Level S_IN Clock Duty Cycle (PLL) DCS_INPLL M_S Pin Float or Low S_IN Clock Duty Cycle (PWM) DCS_INPWM M_S Pin High Pre-Bias Level VPB 1.25 1.75 MHz 0.4 V 1.8 2.5 V 20 80 % 50 Allowable pre-bias as a fraction of programmed output voltage. VOUT Range for POK = High VDDQ rising Range of output voltage as a fraction of programmed value when POK is asserted VOUT Range for POK = High VDDQ falling Range of output voltage as a fraction of programmed value when POK is asserted 0 40 % 92±3 110±3 % 90±3 % Clock cycles POK Deglitch Delay Falling edge deglitch delay after output crossing 90% level 64 VPOK Logic Low level With 4mA current sink into POK pin 0.7 ©Enpirion 2010 all rights reserved, E&OE 5 % 1 V www.enpirion.com EV1380 Datasheet Rev A PARAMETER SYMBOL TEST CONDITIONS MIN VPOK Logic high level POK Current Sink Capability VTT Tracking VDDQ Enable Pin Current 3.07V ≤ AVIN ≤ 3.53V VDDQ – 2*VTT IEN VDDQ > 1V, VDDQ Rate of change at 1V/ms VB-LOW ENABLE, S_IN, VDDQOK Logic High Threshold VB-HIGH ENABLE, S_IN, VDDQOK S_OUT Low Level VS_OUT_LOW S_OUT High Level VS_OUT_HIGH M/S Pin Logic Low Threshold VT-LOW Threshold voltage for Logic Low M/S Pin Logic High Threshold VT-HIGH Threshold voltage for Logic High (internally pulled high; can be left floating to achieve logic high) MAX UNITS AVIN V 4 mA -25 +25 0.4 1.8 2.0 M/S Pin Input Current IITERN Current Balance ΔIOUT With 2 converters in parallel, the difference between any two parts. AVIN<50mV, RTRACE< 2 mΩ V V 0.4 The ternary pin has 100kΩ to AGND and another 100kΩ to an internal 2.5V supply. If connecting to AVIN recommend using a series resistor. See Figure 7. mV μA 50 Tied to VDDQ through a 10kΩ Logic Low Threshold TYP V V 2.0 0.4 V 2.7 V See Figure 7. μA +/-10 % Note 1: Maximum output current may need to be de-rated, based on operating condition, to meet TJ requirements. ©Enpirion 2010 all rights reserved, E&OE 6 www.enpirion.com EV1380 Datasheet Rev A Typical Performance Characteristics 95 90 Efficiency (%) 85 80 75 70 65 60 55 50 0.1 0.3 0.5 0.7 0.9 1.5 2.5 3.5 4.5 5.5 6.5 7.5 Load Current Efficiency AVIN = 3.3V, VDDQ = 1.5V VOUT = VDDQ * 0.5 20MHz BW Limit 500 MHz BW Output Ripple: AVIN = 3.3V, VDDQ = 1.16V, VOUT = VDDQ*0.5, Iout = 8A, CIN = 2x47μF (0805), COUT = 2x47μF (1206) Output Ripple: AVIN = 3.3V, VDDQ = 1.16V, VOUT = VDDQ*0.5, Iout = 8A, CIN = 2x47μF (0805), COUT = 4x100μF (1206) 20MHz BW Limit 500 MHz BW Output Ripple: AVIN = 3.3V, VDDQ = 1.5V, VOUT = VDDQ*0.5, Iout = 8A, CIN = 2x47μF (0805), COUT = 4x100μF (1206) Output Ripple: AVIN = 3.3V, VDDQ = 1.5V, VOUT = VDDQ*0.5, Iout = 8A, CIN = 2x47μF (0805), COUT = 4x100μF (1206) ©Enpirion 2010 all rights reserved, E&OE 7 www.enpirion.com EV1380 Datasheet Rev A Load Transient Response: AVIN = 3.3V, VDDQ = 1.5V, VOUT = VDDQ*0.5, Ch.1: VOUT, Ch.2: ILOAD 0↔~4A, Ch.3: IVDDQ CIN = 2x47μF (0805), COUT = 4x100μF (1206) Load Transient Response: AVIN = 3.3V, VDDQ = 1.215V, VOUT = VDDQ*0.5, Ch.1: VOUT, Ch.2: ILOAD 0↔~4A, Ch.3: IVDDQ CIN = 2x47μF (0805), COUT = 4x100μF (1206) Power Up/Down at No Load: AVIN = 3.3V, VDDQ = 1.5V, VOUT = VDDQ*0.5, Ch.1: VOUT, Ch.2: VDDQOK, Ch.3: VDDQ, Ch. 4: POK CIN = 2x47μF (0805), COUT = 4x100μF (1206) Power Up/Down into a ~94mΩ Load: AVIN = 3.3V, VDDQ = 1.5V, VOUT = VDDQ*0.5, Ch.1: VOUT, Ch.2: VDDQOK, Ch.3: VDDQ, Ch. 4: POK CIN = 2x47μF (0805), COUT = 4x100μF (1206) ©Enpirion 2010 all rights reserved, E&OE 8 www.enpirion.com EV1380 Datasheet Rev A Functional Block Diagram S_OUT S_IN S_DELAY VDDQ EV1380QI To PLL Digital I/O M_S UVLO VDDB Thermal Limit Current Limit HS-Drive Over Voltage NC(SW) VOUT (-) PWM Comp (+) LS-Drive PGND AVIN Compensation Network PLL / Sawtooth Generator (-) FQADJ EAOUT VFB Error Amp (+) power Good Logic ENABLE Soft Start Pre-bias VREF AVIN VDDQOK VDDQ Bandgap Reference AGND POK AVIN EN_PB EAOUT VSENSE Figure 4: Functional Block Diagram Functional Description Synchronous Buck Converter The EV1380 is a synchronous, programmable Buck power supply with integrated power MOSFET switches and integrated inductor. The switching supply uses voltage mode control and a low noise PWM topology. ©Enpirion 2010 all rights reserved, E&OE Typically two power sources are required to operate this device. The first power source (AVIN) is for the controller with a nominal input voltage range of 3.07-3.53V. The second supply (VDDQ) is the supply that is tracked the recommended operating range is 1.16 to 1.65V. With the right choice of input and output 9 www.enpirion.com EV1380 Datasheet Rev A dividers, the output voltage of the EV1380 will produce an Output Voltage which tracks to ½ VDDQ. The EV1380 can continuously source or sink currents up to 8A. The 1.5MHz nominal switching frequency enables small-size input and output capacitors. Soft-Start and Soft-Shutdown The EV1380 is expected to operate with the controller power supply (AVIN) ON, VDDQ ramped up and down at a relatively slow rate (~1V/mS), and ENABLE tied to VDDQ through a 10kΩ resistor. It is also acceptable for VDDQ to be dynamically scaled within a small voltage range. If, however, VDDQ should ramp up at a high rate, a capacitor connected between VREF and AGND provides the soft-start function to limit in-rush current. The soft-start time constant is determined by the input voltage divider and the soft-start capacitor. See figure 5. Pre-Bias Start-up The EV1380 supports start up into a prebiased load. Allowable pre-bias is in the range of 0% to 40% of the programmed output voltage. The Pre-Bias feature is controlled by the EN_PB pin. For the pre-Bias feature to function properly, VDDQ must be stable; Enable must be toggled; and a pre-bias must be present at the output. Phase-Lock Operation: With M_S pin floating or at a logical ‘0,’ the internal switching clock of the DC/DC converter can be phase-locked to a clock signal applied to S_IN. When a clock signal is present at S_IN, an activity detector recognizes the presence of the clock signal and the internal oscillator phase locks to the external clock. The external clock could be the system clock or the output of another EV1380. A delayed version of the phase locked clock is output at S_OUT. The clock frequency should be within 1.25MHz to 1.75MHz for guaranteed phase-lock. Two EV1380 devices on a system board may be daisy chained with appropriate phase delays to reduce or eliminate input ripple as well as avoid beat frequency components. ©Enpirion 2010 all rights reserved, E&OE Master / Slave (Parallel) Operation: Up to two EV1380 devices may be connected in a Master / Slave configuration to handle larger load currents. The Master device’s switching clock may be phase-locked to an external clock source or another EV1380. The device is placed in Master mode by pulling the M_S pin low or in Slave mode by pulling M_S pin high. When this pin is in Float state, parallel operation is not possible. In Master mode, the internal PWM signal is output on the S_OUT pin. The PWM signal at S_OUT is delayed relative to the Master device’s internal PWM signal. This PWM signal from the Master is fed to the Slave device at its S_IN input. The Slave device acts like an extension of the power FETs in the Master. The inductor in the slave prevents crow-bar currents from Master to slave due to timing delays. Enpirion does not recommend paralleling more than 2 EV1380’s. POK Operation The internal POK signal is asserted when VDDQ > 0.3V and 0.45*VDDQ < VOUT < 0.55*VDDQ, indicating VOUT is tracking VDDQ. This assertion range assumes typical VDDQ slew rates associated with VDDQ POL regulators. For typical VDDQ POL regulators, the VDDQ ramp rate will range from 0.5 V/mSec to 2 V/mSec. Within this range of slew rates, the speed of the POK circuit, the loop bandwidth, and the delay caused by the softstart capacitor on the VREF pin will not significantly affect the measured POK threshold. For much faster VDDQ ramp rates, hot-plug slew rates for example, the speed and latency of the elements will cause the measured VOUT voltage where POK is valid to be higher than the actual threshold. The internal EV1380 POK is AND’ed with the VDDQOK input. The VDDQOK input is driven by the upstream VDDQ regulator’s POK output. Normally the VDDQOK input indicates that VDDQ has settled to the required level. If VDDQ is dynamically switched, VDDQOK is expected to mask the EV1380 POK during the voltage transition. POK is not guaranteed to be valid when VDDQ < 300mV. The POK signal is asserted high when rising VOUT 10 www.enpirion.com EV1380 Datasheet Rev A voltage crosses 46% (nominal) of VDDQ. POK is de-asserted low ~64 clock cycles after the falling VOUT voltage crosses 45% (nominal) of VDDQ. POK is also de-asserted if VOUT exceeds 55% (nominal) of VDDQ. For proper POK thresholds, the input voltage divider must generate VREF = ~0.4*VDDQ. Over Current Protection The current limit function is achieved by sensing the current flowing in the hi-Side FET. The OCP trip point is nominally set to 225% of maximum rated load at VDDQ=1.5V. When the sensed current exceeds the current limit, both power FETs are turned off for the rest of the switching cycle. If the over-current condition lasts only a few switching cycles, normal PWM operation is resumed. If the over-current condition persists, the circuit will continue to protect the load by entering a hiccup mode. In the hiccup mode, the output is disabled for approximately 20ms and then it goes through a soft-start. The output will no longer track the input voltage briefly as a result of the fault condition. This cycle can continue indefinitely as long as the over current condition persists. Thermal Overload Protection Temperature sensing circuits in the controller will disable operation when the Junction temperature exceeds approximately 150ºC. When the junction temperature drops by approx 20ºC, the converter will re-start with a normal soft-start cycle. Input Under-Voltage Lock-Out When the controller voltage AVIN is below a required voltage level (VUVLOR) for normal operation, converter switching is inhibited. The lock-out threshold has hysteresis to prevent chatter. When the device is operating normally, the input voltage must fall below the lower threshold (VUVLOF) for the device to stop switching. Application Information / Layout Recommendation Soft-start Capacitor Selection A soft-start capacitor is recommended on the EV1380’s VREF pin. The soft start capacitor serves as both a noise filter for noise on VDDQ as well as a slew rate limiter for fast VDDQ input ramps. The soft start time constant is determined by the value of this capacitor and the input divider resistors RC and RD. See figure 5. For most applications, Enpirion recommends a 0.1µF capacitor on this node. SCHOTTKY VDDQ VCNTRL CIN VTT SW VDDQ EV1380 RC ENABLE AVIN VFB PGND PGND VREF RD VOUT CSS CAVIN AGND FQADJ R1 RA RPD CA RB RFS Output Voltage Programming and loop Compensation Figure 5: Typical Application Schematic The output voltage of EV1380QI is determined by the two voltage dividers as shown in the simplified application diagram of Figure 5. In steady state, VREF = VFB, and VOUT = 0.5 *VDDQ with proper selection of RA and RB. The VDDQ voltage divider consisting of RC and RD should be selected to make VREF = ~0.4 * VDDQ for proper POK operation. Enpirion recommends RC = 3.01kΩ and RD = 2kΩ. This requirement ensures proper POK operation. RA and RB are calculated using the equations in Figure 6. For best voltage accuracy 0.1% resistors are recommended for RA−RD. For example, for VDDQ = 1.5V, RA = 60.4kΩ, RB = 240kΩ. ©Enpirion 2010 all rights reserved, E&OE 11 www.enpirion.com COUT EV1380 Datasheet Rev A Although the EV1380 integrates most of the compensation network, a phase lead capacitor and a resistor are required in parallel with the upper resistor Ra of the external feedback network as shown in Figure 6. For the 1.5V VDDQ example stated above, CA = 120pF. The compensation is optimized for use with 3x100μF or 4x100μF 1206, X5R ceramic output capacitors. In exceptional cases, modifications to the compensation might be required. The EV1380’s compensation can be modified for specific applications. For more information, contact Enpirion Applications Engineering support. VTT RA R A = 40,000 ⋅ VDDQ (value in Ω ) R1 CA = CA RB VFB 8 × 10 −6 RA (C A /R A in F/Ω ) capacitors maybe needed in parallel with the larger capacitors in order to provide high frequency decoupling. Recommended Input Capacitors Description RB = 4 ⋅ R A ⎛ VFB is 0.6V ⎜⎜ ⎝ nominal ⎞ ⎟⎟ ⎠ R1 = 3 kΩ Figure 6: External Feedback and Compensation Network Enable Operation The ENABLE pin should be tied to VDDQ through an 0201 resistor. With the device input power applied, the device automatically starts to operate with a soft-start, provided the AVIN voltage is above the upper UVLO high threshold of ~2.2 volts. LMK316BJ476ML-T Murata GRM21BR60G476M Murata GRM31CR60J107M The EV1380 has been optimized for use with an output capacitance of 300−400µF. Low ESR ceramic capacitors are required with X5R or X7R dielectric formulation. Y5V or equivalent dielectric formulations must not be used as these lose capacitance with frequency, temperature and bias voltage. Recommended Output Capacitors Description MFG 47uF, 10V, X5R, 1206 P/N Taiyo Yuden Taiyo Yuden Murata 47uF, 6.3V, X5R, 1206 100uF, 6.3V, X5R, 1206 LMK316BJ476ML-T JMK316BJ476ML-T GRM31CR60J476ME19L Murata GRM31CR60J107M Output ripple voltage is primarily determined by the aggregate output capacitor impedance. At the 1.5MHz switching frequency output impedance, denoted as Z, is comprised mainly of effective series resistance, ESR, and effective series inductance, ESL: Z = ESR + ESL. Placing multiple capacitors in parallel reduces the impedance and hence will result in lower ripple voltage. 1 Input Capacitor Selection The EV1380 requires between 80uF and 100uF of input capacitance. Low ESR ceramic capacitors are required with X5R or X7R dielectric formulation. Y5V or equivalent dielectric formulations must not be used because these dielectrics lose capacitance with frequency, temperature and bias voltage. P/N Taiyo Yuden Output Capacitor Selection Round C A down to closest standard value lower than calculated value. MFG 47uF, 10V, X5R, 1206 47uF, 4V, X5R, 0805 100uF, 6.3V, X5R, 1206 Z Total = 1 1 1 + + ... + Z1 Z 2 Zn Typical Ripple Voltages Output Capacitor Configuration Typical Output Ripple (mVp-p) VDDQ = 1.5V, VOUT = 0.75V 3 x 100 uF <10mV In some applications, lower value ceramic ©Enpirion 2010 all rights reserved, E&OE 12 www.enpirion.com EV1380 Datasheet Rev A Ternary Pins M_S is a Ternary pin. This pin can assume three states – A low state, a high state and a float state. Device operation is controlled by the state of the pin. The pins may be pulled to ground or left floating without any special care. However when pulling high, it is recommended that this pin is tied to VIN with a series resistor. Using the equations in Figure 7, the resistor value may be optimized to reduce the current drawn by the pin. 2.5V R1 100k PIN To VIN REXT To Gates D1 Vf ~ 2V R3 7k R2 100k Maximum value of REXT= (VIN-2)*67k Input pin current = (VIN -2)/REXT AGND EV1380QI Figure 7: Selection of REXT to Connect Ternary Pins to VIN M_S (Master/Slave) Pin States M_S Pin Function Low This is Master mode. Switching phase locked to S_IN external clock. S_OUT outputs a delayed version of internal PWM signal Float Parallel operation is disabled. Switching phase locked to S_IN external clock. S_OUT outputs a delayed version of switching clock This is Slave mode. The S_IN signal directly drives the power FETs. S_OUT outputs a delayed version of S_IN NOTE: Enpirion Applications can be contacted for additional information on the Parallel operation of up to two EV1380s for high output current. High ©Enpirion 2010 all rights reserved, E&OE 13 www.enpirion.com EV1380 Datasheet Rev A Design Considerations Exposed Metal on Bottom of Package Package lead frames offer advantages in thermal performance, in reduced electrical lead resistance, and in overall foot print. They do, however, require some special considerations. In the assembly process, lead-frame construction requires-for mechanical supportthat some of the lead-frame cantilevers be exposed at the point where wire-bonds or internal passives are attached. Because of this lead frame requirement, several small pads are exposed on the bottom of the package. Only the large thermal pad and the perimeter pads should be mechanically or electrically connected to the PC board. The PCB top layer under the EV1380 should be clear of any metal except for the large thermal pad. The “grayedout” area in Figure 8 represents the area that should be clear of all metal (traces, vias, or planes) on the top layer of the PCB. Figure 8: Lead-Frame Exposed Metal. Gray area highlights exposed metal below which there should not be any metal (traces, vias, or planes) on the top layer of the PCB ©Enpirion 2010 all rights reserved, E&OE 14 www.enpirion.com EV1380 Datasheet Rev A Recommended PCB Footprint Figure 9: EV1380 Package PCB Footprint ©Enpirion 2010 all rights reserved, E&OE 15 www.enpirion.com EV1380 Datasheet Rev A Package and Mechanical Figure 10: EV1380 Package Dimensions Contact Information Enpirion, Inc. Perryville III 53 Frontage Road, Suite 210 Hampton, NJ 08827 USA Phone: 908-894-6000 Fax: 908-894-6090 Enpirion reserves the right to make changes in circuit design and/or specifications at any time without notice. Information furnished by Enpirion is believed to be accurate and reliable. Enpirion assumes no responsibility for its use or for infringement of patents or other third party rights, which may result from its use. Enpirion products are not authorized for use in nuclear control systems, as critical components in life support systems or equipment used in hazardous environment without the express written authority from Enpirion. ©Enpirion 2010 all rights reserved, E&OE 16 www.enpirion.com