austriamicrosystems AG is now ams AG The technical content of this austriamicrosystems datasheet is still valid. Contact information: Headquarters: ams AG Tobelbaderstrasse 30 8141 Unterpremstaetten, Austria Tel: +43 (0) 3136 500 0 e-Mail: [email protected] Please visit our website at www.ams.com Datasheet AS1364 1 A L o w D r o p o u t L i n e a r Vo l t a g e R e g u l a t o r 1 General Description 2 Key Features Low Dropout: 140mV @ 1A Output Voltage Accuracy: Up to 2.0V to 5.5V Input Voltage The ultra-low dropout device requires only 140mV dropout voltage while delivering a guaranteed 1A load current and is therefore perfectly suited for battery-operated portable applications. lv Fixed VOUT: 1.2V to 5.0V Adjustable VOUT: 1.2V to 5.3V Additionally the AS1364 offers extremely low 10µVRMS (100Hz to 100kHz) or 45µVRMS (10Hz to 1MHz) output voltage noise. Low Ground Current: 35µA Low Shutdown Current: 10nA am lc s on A te G nt st il Table 1. Standard Products ±0.75% al id Guaranteed Output Current: 1A The AS1364 is a low-dropout linear regulator (LDO) designed to operate from 2V to 5.5V input, that delivers a wide range of highly accurate (±0.75%) factory-trimmed output voltages as well as adjustable output voltages (using an external resistor-divider network). Model Output Type BYP SET Low Output Noise: 45µVRMS (from 10Hz to 1MHz) AS1364-AD Adjustable No Yes Thermal Overload Protection AS1364-_ _ Fixed Yes No Output Current Limit Output discharge path during shutdown The device features an internal PMOS pass transistor (for a low supply current of only 35µA), reset output, a low-power shutdown mode, and protection from short-circuit and thermal-overload conditions. 8-pin TDFN 3x3mm Package 3 Applications When in shutdown, a 5k (typ) discharge path is connected between the output pin and ground. The AS1364 is available in a 8-pin TDFN 3x3mm package. The device is ideal for laptops, PDAs, portable audio devices, mobile phones, cordless phones, and any other battery-operated portable device. ca Figure 1. AS1364 - Typical Application Diagram ni 3 VIN ch CIN 4.7µF Te On Off www.austriamicrosystems.com 6 IN OUT IN 2 COUT 4.7µF 5 4 AS1364 OUT 1 POK EN 7 8 VOUT Reset Output CBYP 10nF SET/BYP GND Revision 1.8 1 - 19 AS1364 Datasheet - P i n A s s i g n m e n t s 4 Pin Assignments 8 GND EN 2 7 SET/BYP AS1364 6 OUT IN 4 5 OUT am lc s on A te G nt st il IN 3 lv POK 1 al id Figure 2. Pin Assignments (Top View) 4.1 Pin Descriptions Table 2. Pin Descriptions Pin Number Pin Name 1 POK EN Connect a 100k pull-up resistor from this pin to OUT to obtain an output voltage (see Figure 1). Active-Low Shutdown Input. A logic low disables the output and reduces the supply current to 0.1µA. In shutdown, the POK output is low and OUT high impedance. VDD: Normal operation. GND: Shutdown. IN 2.0V to 5.5V Supply Voltage. Bypass with a 4.7µF input capacitor to GND (see Dropout Voltage on page 11). These inputs are internally connected, but they also must be externally connected for proper operation. Regulator Output. Bypass with a 4.7µF low-ESR output capacitor to GND. Connect the OUT pins together externally. ni 3, 4 OUT ch 5, 6 Note: Open-Drain POK Output. POK remains low while VOUT is below the POK threshold. ca 2 Description SET/BYP 8 GND Exposed pad Connect to Substrate Te 7 www.austriamicrosystems.com Voltage-Setting Input. Connect to GND to select the factory-preset output voltage. Connect this pin to an external resistor-divider for adjustable-output operation (see Figure 1) – (AS1364-AD only) Bypass Pin. Connect a 10nF capacitor from this pin to OUT to improve PSRR and noise performance. (AS1364-AD does not offer this feature) Ground Connect to PCB metal area for heatsink purposes. May be left open or connected to common ground. Revision 1.8 2 - 19 AS1364 Datasheet - A b s o l u t e M a x i m u m R a t i n g s 5 Absolute Maximum Ratings Stresses beyond those listed in Table 3 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in Electrical Characteristics on page 4 is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 3. Absolute Maximum Ratings Min Max Units IN, EN, POK to GND -0.3 +7 V OUT, SET/BYP to GND -0.3 VIN + 0.3 V Comments Electrical Parameters Latch-Up Infinite -100 +100 mA JEDEC 78 kV HBM MIL-Std. 883E 3015.7 methods Electrostatic Discharge ESD 2 am lc s on A te G nt st il Temperature Ranges and Storage Conditions lv Output Short-Circuit Duration al id Parameter Thermal Resistance JA 36.3 ºC/W Operating Temperature Range -40 +85 ºC Storage Temperature Range -65 +150 ºC +125 ºC Junction Temperature +260 ºC The reflow peak soldering temperature (body temperature) specified is in accordance with IPC/JEDEC J-STD-020 “Moisture/Reflow Sensitivity Classification for NonHermetic Solid State Surface Mount Devices”. The lead finish for Pb-free leaded packages is matte tin (100% Sn). Te ch ni ca Package Body Temperature on PCB www.austriamicrosystems.com Revision 1.8 3 - 19 AS1364 Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s 6 Electrical Characteristics Note: All limits are guaranteed. The parameters with min and max values are guaranteed by production tests or SQC (Statistical Quality Control) methods. VIN = VOUT(NOM) + 500mV or VIN = +2.0V (whichever is greater),CIN = COUT = 4.7µF, EN = IN, TAMB = -40°C to +85ºC (unless otherwise specified). Typical values are at TAMB = +25ºC. Symbol Parameter Condition VIN Input Voltage VPOR Power On Reset Min Typ 2.0 Max Unit 5.5 V 1.95 V Falling, 100mV hysteresis 1.79 IOUT = 250mA, TAMB = +25ºC -0.75 IOUT = 250mA -1.5 +1.5 -2 +2 1.2 5.3 V 1.23 V IOUT = 1mA to 1A, VIN > (VOUT + 0.5V) 1 Adjustable Output Voltage Range VSET/BYP SET/BYP Voltage Threshold (Adjustable Mode) IOUT Guaranteed Output Current (RMS) ILIMIT Short-Circuit Current Limit VOUT = 0 In-Regulation Current Limit VOUT > 96% of nominal value, VIN 2.0V am lc s on A te G nt st il VOUT +0.75 lv Output Voltage Accuracy (Preset Mode) 1.87 al id Table 4. Electrical Characteristics VIN = 2.5V, IOUT = 250mA, VOUT set to 2.0V SET/BYP Input Bias Current IQ Ground-Pin Current VIN - VOUT Dropout Voltage VLNR Line Regulation VIN from (VOUT + 100mV) to 5.5V, ILOAD = 5mA VLDR Load Regulation IOUT = 1mA to 1A ca Te ch ni Ripple Rejection Output Voltage Noise www.austriamicrosystems.com 1.1 VSET/BYP = 1.20V 1.5 2.3 1.5 50 ISET PSRR 1.20 1 SET/BYP Threshold 2 1.17 100 -100 nA IOUT = 1A 75 200 IOUT = 250mA, VOUT = 3.3V 35 85 IOUT = 1A, VOUT = 3.3V 140 320 f = 1kHz, IOUT = 10mA 72 f = 10kHz, IOUT = 10mA, CBYP = 10nF 75 f = 10kHz, IOUT = 10mA 65 f = 100kHz, IOUT = 10mA, CBYP = 10nF 54 f = 100kHz, IOUT = 10mA 46 100Hz to 100kHz, COUT = 3.3µF, CBYP = 10nF; 10 100Hz to 100kHz, COUT = 3.3µF; 50 10Hz to 1MHz, COUT = 3.3µF, CBYP = 10nF; 45 10Hz to 1MHz, COUT = 3.3µF; 70 Revision 1.8 A +100 150 78 A mV 35 f = 1kHz, IOUT = 10mA, CBYP = 10nF A 150 IOUT = 100µA -0.125 % µA mV +0.125 %/V 0.001 %/mA dB µVRMS 4 - 19 AS1364 Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s Table 4. Electrical Characteristics (Continued) Symbol Parameter Condition Min Typ Max EN = GND, VIN = 5.5V, TAMB = 25°C 0.01 0.5 EN = GND, VIN = 5.5V 0.1 15 Unit Shutdown Shutdown Supply Current VIH EN Input Threshold VIL 2.0V < VIN < 5.5V 1.6 V 2.0V < VIN < 5.5V 0.6 EN = IN or GND, TAMB = +25ºC 1 TAMB = +85ºC 5 POK Output Low Voltage POK sinking 1mA 0.05 Operating Voltage Range for Valid POK Signal POK sinking 100µA ISHDNN EN Input Bias Current nA V 5.5 V nA POK Threshold lv 0.25 POK Output High leakage Current Thermal Protection V am lc s on A te G nt st il POK Output VOL µA al id IOFF 1.1 POK = 5.5V, TAMB = +25ºC 1 TAMB = +85ºC Rising edge (referenced to VOUT(NOM)) 5 90 94 98 % TSHDNN Thermal Shutdown Temperature 170 ºC TSHDNN Thermal Shutdown Hysteresis 20 ºC 4.7 µF Output Capacitor Output Capacitor COUT Load Capacitor Range Load Capacitor ESR 1 500 m Te ch ni ca 1. Guaranteed by production test of load regulation and line regulation. 2. Dropout voltage is defined as VIN - VOUT, when VOUT is 100mV below the value of VOUT measured for VIN = (VOUT(NOM) + 500mV). Since the minimum input voltage is 2.0V, this specification is only valid when VOUT(NOM) > 2.0V. www.austriamicrosystems.com Revision 1.8 5 - 19 AS1364 Datasheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s 7 Typical Operating Characteristics VIN = VOUT(NOM) + 0.5V, CIN = COUT = 4.7µF, TAMB = 25°C (unless otherwise specified). 3.31 140 3.309 Output Voltage (V) . 120 100 80 60 40 20 3.308 3.307 3.306 3.305 3.304 3.303 3.302 am lc s on A te G nt st il Dropout Voltage (mV) . 160 al id Figure 4. VOUT vs. IOUT; VOUT(NOM) = 3.3V lv Figure 3. VDROP vs. IOUT 3.301 0 3.3 0 200 400 600 800 1000 0 200 Load Current (mA) Figure 5. VOUT vs. Temperature; VOUT(NOM) = 3.3V 3.32 600 800 1000 Figure 6. VOUT vs. VIN; VOUT(NOM) = 3.3V 3.5 3 Output Voltage (V) . 3.315 Output Voltage (V) . 400 Output Current (mA) 3.31 3.305 3.3 3.295 3.29 2.5 2 1.5 1 no load 0.5 ca Iout = 1A 3.285 -45 -30 -15 0 15 30 45 60 0 75 90 0 1 Temperature (°C) Quiescent Current (µA) 100 80 60 40 70 60 50 40 30 20 20 10 0 0 2 3 4 5 6 Vin = 3.8V Vin = 5.5V 0 Input Voltage (V) www.austriamicrosystems.com 6 80 Iout = 1A 120 1 5 90 no load 140 0 4 Figure 8. Quiescent Current vs. IOUT Te Quiescent Current (µA) ch . 160 3 . ni Figure 7. Quiescent Current vs. VIN 180 2 Input Voltage (V) 200 400 600 800 1000 Output Current (mA) Revision 1.8 6 - 19 AS1364 Datasheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s Figure 9. Quiescent Current vs. Temperature Figure 10. Spectral Noise vs. Freq; IOUT = 10mA 90 10 COUT = 3.3µF . 60 50 40 30 20 no load 10 Iout = 250mA 0 -45 -30 -15 0 15 30 45 60 75 90 1 al id 70 0.1 0.01 0.01 Temperature (°C) 0.1 1 lv Quiescent Current (µA) . Output Noise Density (µV/ Hz) 80 10 100 1000 am lc s on A te G nt st il Frequency (kHz) Figure 11. PSRR vs. Frequency; IOUT = 10mA 100 PSRR (dB) . 80 60 40 20 0 0.01 1 100 10000 Te ch ni ca Frequency (kHz) www.austriamicrosystems.com Revision 1.8 7 - 19 AS1364 Datasheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s 200mA/Div al id VOUT 100µs/Div am lc s on A te G nt st il 5µs/Div lv IOUT 20mV/Div VIN VOUT 20µs/Div Te ch ni ca 1ms/Div 1V/Div 1V/Div Figure 15. Startup; VIN = 3.8V, IOUT = 100mA 1V/Div VOUT VIN Figure 14. Startup; VIN = 3.8V, IOUT = 100mA 1V/Div VIN VOUT 50mV/Div Figure 13. Load Transient Response; VIN = 3.8V, IOUT = 50mA to 500mA 200mV/Div Figure 12. Line Transient Response; VIN = 3.8V to 4.3V, IOUT = 100mA www.austriamicrosystems.com Revision 1.8 8 - 19 AS1364 Datasheet - D e t a i l e d D e s c r i p t i o n 8 Detailed Description The AS1364 output voltage is factory-trimmed or is adjustable from +1.2V to +5V, and is guaranteed to supply 1A of output current. The device consists of a +1.20V internal reference, error amplifier, MOSFET driver, P-channel pass transistor, internal feedback voltage-divider and a comparator (see Figure 16). VIN 2.0V to 5.5V lv al id Figure 16. AS1364 - Block Diagram 4 IN 3 CIN 4.7µF Thermal Sensor am lc s on A te G nt st il IN 5 MOSFET Driver w/ILIM OUT VOUT 1.2V to 5.0V 6 2 On Off EN Shutdown Logic OUT 1.20V Reference + Error Amplifier VOUT Logic Supply Voltage RPOK 100k To Controller COUT 4.7µF 5k – R1 1 7 POK + – 94%VREF SET/BYP + – + – 100mV R2 + – 8 GND ch ni ca AS1364 Te Figure 16 shows the block diagram of the AS1364. It identifies the basics of a series linear regulator employing a P-Channel MOSFET as the control element. A stable voltage reference (1.2V REF in Figure 16) is compared with an attenuated sample of the output voltage. Any difference between the two voltages (reference and sample) creates an output from the error amplifier that drives the series control element to reduce the difference to a minimum. The error amplifier incorporates additional buffering to drive the relatively large gate capacitance of the series pass Pchannel MOSFET, when additional drive current is required under transient conditions. Input supply variations are absorbed by the series element, and output voltage variations with loading are absorbed by the low output impedance of the regulator. When in shutdown, a 5k discharge path is connected between the output terminal and ground. www.austriamicrosystems.com Revision 1.8 9 - 19 AS1364 Datasheet - D e t a i l e d D e s c r i p t i o n 8.1 Output Voltage Selection At the factory trimmed versions of the AS1364 offering the bypass pin (see Figure ), the output voltage is then set to an internally trimmed voltage (see Ordering Information on page 18). For the adjustable AS1364-AD, an output voltage between +1.2V and +5V can be set by using two external resistors (see Figure 17). In this mode, VOUT is determined by: R1 V OUT = V SETBYP 1 + ------ R 2 al id (EQ 1) Where: VSET/BYP = 1.2V ±0.03V A simplification of R1 and R2 selection is: V OUT R 1 = R 2 --------------------- – 1 V SETBYP lv (EQ 2) am lc s on A te G nt st il Since the input bias current at SET is less than 100nA, large resistance values can be used for R1 and R2 to minimize power consumption and therefore increasing efficiency. Note: Up to 125k is acceptable for R2. If the SET pin is connected to GND without a resistor, 3.3V will be set as output voltage. In preset voltage mode, the impedance from SET to GND should be less than 10k or spurious conditions may cause the voltage at SET to exceed the 50mV threshold. Figure 17. Adjustable Output Voltage Typical Application 3 5 IN VIN CIN 4.7µF On Off OUT 4 IN 2 6 AS1364 R1 OUT COUT 4.7µF VOUT 7 SET/BYP EN 1 8 POK Reset Output R2 ni ca GND ch 8.2 Shutdown If pin EN is connected to GND the AS1364 is disabled. In shutdown mode all internal circuits are turned off, reducing supply current to 10nA (typ). For normal device operation pin EN must be connected to IN. During shutdown, POK goes low. Te When in shutdown, a 5k (typ) discharge path is connected between the output pin and ground. 8.3 Power-OK The AS1364 features a power-ok indicator that asserts when the output voltage falls out of regulation. The open-drain POK output goes low when output voltage at OUT falls 6% below its nominal value. A 100k pull-up resistor from POK to a (typically OUT) provides a logic control signal. POK can be used as a power-on-reset (POR) signal to a microcontroller or can drive an external LED to indicate a power failure condition. Note: POK is low during shutdown. www.austriamicrosystems.com Revision 1.8 10 - 19 AS1364 Datasheet - A p p l i c a t i o n I n f o r m a t i o n 9 Application Information 9.1 Dropout Voltage Dropout is the input to output voltage difference, below which the linear regulator ceases to regulate. At this point, the output voltage change follows the input voltage change. Dropout voltage may be measured at different currents and, in particular at the regulator maximum one. From this is obtained the MOSFET maximum series resistance over temperature etc. More generally: V DROPOUT = I LOAD R SERIES al id (EQ 3) Dropout is probably the most important specification when the regulator is used in a battery application. The dropout performance of the regulator defines the useful “end of life” of the battery before replacement or re-charge is required. lv Figure 18. Graphical Representation of Dropout Voltage am lc s on A te G nt st il VIN VOUT VIN = VOUT(TYP) + 0.5V Dropout Voltage VOUT 100mV VIN VOUT VIN ni 9.2 Efficiency ca Figure 18 shows the variation of VOUT as VIN is varied for a certain load current. The practical value of dropout is the differential voltage (VOUTVIN) measured at the point where the LDO output voltage has fallen by 100mV below the nominal, fully regulated output value. The nominal regulated output voltage of the LDO is that obtained when there is 500mV (or greater) input-output voltage differential. ch Low quiescent current and low input-output voltage differential are important in battery applications amongst others, as the regulator efficiency is directly related to quiescent current and dropout voltage. Efficiency is given by: V I V IN I Q + I LOAD LOAD LOAD Efficiency = --------------------------------------- 100 % (EQ 4) Te Where: IQ = Quiescent current of LDO www.austriamicrosystems.com Revision 1.8 11 - 19 AS1364 Datasheet - A p p l i c a t i o n I n f o r m a t i o n 9.3 Power Dissipation Maximum power dissipation (PD) of the LDO is the sum of the power dissipated by the internal series MOSFET and the quiescent current required to bias the internal voltage reference and the internal error amplifier, and is calculated as: PD MAX Seriespass = I LOAD MAX V IN MAX – V OUT MIN Watts (EQ 5) Internal power dissipation as a result of the bias current for the internal voltage reference and the error amplifier is calculated as: PD MAX Bias = V IN MAX I Q Watts al id (EQ 6) Total LDO power dissipation is calculated as: PD MAX Total = PD MAX Seriespass + PD MAX Bias Watts (EQ 7) 9.4 Junction Temperature lv Under all operating conditions, the maximum junction temperature should not be allowed to exceed 125ºC (unless the data sheet specifically allows). Limiting the maximum junction temperature requires knowledge of the heat path from junction to case (JCºC/W fixed by the IC manufacturer), and adjustment of the case to ambient heat path (CAºC/W) by manipulation of the PCB copper area adjacent to the IC position. am lc s on A te G nt st il Figure 19. Package Physical Arrangements TDFN Package Chip Package Bond Wire Lead Frame PCB Exposed Pad ni ca Figure 20. Steady State Heat Flow Equivalent Circuit Te ch Junction TJ°C Package TC°C RJC Ambient TA°C PCB/Heatsink TS°C RCS RSA Chip Power www.austriamicrosystems.com Revision 1.8 12 - 19 AS1364 Datasheet - A p p l i c a t i o n I n f o r m a t i o n Total Thermal Path Resistance: R JA = R JC + R CS + R SA (EQ 8) T J = PD MAX R JA + T AMB ºC (EQ 9) Junction Temperature (TJºC) is determined by: 9.5.1 al id 9.5 Explanation of Steady State Specifications Line Regulation Line regulation is defined as the change in output voltage when the input (or line) voltage is changed by a known quantity. It is a measure of the regulator’s ability to maintain a constant output voltage when the input voltage changes. Line regulation is a measure of the DC open loop gain of the error amplifier. More generally: lv V V IN OUT Line Regulation = ---------------- and is a pure number am lc s on A te G nt st il In practise, line regulation is referred to the regulator output voltage in terms of % / VOUT. This is particularly useful when the same regulator is available with numerous output voltage trim options. V V IN 100 V OUT OUT Line Regulation = ---------------- ------------ % / V 9.5.2 Load Regulation (EQ 10) Load regulation is defined as the change of the output voltage when the load current is changed by a known quantity. It is a measure of the regulator’s ability to maintain a constant output voltage when the load changes. Load regulation is a measure of the DC closed loop output resistance of the regulator. More generally: V I OUT OUT Load Regulation = ---------------- and is units of ohms () (EQ 11) In practise, load regulation is referred to the regulator output voltage in terms of % / mA. This is particularly useful when the same regulator is available with numerous output voltage trim options. V I OUT 100 V OUT OUT Load Regulation = ---------------- ---------------- % / mA 9.5.3 Setting Accuracy (EQ 12) ca Accuracy of the final output voltage is determined by the accuracy of the ratio of R1 and R2, the reference accuracy and the input offset voltage of the error amplifier. When the regulator is supplied pre-trimmed, the output voltage accuracy is fully defined in the output voltage specification. When the regulator has a SET terminal, the output voltage may be adjusted externally. In this case, the tolerance of the external resistor network must be incorporated into the final accuracy calculation. Generally: ni R1 R1 V OUT = V SET V SET 1 + --------------------- R2 R2 (EQ 13) ch The reference tolerance is given both at 25ºC and over the full operating temperature range. 9.5.4 Total Accuracy Te Away from dropout, total steady state accuracy is the sum of setting accuracy, load regulation and line regulation. Generally: Total % Accuracy = Setting % Accuracy + Load Regulation % + Line Regulation % www.austriamicrosystems.com Revision 1.8 (EQ 14) 13 - 19 AS1364 Datasheet - A p p l i c a t i o n I n f o r m a t i o n 9.6 Explanation of Dynamic Specifications 9.6.1 Power Supply Rejection Ratio (PSRR) V OUT V IN PSSR = 20Log ---------------- dB using lower case to indicate AC values (EQ 15) Power supply rejection ratio is fixed by the internal design of the regulator. Additional rejection must be provided externally. 9.6.2 al id Known also as Ripple Rejection, this specification measures the ability of the regulator to reject noise and ripple beyond DC. PSRR is a summation of the individual rejections of the error amplifier, reference and AC leakage through the series pass transistor. The specification, in the form of a typical attenuation plot with respect to frequency, shows up the gain bandwidth compromises forced upon the designer in low quiescent current conditions. Generally: Output Capacitor ESR lv The series regulator is a negative feedback amplifier, and as such is conditionally stable. The ESR of the output capacitor is usually used to cancel one of the open loop poles of the error amplifier in order to produce a single pole response. Excessive ESR values may actually cause instability by excessive changes to the closed loop unity gain frequency crossover point. The range of ESR values for stability is usually shown either by a plot of stable ESR versus load current, or a limit statement in the datasheet. am lc s on A te G nt st il Some ceramic capacitors exhibit large capacitance and ESR variations with temperature. Z5U and Y5V capacitors may be required to ensure stability at temperatures below TAMB = -10ºC. With X7R or X5R capacitors, a 4.7µF capacitor should be sufficient at all operating temperatures. Larger output capacitor values (10µF max) help to reduce noise and improve load transient-response, stability and power-supply rejection. 9.6.3 Input Capacitor An input capacitor at VIN is required for stability. It is recommended that a 4.7µF capacitor be connected between the AS1364 power supply input pin VIN and ground (capacitance value may be increased without limit subject to ESR limits). This capacitor must be located at a distance of not more than 1cm from the VIN pin and returned to a clean analog ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input. 9.6.4 Noise The regulator output is a DC voltage with noise superimposed on the output. The noise comes from three sources; the reference, the error amplifier input stage, and the output voltage setting resistors. Noise is a random fluctuation and if not minimized in some applications, will produce system problems. 9.6.5 Transient Response The series regulator is a negative feedback system, and therefore any change at the output will take a finite time to be corrected by the error loop. This “propagation time” is related to the bandwidth of the error loop. The initial response to an output transient comes from the output capacitance, and during this time, ESR is the dominant mechanism causing voltage transients at the output. More generally: ca V TRANSIENT = I OUTPUT R ESR Units are Volts, Amps, Ohms. (EQ 16) Thus an initial +50mA change of output current will produce a -12mV transient when the ESR=240m. Remember to keep the ESR within stability recommendations when reducing ESR by adding multiple parallel output capacitors. ni After the initial ESR transient, there follows a voltage droop during the time that the LDO feedback loop takes to respond to the output change. This drift is approx. linear in time and sums with the ESR contribution to make a total transient variation at the output of: ch T V TRANSIENT = I OUTPUT R ESR + ---------------- C LOAD Units are Volts, Seconds, Farads, Ohms. (EQ 17) Te Where: CLOAD is output capacitor T = Propagation delay of the LDO This shows why it is convenient to increase the output capacitor value for a better support for fast load changes. Of course the formula holds for t < “propagation time”, so that a faster LDO needs a smaller cap at the load to achieve a similar transient response. For instance 50mA load current step produces 50mV output drop if the LDO response is 1usec and the load cap is 1µF. There is also a steady state error caused by the finite output impedance of the regulator. This is derived from the load regulation specification discussed above. www.austriamicrosystems.com Revision 1.8 14 - 19 AS1364 Datasheet - A p p l i c a t i o n I n f o r m a t i o n 9.6.6 Turn On Time This specification defines the time taken for the LDO to awake from shutdown. The time is measured from the release of the enable pin to the time that the output voltage is within 5% of the final value. It assumes that the voltage at VIN is stable and within the regulator Min and Max limits. Shutdown reduces the quiescent current to very low, mostly leakage values (<1µA). 9.6.7 Thermal Protection Te ch ni ca am lc s on A te G nt st il lv al id To prevent operation under extreme fault conditions, such as a permanent short circuit at the output, thermal protection is built into the device. Die temperature is measured, and when a 170ºC (AS1364) threshold is reached, the device enters shutdown. When the die cools sufficiently, the device will restart (assuming input voltage exists and the device is enabled). Hysteresis of 20ºC prevents low frequency oscillation between startup and shutdown around the temperature threshold. www.austriamicrosystems.com Revision 1.8 15 - 19 AS1364 Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g s 10 Package Drawings and Markings The device is available in an 8-pin TDFN 3x3mm package. Figure 21. 8-pin TDFN 3x3mm Package D D2 B D 2/2 al id A SEE DE TAIL B aaa C PIN 1 INDEX AREA (D/2 xE/2) 4 lv 2x E E2 E2/2 NX L NX K PIN 1 INDEX AREA (D/2 xE/2) 4 aaa C 7 2x NX b e (ND -1) X e 5 bbb C A B am lc s on A te G nt st il TOP VIEW N N -1 e 6 ddd C BTM VIEW Term inal Tip 5 e/2 A A3 ccc C 7 NX 0.08 C C SEATING PLANE A1 S IDE V IEW D atum A or B E VE N T E RMINAL S IDE Typ 0.75 0.02 0.20 REF Max 0.80 0.05 0.15 0.13 ca 0.15 0.10 0.10 0.05 0.08 0.10 Notes 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 Symbol D BSC E BSC D2 E2 L K b e N ND Min 1.60 1.35 0.30 0º 0.20 0.25 Typ 3.00 3.00 0.40 0.30 0.65 8 4 Max 2.50 1.75 0.50 14º 0.35 Notes 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2, 5 1, 2 1, 2, 5 ch Notes: Min 0.70 0.00 ni Symbol A A1 A3 L1 L2 aaa bbb ccc ddd eee ggg Te 1. Figure 21 is shown for illustration only. 2. All dimensions are in millimeters; angles in degrees. 3. Dimensioning and tolerancing conform to ASME Y14.5 M-1994. 4. N is the total number of terminals. 5. The terminal #1 identifier and terminal numbering convention shall conform to JEDEC 95-1, SPP-012. Details of terminal #1 identifier are optional, but must be located within the zone indicated. The terminal #1 identifier may be either a mold or marked feature. 6. Dimension b applies to metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 7. ND refers to the maximum number of terminals on side D. 8. Unilateral coplanarity zone applies to the exposed heat sink slug as well as the terminals www.austriamicrosystems.com Revision 1.8 16 - 19 AS1364 Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g s Revision History Revision Date Owner Description - - - Initial revisions 1.5 Sep 2011 1.6 18 Nov, 2011 1.7 12 Dec, 2011 1.8 03 Apr, 2012 Changes made across document afe al id Updated equations in Power Dissipation section Corrected Figure 1, Figure 16, Figure 17 Te ch ni ca am lc s on A te G nt st il lv Note: Typos may not be explicitly mentioned under revision history. www.austriamicrosystems.com Revision 1.8 17 - 19 AS1364 Datasheet - O r d e r i n g I n f o r m a t i o n 11 Ordering Information The device is available as the standard products shown in Table 5. Table 5. Ordering Information Marking Output SET/BYP Delivery Form Package AS1364-BTDT-AD ASRF Adjustable (preset to 3.3V) SET Tape and Reel 8-pin TDFN 3x3mm al id Ordering Code ASRN 1.2V BYP Tape and Reel 8-pin TDFN 3x3mm AS1364-BTDT-15 ASRG 1.5V BYP Tape and Reel 8-pin TDFN 3x3mm AS1364-BTDT-18 ASRH 1.8V BYP Tape and Reel 8-pin TDFN 3x3mm AS1364-BTDT-30 ASRJ 3.0V BYP Tape and Reel 8-pin TDFN 3x3mm AS1364-BTDT-33 ASRI 3.3V BYP Tape and Reel 8-pin TDFN 3x3mm AS1364-BTDT-45 ASRK 4.5V BYP Tape and Reel 8-pin TDFN 3x3mm *Future product. lv AS1364-BTDT-12* am lc s on A te G nt st il Non-standard devices are available between 1.4V and 4.6V in 50mV steps and between 4.6V and 5.0V in 100mV steps. For more information and inquiries contact http://www.austriamicrosystems.com/contact Note: All products are RoHS compliant. Buy our products or get free samples online at ICdirect: http://www.austriamicrosystems.com/ICdirect Technical Support is available at http://www.austriamicrosystems.com/Technical-Support Te ch ni ca For further information and requests, please contact us mailto:[email protected] or find your local distributor at http://www.austriamicrosystems.com/distributor www.austriamicrosystems.com Revision 1.8 18 - 19 AS1364 Datasheet - O r d e r i n g I n f o r m a t i o n Copyrights Copyright © 1997-2012, austriamicrosystems AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies. al id Disclaimer lv Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. Headquarters ca Contact Information am lc s on A te G nt st il The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services. austriamicrosystems AG Tobelbaderstrasse 30 A-8141 Unterpremstaetten, Austria ch ni Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01 For Sales Offices, Distributors and Representatives, please visit: Te http://www.austriamicrosystems.com/contact www.austriamicrosystems.com Revision 1.8 19 - 19