TI 74F132

54F132,74F132
Quad 2-Input NAND Schmitt Trigger
Literature Number: SNOS151A
The ’F132 contains four 2-input NAND gates which accept
standard TTL input signals and provide standard TTL output
levels. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. In
addition, they have a greater noise margin than conventional
NAND gates.
Each circuit contains a 2-input Schmitt trigger followed by
level shifting circuitry and a standard FAST ® output structure. The Schmitt trigger uses positive feedback to effectively
speed-up slow input transitions, and provide different input
Ordering Code:
Features
n Guaranteed 4000V minimum ESD protection
n Standard Military Drawing (SMD)
n 5962-89487
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Commercial
See Section 0
threshold voltages for positive and negative-going transitions. This hysteresis between the positive-going and
negative-going input threshold (typically 800 mV) is determined by resistor ratios and is essentially insensitive to temperature and supply voltage variations.
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General Description
Military
Package
Package Description
Number
74F132PC
N14A
14-Lead (0.300" Wide) Molded Dual-In-Line
J14A
14-Lead Ceramic Dual-In-Line
M14A
14-Lead (0.150" Wide) Molded Small Outline, JEDEC
M14D
14-Lead (0.300" Wide) Molded Small Outline, EIAJ
54F132FM (Note 2)
W14B
14-Lead Cerpack
54F132LM (Note 2)
E20A
20-Lead Ceramic Leadless Chip Carrier, Type C
54F132DM (Note 2)
74F132SC (Note 1)
74F132SJ (Note 1)
54F/74F132
54F/74F132
Quad 2-Input NAND Schmitt Trigger
54F/74F132 Quad 2-Input NAND Schmitt Trigger
November 1994
DSXXX
Note 1: Devices also available in 13" reel. Use suffix = SCX and SJX.
Note 2: Military grade device with environmental and burn-in processing. Use suffix = DMQB, FMQB and LMQB.
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Logic Symbol
O
IEEE/IEC
DS009477-3
TRI-STATE ® is a registered trademark of National Semiconductor Corporation.
© 1997 National Semiconductor Corporation
www.national.com
DS009477
PrintDate=1997/08/28 PrintTime=12:25:28 10193 ds009477 Rev. No. 1
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1
Connection Diagrams
Pin Assignment for
DIP, SOIC and Flatpak
Pin Assignment
for LCC
DS009477-1
Unit Loading/Fan Out
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DS009477-2
See Section 0 for U.L. definitions
DSXXX
54F/74F
Pin Names
Description
U.L.
HIGH/LOW
Inputs
1.0/1.0
Outputs
50/33.3
20 µA/−0.6 mA
−1 mA/20 mA
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An, Bn
On
Input IIH/IIL
Output IOH/IOL
Function Table
Inputs
Outputs
A
B
L
L
L
H
H
L
H
H
H
H
H
L
O
bs
H = HIGH Voltage Level
L = LOW Voltage Level
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Current Applied to Output
in LOW State (Max)
ESD Last Passing Voltage (Min)
(Note 3)
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
Plastic
VCC Pin Potential to
Ground Pin
Input Voltage (Note 4)
Input Current (Note 4)
Voltage Applied to Output
in HIGH State (with VCC = 0V)
Standard Output
TRI-STATE ® Output
−65˚C
−55˚C
−55˚C
−55˚C
to
to
to
to
Recommended Operating
Conditions
+150˚C
+125˚C
+175˚C
+150˚C
Free Air Ambient Temperature
Military
Commercial
Supply Voltage
Military
Commercial
−0.5V to +7.0V
−0.5V to +7.0V
−30 mA to +5.0 mA
−0.5V to VCC
−0.5V to +5.5V
Parameter
Positive-going Threshold
1.5
VT−
Negative-going Threshold
0.7
∆VT
Hysteresis (VT+ − VT−)
0.4
VCD
Input Clamp Diode Voltage
VOH
Output HIGH
Voltage
VOL
Output LOW
Voltage
IIH
VID
VCC
2.0
V
5.0
1.1
V
5.0
V
5.0
V
Min
V
Min
V
Min
IOH = −1 mA
IOL = 20 mA
IOL = 20 mA
µA
Max
VIN = 2.7V
µA
Max
VIN = 7.0V
µA
Max
VOUT = VCC
V
0.0
IID = 1.9 µA
−1.2
54F 10% VCC
2.5
74F 10% VCC
2.5
74F 5% VCC
2.7
54F 10% VCC
0.5
0.5
54F
20.0
74F
5.0
Input HIGH Current
54F
100
Breakdown Test
74F
7.0
Output HIGH
54F
250
Leakage Current
74F
50
Input Leakage
74F
bs
ICEX
Units
4.75
Test
IOD
Output Leakage
74F
O
Input LOW Current
3.75
µA
0.0
−0.6
mA
Max
All Other Pins Grounded
VIN = 0.5V
IOS
Output Short-Circuit Current
−150
mA
Max
ICCH
Power Supply Current
17.0
mA
Max
ICCL
Power Supply Current
18.0
mA
Max
−60
IIN = −18 mA
IOH = −1 mA
IOH = −1 mA
All Other Pins Grounded
VIOD = 150 mV
Circuit Current
IIL
Conditions
Max
74F 10% VCC
Input HIGH
Current
IBVI
Typ
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VT+
+4.5V to +5.5V
+4.5V to +5.5V
Note 4: Either voltage limit or current limit is sufficient to protect inputs.
54F/74F
Min
−55˚C to +125˚C
0˚C to +70˚C
Note 3: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under these
conditions is not implied.
DC Electrical Characteristics
Symbol
twice the rated IOL (mA)
4000V
te
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
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PrintDate=1997/08/28 PrintTime=12:25:38 10193 ds009477 Rev. No. 1
VOUT = 0V
VO = HIGH
VO = LOW
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AC Electrical Characteristics
See Section 0 for Waveforms and Load Configurations
Symbol
DSXXX
74F
TA = +25˚C
VCC = +5.0V
Parameter
54F
TA, VCC = Mil
CL = 50 pF
74F
TA, VCC = Com
CL = 50 pF
Fig.
Units
No.
CL = 50 pF
Max
Min
Max
Min
tPLH
Propagation Delay
Min
4.0
Typ
10.5
2.0
13.0
3.5
Max
12.0
tPHL
An, Bn to On
5.0
12.5
4.5
16.0
5.0
13.0
ns
kk-kk
DSXXX
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows:
DS009477-5
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inches (millimeters) unless otherwise noted
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Physical Dimensions
O
bs
20-Lead Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
14-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J14A
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inches (millimeters) unless otherwise noted (Continued)
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Physical Dimensions
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14-Lead (0.150" Wide) Molded Small Outline Package, JEDEC (S)
NS Package Number M14A
14-Lead (0.300" Wide) Molded Small Outline Package, EIAJ (SJ)
NS Package Number M14D
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inches (millimeters) unless otherwise noted (Continued)
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Physical Dimensions
O
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14-Lead (0.300" Wide) (Molded Dual-In-Line Package (P)
NS Package Number N14A
14-Lead Ceramic Flatpak (F)
NS Package Number W14B
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54F/74F132 Quad 2-Input NAND Schmitt Trigger
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LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into
sonably expected to cause the failure of the life support
the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness.
ure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
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Email: [email protected]
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
PrintDate=1997/08/28 PrintTime=12:25:44 10193 ds009477 Rev. No. 1
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