54F676,74F676 54F676 74F676 16-Bit Serial/Parallel-In, Serial-Out Shift Register Literature Number: SNOS213A 54F/74F676 16-Bit Serial/Parallel-In, Serial-Out Shift Register General Description Features The ’F676 contains 16 flip-flops with provision for synchronous parallel or serial entry and serial output. When the Mode (M) input is HIGH, information present on the parallel data (P0 – P15) inputs is entered on the falling edge of the Clock Pulse (CP) input signal. When M is LOW, data is shifted out of the most significant bit position while information present on the Serial (SI) input shifts into the least significant bit position. A HIGH signal on the Chip Select (CS) input prevents both parallel and serial operations. Y Y e Package Number Military Y 16-bit parallel-to-serial conversion 16-bit serial-in, serial-out Chip select control Slim 24 lead 300 mil package Package Description et Commercial Y 74F676PC N24A 24-Lead (0.600× Wide) Molded Dual-In-Line N24C 24-Lead (0.300× Wide) Molded Dual-In-Line 54F676DM (Note 2) J24A 24-Lead (0.600× Wide) Ceramic Dual-In-Line 54F676SDM (Note 2) J24F 24-Lead (0.300× Wide) Ceramic Dual-In-Line M24B 24-Lead (0.300× Wide) Molded Small Outline, JEDEC 54F676FM (Note 2) W24C 24-Lead Cerpack 54F676LM (Note 2) E28A 24-Lead Ceramic Leadless Chip Carrier, Type C 74F676SPC bs ol 74F676SC (Note 1) Note 1: Devices also available in 13× reel. Use suffix e SCX. Note 2: Military grade device with environmental and burn-in processing. Use suffix e DMQB, FMQB and LMQB. Connection Diagrams Pin Assignment for LCC O Pin Assignment for DIP, SOIC and Flatpak TL/F/9588 – 3 TL/F/9588 – 2 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/F/9588 RRD-B30M105/Printed in U. S. A. 54F/74F676 16-Bit Serial/Parallel-In, Serial-Out Shift Register December 1994 Logic Symbols IEEE/IEC e TL/F/9588 – 1 Unit Loading/Fan Out TL/F/9588 – 4 P0 – P15 CS CP M SI SO Description U.L. HIGH/LOW Parallel Data Inputs Chip Select Input (Active LOW) Clock Pulse Input (Active LOW) Mode Select Input Serial Data Input Serial Output 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 50/33.3 Input IIH/IIL Output IOH/IOL 20 mA/b0.6 mA 20 mA/b0.6 mA 20 mA/b0.6 mA 20 mA/b0.6 mA 20 mA/b0.6 mA b 1 mA/20 mA bs ol Pin Names et 54F/74F Functional Description The 16-bit shift register operates in one of three modes, as indicated in the Shift Register Operations Table. HOLDÐa HIGH signal on the Chip Select (CS) input prevents clocking, and data is stored in the sixteen registers. Shift/Serial LoadÐdata present on the SI pin shifts into the register on the falling edge of CP. Data enters the Q0 position and shifts toward Q15 on successive clocks, finally appearing on the SO pin. Parallel LoadÐdata present on P0 – P15 are entered into the register on the falling edge of CP. The SO output represents the Q15 register output. To prevent false clocking, CP must be LOW during a LOWto-HIGH transition of CS. Shift Register Operations Table Control Input CS M CP H L L X L H X K K Operating Mode Hold Shift/Serial Load Parallel Load O H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial K e HIGH-to-LOW Transition Block Diagram TL/F/9588 – 5 2 Absolute Maximum Ratings (Note 1) Recommended Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Storage Temperature b 65§ C to a 150§ C Ambient Temperature under Bias Junction Temperature under Bias Plastic b 55§ C to a 125§ C Free Air Ambient Temperature Military Commercial b 55§ C to a 125§ C 0§ C to a 70§ C Supply Voltage Military Commercial b 55§ C to a 175§ C b 55§ C to a 150§ C a 4.5V to a 5.5V a 4.5V to a 5.5V VCC Pin Potential to Ground Pin b 0.5V to a 7.0V b 0.5V to a 7.0V Input Voltage (Note 2) b 30 mA to a 5.0 mA Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC e 0V) b 0.5V to VCC Standard Output b 0.5V to a 5.5V TRI-STATEÉ Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA) e Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Symbol Parameter et DC Electrical Characteristics 54F/74F Min Input HIGH Voltage VIL Input LOW Voltage VCD Input Clamp Diode Voltage VOH Units VCC 2.0 V Recognized as a HIGH Signal 0.8 V Recognized as a LOW Signal b 1.2 V Min Min IOH e b1 mA IOH e b1 mA IOH e b1 mA 0.5 0.5 V Min IOL e 20 mA IOL e 20 mA 54F 74F 20.0 5.0 mA Max VIN e 2.7V Input HIGH Current Breakdown Test 54F 74F 100 7.0 mA Max VIN e 7.0V Output HIGH Leakage Current 54F 74F 250 50 mA Max VOUT e VCC Input Leakage Test 74F V 0.0 IID e 1.9 mA, All Other Pins Grounded IOD Output Leakage Circuit Current 74F 3.75 mA 0.0 VIOD e 150 mV, All Other Pins Grounded IIL Input LOW Current IIH IBVI ICEX Output LOW Voltage 54F 10% VCC 74F 10% VCC Input HIGH Current O VID 54F 10% VCC 74F 10% VCC 74F 5% VCC IOS Output Short-Circuit Current ICC Power Supply Current 2.5 2.5 2.7 IIN e b18 mA V VOL Output HIGH Voltage Conditions Max bs ol VIH Typ 4.75 b 60 3 b 0.6 mA Max VIN e 0.5V b 150 mA Max VOUT e 0V 72 mA Max AC Electrical Characteristics Symbol Parameter 74F 54F 74F TA e a 25§ C VCC e a 5.0V CL e 50 pF TA, VCC e Mil CL e 50 pF TA, VCC e Com CL e 50 pF Min Typ fmax Maximum Clock Frequency 100 110 tPLH tPHL Propagation Delay CP to SO 4.5 5.0 9.0 9.0 Max Min Max 45 11.0 12.5 Min Max 90 4.5 5.0 17.0 14.5 Units MHz 4.5 5.0 12.0 13.5 ns AC Operating Requirements Parameter 54F 74F TA, VCC e Mil TA, VCC e Com Min Min Min Max Max Units Max e Symbol 74F TA e a 25§ C VCC e a 5.0V ts(H) ts(L) Setup Time, HIGH or LOW SI to CP 4.0 4.0 4.0 4.0 4.0 4.0 th(H) th(L) Hold Time, HIGH or LOW SI to CP 4.0 4.0 4.0 4.0 ts(H) ts(L) Setup Time, HIGH or LOW Pn to CP 3.0 3.0 th(H) th(L) Hold Time, HIGH or LOW Pn to CP 4.0 4.0 ts(H) ts(L) Setup Time, HIGH or LOW M to CP 8.0 8.0 th(H) th(L) Hold Time, HIGH or LOW M to CP 2.0 2.0 2.0 2.0 2.0 2.0 ts(L) Setup Time, LOW CS to CP 10.0 12.0 10.0 th(H) Hold Time, HIGH CS to CP 10.0 10.0 10.0 tw(H) tw(L) CP Pulse Width HIGH or LOW 4.0 6.0 5.0 9.0 4.0 6.0 ns et 4.0 4.0 3.0 3.0 4.0 4.0 4.0 4.0 8.0 8.0 8.0 8.0 O bs ol 3.0 3.0 4 ns ns ns ns Ordering Information The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows: 74F 676 S Temperature Range Family 74F e Commercial 54F e Military C X Special Variations QB e Military grade device with environmental and burn-in processing Device Type Temperature Range C e Commercial (0§ C to a 70§ C) M e Military (b55§ C to a 125§ C) O bs ol et e Package Code Plastic DIP Pe SP e Slim Plastic DIP De Ceramic DIP SD e Slim Ceramic DIP Fe Flatpak Le Leadless Chip Carrier (LCC) Se Small Outline SOIC JEDEC 5 6 e et bs ol O Physical Dimensions inches (millimeters) O bs ol et e 28-Lead Ceramic Leadless Chip Carrier (L) NS Package Number E28A 24-Lead Ceramic Dual-In-Line Package (D) NS Package Number J24A 7 et e Physical Dimensions inches (millimeters) (Continued) O bs ol 24-Lead (0.300× Wide) Ceramic Dual-In-Line Package (SD) NS Package Number J24F 24-Lead (0.300× Wide) Molded Small Outline Package, JEDEC NS Package Number M24B 8 et e Physical Dimensions inches (millimeters) (Continued) O bs ol 24-Lead (0.600× Wide) Molded Dual-In-Line Package (P) NS Package Number N24A 24-Lead (0.300× Wide) Molded Dual-In-Line Package (SP) NS Package Number N24C 9 e et 24 Lead Ceramic Flatpak (F) NS Package Number W24C bs ol 54F/74F676 16-Bit Serial/Parallel-In, Serial-Out Shift Register Physical Dimensions inches (millimeters) (Continued) LIFE SUPPORT POLICY O NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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