TI 54F377

54F377
54F377 Octal D Flip-Flop with Clock Enable
Literature Number: SNOS191A
54F/74F377
Octal D Flip-Flop with Clock Enable
General Description
Features
The ’F377 has eight edge-triggered, D-type flip-flops with
individual D inputs and Q outputs. The common buffered
Clock (CP) input loads all flip-flops simultaneously, when the
Clock Enable (CE) is LOW.
The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output. The CE input must be stable only one setup time prior
to the LOW-to-HIGH clock transition for predictable operation.
Y
74F377PC
54F377DM (QB)
Package
Number
Y
Y
Y
Y
Y
e
Military
Y
Ideal for addressable register applications
Clock enable for address and data synchronization
applications
Eight edge-triggered D flip-flops
Buffered common clock
See ’F273 for master reset version
See ’F373 for transparent latch version
See ’F374 for TRI-STATEÉ version
Guaranteed 4000V minimum ESD protection
Package Description
et
Commercial
Y
N20A
20-Lead (0.300× Wide) Molded Dual-In-Line
J20A
20-Lead Ceramic Dual-In-Line
M20B
74F377SJ (Note 1)
M20D
20-Lead (0.300× Wide) Molded Small Outline, JEDEC
20-Lead (0.300× Wide) Molded Small Outline, EIAJ
bs
ol
74F377SC (Note 1)
54F377FM (QB)
W20A
20-Lead Cerpack
54F377LM (QB)
E20A
20-Lead Ceramic Leadless Chip Carrier, Type C
Note 1: Devices also available in 13× reel. Use suffix e SCX and SJX.
Logic Symbols
O
IEEE/IEC
TL/F/9525 – 1
TL/F/9525 – 4
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
C1995 National Semiconductor Corporation
TL/F/9525
RRD-B30M75/Printed in U. S. A.
54F/74F377 Octal D Flip-Flop with Clock Enable
May 1995
Connection Diagrams
Pin Assignment for
DIP, SOIC and Flatpak
Pin Assignment
for LCC
TL/F/9525 – 3
Unit Loading/Fan Out
54F/74F
D0 – D7
CE
CP
Q0 – Q7
Description
U.L.
HIGH/LOW
Data Inputs
Clock Enable (Active LOW)
Clock Pulse Input
Data Outputs
1.0/1.0
1.0/1.0
1.0/1.0
50/33.3
Inputs
Operating Mode
Load ‘‘1’’
Load ‘‘0’’
20 mA/b0.6 mA
20 mA/b0.6 mA
20 mA/b0.6 mA
b 1 mA/20 mA
bs
ol
Mode Select-Function Table
Input IIH/IIL
Output IOH/IOL
et
Pin Names
e
TL/F/9525–2
Hold
(Do Nothing)
Output
CP
CE
Dn
Qn
L
I
h
H
L
I
I
L
L
X
h
H
X
X
No Change
No Change
H e HIGH Voltage Level
h e HIGH Voltage Level one setup time prior to
the LOW-to-HIGH Clock Transition
L e LOW Voltage Level
I e LOW Voltage Level one setup time prior to
the LOW-to-HIGH Clock Transition
X e Immaterial
L e LOW-to-HIGH Clock Transition
O
Logic Diagram
TL/F/9525 – 5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
2
Absolute Maximum Ratings (Note 1)
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Storage Temperature
b 65§ C to a 150§ C
Ambient Temperature under Bias
Junction Temperature under Bias
Plastic
b 55§ C to a 125§ C
Free Air Ambient Temperature
Military
Commercial
b 55§ C to a 125§ C
0§ C to a 70§ C
Supply Voltage
Military
Commercial
b 55§ C to a 175§ C
b 55§ C to a 150§ C
a 4.5V to a 5.5V
a 4.5V to a 5.5V
VCC Pin Potential to
Ground Pin
e
b 0.5V to a 7.0V
b 0.5V to a 7.0V
Input Voltage (Note 2)
b 30 mA to a 5.0 mA
Input Current (Note 2)
Voltage Applied to Output
in HIGH State (with VCC e 0V)
b 0.5V to VCC
Standard Output
b 0.5V to a 5.5V
TRI-STATE Output
Current Applied to Output
in LOW State (Max)
twice the rated IOL (mA)
ESD Last Passing Voltage (Min)
4000V
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under
these conditions is not implied.
DC Electrical Characteristics
Symbol
Parameter
et
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
54F/74F
Min
Input HIGH Voltage
VIL
Input LOW Voltage
VCD
VOH
VOL
IIH
IBVI
IIL
IOS
ICEX
2.0
0.8
Input Clamp Diode Voltage
VCC
Conditions
V
Recognized as a HIGH Signal
V
Recognized as a LOW Signal
V
Min
IIN e b18 mA
V
Min
IOH e b1 mA
IOH e b1 mA
IOH e b1 mA
0.5
0.5
V
Min
IOL e 20 mA
IOL e 20 mA
Input HIGH Current
5.0
mA
Max
VIN e 2.7V
Input HIGH Current
Breakdown Test
7.0
mA
Max
VIN e 7.0V
Output HIGH
Voltage
54F 10% VCC
74F 10% VCC
74F 5% VCC
Output LOW
Voltage
54F 10% VCC
74F 10% VCC
b 1.2
2.5
2.5
2.7
Input LOW Current
Output Short-Circuit Current
b 60
Output HIGH Leakage Current
Input Leakage Test
O
VID
Units
Max
bs
ol
VIH
Typ
IOD
Output Leakage Circuit Current
ICCH
ICCL
Power Supply Current
b 0.6
mA
Max
VIN e 0.5V
b 150
mA
Max
VOUT e 0V
50
mA
Max
VOUT e VCC
V
0.0
IID e 1.9 mA
All Other Pins Grounded
3.75
mA
0.0
VIOD e 150 mV
All Other Pins Grounded
46
56
mA
Max
CP e L
Dn e MR e HIGH
4.75
35
44
3
AC Electrical Characteristics
Symbol
Parameter
74F
54F
74F
TA e a 25§ C
VCC e a 5.0V
CL e 50 pF
TA, VCC e Mil
CL e 50 pF
TA, VCC e Com
CL e 50 pF
Min
fMax
Maximum Clock Frequency
130
tPLH
tPHL
Propagation Delay
CP to Qn
3.0
4.0
Typ
Max
Min
Max
85
7.0
9.0
Min
Max
105
2.0
3.0
8.5
10.5
Units
MHz
2.5
3.5
7.5
9.0
ns
AC Operating Requirements
Parameter
54F
74F
TA, VCC e Mil
TA, VCC e Com
Min
Min
Min
Max
Setup Time, HIGH or LOW
Dn to CP
3.0
3.5
3.5
4.0
th(H)
th(L)
Hold Time, HIGH or LOW
Dn to CP
0.5
1.0
1.0
1.0
ts(H)
ts(L)
Setup Time, HIGH or LOW
CE to CP
4.1
3.5
th(H)
th(L)
Hold Time, HIGH to LOW
CE to CP
0.5
2.0
tw(H)
tw(L)
Clock Pulse Width,
HIGH or LOW
6.0
6.0
Max
Max
3.0
3.5
ns
0.5
1.0
ns
et
ts(H)
ts(L)
Units
e
Symbol
74F
TA e a 25§ C
VCC e a 5.0V
4.1
4.0
ns
1.5
2.5
0.5
2.0
ns
5.0
5.0
6.0
6.0
ns
bs
ol
4.0
5.0
Ordering Information
The device number is used to form part of a simplified purchasing code where a package type and temperature range are
defined as follows:
74F
377
S
Temperature Range Family
74F e Commercial
54F e Military
C
X
Special Variations
X e Devices shipped in 13× reels
QB e Military grade with environmental
and burn-in processing shipped
in tubes
Device Type
Package Code
P e Plastic DIP
D e Ceramic DIP
S e Small Outline SOIC JEDEC
SJ e Small Outline SOIC EIAJ
O
Temperature Range
C e Commercial (0§ C to a 70§ C)
M e Military (b55§ C to a 125§ C)
4
5
e
et
bs
ol
O
et
e
Physical Dimensions inches (millimeters)
O
bs
ol
20-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J20A
20-Lead (0.300× Wide) Molded Small Outline Package, JEDEC (S)
NS Package Number M20B
6
et
e
Physical Dimensions inches (millimeters) (Continued)
O
bs
ol
20-Lead (0.300× Wide) Molded Small Outline Package, EIAJ (SJ)
NS Package Number M20D
7
e
et
20-Lead (0.300× Wide) Molded Dual-In-Line Package (P)
NS Package Number N20A
bs
ol
54F/74F377 Octal D Flip-Flop with Clock Enable
Physical Dimensions inches (millimeters) (Continued)
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O
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