EMIF03-SIM04F3 3-line IPAD™, EMI filter including ESD protection Features ■ EMI symmetrical (I/O) low-pass filter ■ high efficiency in EMI/ESD protection ■ lead-free package ■ very thin package ■ high reliability offered by monolithic integration ■ high reduction of parasitic elements through integration and wafer level packaging Complies with the following standards ■ ■ Lead-free Flip-Chip package (11 bumps) Figure 1. Pin configuration (bump side) 1 IEC 61000-4-2 level 4: – ± 15 kV (air discharge) – ± 8 kV (contact discharge) 2 3 A B IEC 61000-4-2 level 1: – ± 2 kV (air discharge) – ± 2 kV (contact discharge) C D Applications Where EMI filtering in ESD sensitive equipment is required: ■ mobile phones and communication systems ■ computers, printers and MCU Boards Figure 2. D1 100 Ω A1 The EMIF03-SIM04F3 Flip Chip is a low capacitance EMI filter designed to suppress EMI/RFI noise in all systems subjected to electromagnetic interference. C3 R3 A2 GND D3 B3 R2 100 Ω C1 D2 A3 R1 47 Ω B1 Description Configuration C2 GND A2 and C2 bumps must be connected together on the PCB This filter includes ESD protection circuitry, which prevents damage to the protected device when subjected to ESD surges up to 15 kV. TM: IPAD is a trademark of STMicroelectronics. October 2010 Doc ID 17053 Rev 2 1/7 www.st.com 7 Electrical characteristics 1 EMIF03-SIM04F3 Electrical characteristics Table 1. Absolute maximum ratings (Tamb = 25 °C) Symbol Parameter Value Unit Internal pins (A1, B1, C1): ESD discharge IEC 61000-4-2, level 1, air discharge ESD discharge IEC 61000-4-2, level 1, contact discharge External pins (A3, B3, C3, D1, D2 and D3): ESD discharge IEC 61000-4-2, level 4, air discharge ESD discharge IEC 61000-4-2, level 4, contact discharge ±15 ±15 Pd Line resistance power dissipation at 70 °C 60 mW Top Operating temperature range - 40 to + 85 °C Tstg Storage temperature range - 55 to 150 °C VPP Figure 3. ±2 ±2 kV Electrical characteristics (definitions) I Symbol VBR = IRM = Parameter Breakdown voltage Leakage current @ VRM RI/O = Series resistance between input and output Line capacitance Cline = Table 2. VBR VRM IRM IR V VRM VBR Electrical characteristics (Tamb = 25 °C) Symbol Test conditions VBR IR = 1 mA IRM VRM = 3 V per line Min. Typ. Max. 6 Unit V 50 200 nA R1, R3 Tolerance ± 20% 80 100 120 Ω R2 Tolerance ± 20% 37.6 47 56.4 Ω 8 10 12 pF Cline Vline = 0 V, Vosc = 30 mV, F = 1 MHz (measured under zero light conditions)(1) 1. A2 and C2 bumps must be connected together on the printed circuit board 2/7 IR IRM Doc ID 17053 Rev 2 EMIF03-SIM04F3 Figure 4. 0.00 Electrical characteristics S21 (dB) attenuation measurement Figure 5. B3 - B1 S21 (dB) S21 (dB) analog crosstalk measurements C3 - A1 0.00 -10.00 -20.00 - --20.00 -40.00 - --30.00 -60.00 - --40.00 -80.00 - F (Hz) F (Hz) --50.00 100.0k Figure 6. 1.0M 10.0M 100.0M -100.00 100.0k 1.0G ESD response to IEC 61000-4-2 (+15 kV air discharge) on one line 100 ns/dIV 20 V/Div S21 (dB) Figure 7. C2 1.0M 10.0M 100.0M 1.0G ESD response to IEC 61000-4-2 (-15 kV air discharge) on one line 10 V/Div IN IN C2 100 ns/Div C3 10 V/Div OUT OUT C3 100 ns/dIV Figure 8. 10 V/Div 100 ns/Div Digital crosstalk measurement 1 V/Div IN C2 20 ns/Div 500 mV/Div OUT C3 20 ns/Div Doc ID 17053 Rev 2 3/7 Ordering information scheme 2 EMIF03-SIM04F3 Ordering information scheme Figure 9. Ordering information scheme EMIF EMI filter Number of lines Information x = resistance value (Ohms) z = capacitance value / 10(pF) or 3 letters = application 2 digits = version Package F = Flip chip x = 3: Lead-free, pitch = 400 µm 4/7 Doc ID 17053 Rev 2 yy - xxx zz Fx EMIF03-SIM04F3 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 10. Package dimensions 400 µm ± 30 255 µm ± 40 605 µm ± 55 1.14 mm ± 30 µm 400 µm ± 30 170 µm 1.54 mm ± 30 µm 170 µm Figure 11. Footprint Figure 12. Marking Copper pad Diameter: 220 µm recommended 260 µm maximum Dot, ST logo ECOPACK® Grade Solder mask opening: 300 µm minimum xx = marking z = manufacturing location yww = datecode (y = year ww = week) Solder stencil opening: 220 µm recommended x x z y ww Figure 13. Flip-Chip tape and reel specification Dot identifying pin A1 location 2.0 ± 0.05 Ø 1.5 ± 0.1 xxz yww STE xxz yww STE xxz yww 1.68 3.5 ±- 0.1 1.75 ± 0.1 4.0 ± 0.1 STE 8.0 ± 0.3 3 Package information 1.31 4.0 ± 0.1 0.69 ± 0.05 All dimensions in mm User direction of unreeling Doc ID 17053 Rev 2 5/7 Ordering information 4 EMIF03-SIM04F3 Ordering information Table 3. Ordering information Order code Marking Package Weight Base qty Delivery mode EMIF03-SIM04F3 JI Flip Chip 1.74 mg 5000 Tape and reel 7” Note: More information is available in the application notes: AN2348: “STMicroelectronics 400 micro-metre Flip Chip: package description and recommendation for use” AN1751: “EMI filters: recommendations and measurements” 5 Revision history Table 4. 6/7 Document revision history Date Revision Changes 03-May-2010 1 Initial release. 12-Oct-2010 2 Updated value IRM in Table 2. Doc ID 17053 Rev 2 EMIF03-SIM04F3 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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