STMICROELECTRONICS EMIF02

EMIF02-USB01F2
2-line IPAD™, EMI filter including ESD protection
Features
■
2-line low-pass filter + ESD protection
■
High efficiency in EMI filtering
■
Lead-free package
■
Very low PCB space occupation: < 2.5 mm2
■
Very thin package: 0.65 mm
■
High efficiency in ESD suppression
(IEC61000-4-2 level 4)
■
High reliability offered by monolithic integration
■
High reduction of parasitic elements through
integration and wafer level packaging
Flip Chip
(8 bumps)
Figure 1.
Pin configuration (bump side
view)
3
2
Pup
1
Vbus
Complies with the following standards
B
DZ
■
IEC 61000-4-2 level 4
– 15 kV (air discharge)
– 8 kV (contact discharge)
D+
out
D+
in
C
D
GND
Din
A
Dout
E
Application
ESD protection and EMI filtering for:
■
Figure 2.
Schematic
USB port
Pup
Vbus
Description
33
DZ
The EMIF02-USB01F2 is a highly integrated array
designed to suppress EMI / RFI noise for USB
port filtering. The EMIF02-USB01F2 Flip Chip
packaging means the package size is equal to the
die size.
Additionally, this filter includes ESD protection
circuitry which prevents damage to the protected
device when subjected to ESD surges up to
15 kV.
April 2008
1.3K
D+ in
D+ out
GND
33
D- out
D- in
TM: IPAD is a trademark of STMicroelectronics.
Rev 3
1/8
www.st.com
8
Electrical characteristics
1
EMIF02-USB01F2
Electrical characteristics
Table 1.
Absolute ratings (Tamb = 25 °C)
Symbol
Tj
Parameter
Unit
125
°C
junction temperature
Top
Operating temperature range
-40 to +85
°C
Tstg
Storage temperature range
-55 to 150
°C
Table 2.
Electrical characteristics (Tamb = 25 °C)
Symbol
Parameters
VBR
Breakdown voltage
IRM
Leakage current @ VRM
VRM
Stand-off voltage
VCL
Clamping voltage
Rd
Dynamic impedance
IPP
Peak pulse current
RI/O
Series resistance between input and
output
Cline
Input capacitance per line
Symbol
2/8
Value
Test conditions
slope: 1/Rd
Min
Typ
Max
Unit
VBR
IR = 1 mA
IRM
VRM = 3 V
Cline
@0V
40
R1, R2
Tolerance ± 5 %
33
Ω
R3
Tolerance ± 5 %
1.30
kΩ
6
V
0.5
µA
45
pF
EMIF02-USB01F2
Figure 3.
Electrical characteristics
S21 (dB) attenuation measurement Figure 4.
Analog crosstalk measurements
0.00
dB
-10.00
EMIF02-USB01: filtering response of lines C1/C3 and E1/E3
0.00
dB
-5.00
-20.00
-10.00
-30.00
-15.00
-40.00
-20.00
-50.00
-25.00
-60.00
-30.00
-70.00
-35.00
-40.00
-80.00
-45.00
-90.00
-100.0
-50.00
1.0M
E1_E3
Figure 5.
3.0M
10.0M
30.0M
100.0M
300.0M
1.0G
3.0G
1.0M
3.0M
10.0M
C1_C3
Frequency/Hz
100.0M
300.0M
1.0G
3.0G
f/Hz
ESD response to IEC61000-4-2
(+15 kV air discharge) on one input
V(in) and on one output (Vout)
Figure 6.
ESD response to IEC61000-4-2
(-15 kV air discharge) on one input
V(in) and on one output (Vout)
Vin : 10V/d
Vin : 5V/d
Vout : 10V/d
Vout : 5V/d
100ns/d
100ns/d
Figure 7.
30.0M
Capacitance versus reverse applied voltage (typical)
C(pF)
40
35
30
25
20
15
VR(V)
10
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
3/8
Application information
2
EMIF02-USB01F2
Application information
Figure 8.
Aplac model (resistors, diodes and bumps and ground connections)
R_1k3
3.8nH
A1, A3, B2, C1, C3, E1, E3
A3
C1
Csub
Csub
rsub_1k3
D2
Cbump Rsubump
I/O
bulk
0.15nH
rsub_1k3
Lbump
D02_usb
100m
D2
bulk
Rbump
bulk
0.15nH
cap_33R
R_33R
0.23nH
C3
Csub
rsub_33R
Csub
rsub_33R
D02_Nw
D02_usb
Rhole
Lgnd_D
Rsub_D
D2
bulk
bulk
0.3nH
R_33R
0.7nH
E1
E3
cap_33R
Csub
rsub_33R
Csub
rsub_33R
cap_33R
bulk
Figure 9.
Aplac model parameters
R_33R 33.9
cap_33R 1.2pF
R_1k3 1.3k
Cz29pF
Rsub_D 100
Csub0.3pF
Rsub_33R 15
Rsub_1k3 50
lhole10pH
Rhole400m
Caphole0.4pF
Lgnd_D 150pH
Lbump50pH
Rbump50m
Cbump1.5pF
Rsubump150
4/8
Lhole
caphole
cap_33R
Model D02_Nw
BV=100
IBV=1m
CJO=6.8p
M=0.3333
RS=2
VJ=0.6
TT=100n
Model D02_usb
BV=16
IBV=1m
CJO=Cz
M=0.3333
RS=2
VJ=0.6
TT=100n
EMIF02-USB01F2
3
Ordering information scheme
Ordering information scheme
Figure 10. Ordering information scheme
EMIF
yy
-
xxx zz
Fx
EMI Filter
Number of lines
Information
x = resistance value (Ohms)
z = capacitance value / 10(pF)
or
3 letters = application
2 digits = version
Package
F = Flip Chip
X = 2: Lead-free, pitch = 500 µm, bump = 315 µm
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the inner box label, in compliance with JEDEC
Standard JESD97. The maximum ratings related to soldering conditions are also marked on
the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at
www.st.com.
Figure 11. Package dimensions
700 ± 50
315 ± 50
650µm ± 65
µm
5
49
±
5µ
m
±
50
1.97mm ± 50µm
50
1.27mm ± 50µm
285 µm
285µm
49
4
5/8
Ordering information
EMIF02-USB01F2
Figure 12. Footprint
Figure 13. Marking
Dot, ST logo
xx = marking
z = manufacturing location
yww = datecode
(y = year
ww = week)
Copper pad Diameter:
250 µm recommended, 300 µm max
Solder stencil opening: 330 µm
E
x x z
y ww
Solder mask opening recommendation:
340 µm min for 315 µm copper pad diameter
Figure 14. Flip Chip tape and reel specification
Dot identifying Pin A1 location
3.5 ± 0.1
xxz
yww
ST E
6/8
1.37
User direction of unreeling
Ordering information
Table 3.
Note:
xxz
yww
4 ± 0.1
All dimensions in mm
5
ST E
xxz
yww
ST E
8 ± 0.3
2.07
0.73 ± 0.05
1.75 ± 0.1
Ø 1.5 ± 0.1
4 ± 0.1
Ordering information
Order code
Marking
Package
Weight
Base qty
Delivery mode
EMIF02-USB01F2
FF
Flip Chip
3.35 mg
5000
Tape and reel 7”
More information is available in the application notes:
AN1235:"Flip Chip: Package description and recommendations for use"
AN1751: “EMI filters: Recommendations and measurements”
EMIF02-USB01F2
6
Revision history
Revision history
Table 4.
Document revision history
Date
Revision
Changes
26-Oct-2004
1
Initial release.
16-Apr-2007
2
Updated ECOPACK statement. Updated Figure 10, Figure 11 and
Figure 14. Reformatted to current standards.
29-Apr-2008
3
Typographical errors corrected.
7/8
EMIF02-USB01F2
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