STMICROELECTRONICS EMIF02

EMIF02-MIC06F3
2-line IPAD™ EMI filter and ESD protection
Features
■
2-line symmetrical low-pass filter
■
Lead-free package
■
Very low PCB space consuming: < 1.5 mm2
■
Very thin package: 0.65 mm
■
High efficiency in ESD suppression
IEC 61000-4-2 level 4
■
High reliability offered by monolithic integration
■
High reduction of parasitic elements through
integration and wafer level packaging
Lead-free Flip-Chip package
(8 bumps)
Figure 1.
Pin configuration (bump side)
Complies with the following standards
■
IEC 61000-4-2 level 4:
– 15 kV (air discharge)
– 8 kV (contact discharge)
Application
■
Mobile phones (differential microphone filtering
and ESD protection)
3
2
1
MIC
Bias
ECI
Op
n
Gnd
Mic2p
B
On
A
Gnd
Mic2n
C
A
Description
The EMIF02-MIC06F3 is a highly integrated
device designed to suppress EMI/RFI noise for
dual microphone line filtering.
The EMIF02-MIC06F3 Flip-Chip packaging
means the package size is equal to the die size.
That's why EMIF02-MIC06F3 is a very small
device.
Additionally, this filter includes an ESD protection
circuitry which prevents damage to the application
when subjected to ESD surges up to 15 kV.
TM: IPAD is a trademark of STMicroelectronics.
September 2011
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www.st.com
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Characteristics
1
EMIF02-MIC06F3
Characteristics
Figure 2.
Configuration
ECI
A2
GND
GND
Mic Bias
A3
C11
B1
GND
C21
R11
R31
R21
B3
Mic2p
to ASIC
Mic2n
R22
C1
C12
GND
GND
C3
R12
GND
C22
GND
B2 and C2 are ground pins
ECI pin connection
The ECI pin (enhancement control interface) is an input pin for the audio pre-amplifier chip
which detects the voltage of the microphone line MIC2P in case the user presses the onhook/off-hook button on the headset. When the user selects off-hook using the headset
button, the MIC2P is shorted to MIC2N which is grounded. If your design does not support
the ECI feature, the ECI pin must be left open (not connected).
Table 1.
Symbol
VPP
2/8
Absolute ratings (limiting values)
Parameter and test conditions
Pins B1 and C1:
ESD discharge IEC 61000-4-2, level 4
air discharge
contact discharge
Pins A2, A3, B2, B3, C2, C3:
ESD discharge IEC 61000-4-2, level 1
air discharge
contact discharge
Value
15
8
Unit
kV
2
2
PD
Power dissipation at Tamb = 25 °C
60
mW
Tj
Maximum junction temperature
125
°C
Top
Operating temperature range
- 40 to + 85
°C
Tstg
Storage temperature range
- 55 to + 150
°C
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EMIF02-MIC06F3
Figure 3.
Characteristics
Electrical characteristics (definitions)
I
Symbol
VBR =
IRM =
Parameter
Breakdown voltage
Leakage current @ VRM
RI/O =
Series resistance
between input and output
Line capacitance
Cline =
Table 2.
IR
IRM
IRM
IR
VRM VBR
V
Electrical characteristics - values (Tamb = 25 °C)
Symbol
Test conditions
VBR
IR = 1 mA
IRM
VRM = 3 V per line
Min.
Typ.
Max.
Unit
14
V
100
nA
R11
1.9
2
2.1
kΩ
R12
0.8
1
1.2
kΩ
R21, R22
1.76
2.2
2.64
kΩ
R31
20
25
30
Ω
0.8
1
nF
C11, C12
VR = 0 V
C21, C22
VR = 0 V
Figure 4.
0
VBR VRM
1
Attenuation simulation with
1 kΩ input and 10 kΩ output
Figure 5.
db
0.00
1.25
nF
Analog crosstalk measurement
db
-10.00
-10
-20.00
-20
-30.00
-30
50Ω measurements
-40.00
-40
-50.00
-50
Input: 1 k Ω
Output: 10 kΩ
AC simulation
-60
-70
-60.00
50Ω simulations
-70.00
-80.00
-80
-90.00
-90
F (Hz)
F (Hz)
-100.00
-100
10
100
1k
10k
100k
1M
10M
100M
1G
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100.0k
1.0M
Mic2p-On
10.0M
100.0M
Mic2n-Op
1.0G
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Characteristics
Figure 6.
EMIF02-MIC06F3
ESD response to IEC 61000-4-2
(+15 kV air discharge) on Mic2p
Figure 7.
ESD response to IEC 61000-4-2
(-15 kV air discharge) on Mic2p
10 V/div
10 V/div
Input
Input
5 V/div
5 V/div
Output
Output
500 ns/div
500 ns/div
Figure 8.
ESD response to IEC 61000-4-2
(+15 kV air discharge) on Mic2n
Figure 9.
ESD response to IEC 61000-4-2
(-15 kV air discharge) on Mic2n
10 V/div
10 V/div
Input
Input
2 V/div
2 V/div
Output
Output
200 ns/div
200 ns/div
Figure 10. Line capacitance versus applied voltage
CLINE (pF)
1 200.00
1 000.00
800.00
F = 1 Mhz
VOSC = 30 mV rms
Tj = 25 °C
600.00
400.00
200.00
VLINE (V)
0.00
0
4/8
0.5
1
1.5
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2.5
3
EMIF02-MIC06F3
2
Ordering information scheme
Ordering information scheme
Figure 11. Ordering information scheme
EMIF
yy
-
xxx zz
Fx
EMI filter
Number of lines
Information
x = resistance value (Ohms)
z = capacitance value / 10(pF)
or
3 letters = application
2 digits = version
Package
F = Flip Chip
x = 3: lead-free, pitch = 400 µm
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 12. Flip Chip package dimensions
400 µm ± 40
605 µm ± 55
255 µm ± 40
1.20 mm ± 30 µm
400 µm ± 40
200 µm
1.20 mm ± 30 µm
200 µm
3
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Ordering information
EMIF02-MIC06F3
Figure 13. Footprint recommendations
Figure 14. Marking
Dot, ST logo
ECOPACK status
xx = marking
z = manufacturing location
yww = datecode
(y = year
Copper pad Diameter:
220µm recommended
260µm maximum
Solder mask opening:
300µm minimum
x x z
y ww
Solder stencil opening :
220µm recommended
Figure 15. Flip Chip tape and reel specification
Dot identifying Pin A1 location
2.0
Ø 1.55
4.0
xxz
yww
ST
xxz
yww
ST
xxz
yww
ST
8.0
3.5
1.30
1.75
0.22
4.0
1.30
0.69
All dimensions are typical values in mm
4
Ordering information
Table 3.
Note:
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User direction of unreeling
Ordering information
Order code
Marking
Package
Weight
Base qty
Delivery mode
EMIF02-MIC06F3
JB
Flip Chip
1.8 mg
5000
Tape and reel 7”
More information is available in the application notes
AN2348: “Flip Chip: Package description and recommendations for use”
AN1751: “EMI Filters: Recommendations and measurements”
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EMIF02-MIC06F3
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Revision history
Revision history
Table 4.
Document revision history
Date
Revision
Changes
21-Nov-2008
1
Initial release
05-Mar-2009
2
Updated Figure 4 and Figure 12.
07-Apr-2010
3
Updated tolerance Figure 12.
23-Sep-2011
4
Added ECI pin connection on page 2.
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EMIF02-MIC06F3
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