CY7C1380CV25 CY7C1382CV25 18-Mbit (512K x 36/1M x 18) Pipelined SRAM Functional Description[1] Features • Supports bus operation up to 250 MHz • Available speed grades are 250, 225, 200,166 and 133 MHz • Registered inputs and outputs for pipelined operation • 2.5V core power supply • Fast clock-to-output times — 2.6 ns (for 250-MHz device) — 2.8 ns (for 225-MHz device) — 3.0 ns (for 200-MHz device) — 3.4 ns (for 166-MHz device) — 4.2 ns (for 133-MHz device) • Provide high-performance 3-1-1-1 access rate • User-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences • Separate processor and controller address strobes • Synchronous self-timed writes • Asynchronous output enable • Single Cycle Chip Deselect • Offered in JEDEC-standard 100-pin TQFP, 119-ball BGA and 165-Ball fBGA packages • IEEE 1149.1 JTAG-Compatible Boundary Scan • “ZZ” Sleep Mode Option The CY7C1380CV25/CY7C1382CV25 SRAM integrates 524,288 x 36 and 1,048,576 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depthexpansion Chip Enables (CE2 and CE3 [2]), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWX, and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle.This part supports Byte Write operations (see Pin Descriptions and Truth Table for further details). Write cycles can be one to two or four bytes wide as controlled by the byte write control inputs. GW when active LOW causes all bytes to be written. The CY7C1380CV25/CY7C1382CV25 operates from a +2.5V core power supply. All outputs also operate with a +2.5 supply. All inputs and outputs are JEDEC-standard JESD8-5compatible. Selection Guide 250 MHz 225 MHz 200 MHz 167 MHz 133 MHz Unit Maximum Access Time 2.6 2.8 3.0 3.4 4.2 ns Maximum Operating Current 350 325 300 275 245 mA Maximum CMOS Standby Current 70 70 70 70 70 mA Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. Notes: 1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com. 2. CE3, CE2 are for TQFP and 165 fBGA package only. 119 BGA is offered only in 1 Chip Enable. Cypress Semiconductor Corporation Document #: 38-05240 Rev. *C • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised May 11, 2004 CY7C1380CV25 CY7C1382CV25 1 Logic Block Diagram – CY7C1380CV25 (512K x 36) A0, A1, A ADDRESS REGISTER 2 A[1:0] MODE ADV CLK Q1 BURST COUNTER CLR AND Q0 LOGIC ADSC ADSP BWD DQD ,DQPD BYTE WRITE REGISTER DQD ,DQPD BYTE WRITE DRIVER BWC DQC ,DQPC BYTE WRITE REGISTER DQC ,DQPC BYTE WRITE DRIVER DQB ,DQPB BYTE WRITE REGISTER DQB ,DQPB BYTE WRITE DRIVER BWB BWA BWE GW CE1 CE2 CE3 OE ZZ SENSE AMPS OUTPUT REGISTERS OUTPUT BUFFERS E DQs DQPA DQPB DQPC DQPD DQA ,DQPA BYTE WRITE DRIVER DQA ,DQPA BYTE WRITE REGISTER ENABLE REGISTER MEMORY ARRAY INPUT REGISTERS PIPELINED ENABLE SLEEP CONTROL 2 Logic Block Diagram – CY7C1382CV25 (1M x 18) A0, A1, A ADDRESS REGISTER 2 A[1:0] MODE BURST Q1 COUNTER AND LOGIC CLR Q0 ADV CLK ADSC ADSP BWB DQB,DQPB WRITE DRIVER DQB,DQPB WRITE REGISTER MEMORY ARRAY BWA DQA,DQPA WRITE DRIVER DQA,DQPA WRITE REGISTER SENSE AMPS OUTPUT REGISTERS OUTPUT BUFFERS DQs DQPA DQPB E BWE GW CE1 CE2 CE3 ENABLE REGISTER PIPELINED ENABLE INPUT REGISTERS OE ZZ SLEEP CONTROL 3 Document #: 38-05240 Rev. *C Page 2 of 33 CY7C1380CV25 CY7C1382CV25 Pin Configurations NC NC NC CY7C1382CV25 (1M x 18) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 Document #: 38-05240 Rev. *C A NC NC VDDQ VSSQ NC DQPA DQA DQA VSSQ VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA NC NC VSSQ VDDQ NC NC NC A A A A A A A A A A 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VDDQ VSSQ NC NC DQB DQB VSSQ VDDQ DQB DQB NC VDD NC VSS DQB DQB VDDQ VSSQ DQB DQB DQPB NC VSSQ VDDQ NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 MODE A A A A A1 A0 NC / 72M NC / 36M VSS VDD DQPB DQB DQB VDDQ VSSQ DQB DQB DQB DQB VSSQ VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA DQA DQA VSSQ VDDQ DQA DQA DQPA 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 CY7C1380CV25 (512K X 36) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 MODE A A A A A1 A0 NC / 72M NC / 36M VSS VDD A A A A A A A A DQPC DQC DQc VDDQ VSSQ DQC DQC DQC DQC VSSQ VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD DQPD A A CE1 CE2 NC NC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A A A CE1 CE2 BWD BWC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A 100-pin TQFP Pinout Page 3 of 33 CY7C1380CV25 CY7C1382CV25 Pin Configurations (continued) 119-ball BGA (1 Chip Enable with JTAG) 1 CY7C1380CV25 (512K x 36) 3 4 5 A A ADSP A VDDQ 2 A B C NC NC A A A A ADSC VDD A A A A NC NC D E DQC DQC DQPC DQC VSS VSS NC CE1 VSS VSS DQPB DQB DQB DQB F VDDQ DQC VSS OE VSS DQB VDDQ G H J K DQC DQC VDDQ DQD DQC DQC VDD DQD BWC VSS NC VSS ADV BWB VSS NC VSS DQB DQB VDD DQA DQB DQB VDDQ DQA BWA VSS DQA DQA DQA VDDQ VSS DQA DQA GW VDD CLK NC 6 A 7 VDDQ L DQD DQD M VDDQ DQD BWD VSS N DQD DQD VSS BWE A1 P DQD DQPD VSS A0 VSS DQPA DQA R NC A MODE VDD NC A NC T U NC VDDQ NC / 72M TMS A TDI A TCK A TDO NC / 36M NC ZZ VDDQ 3 4 5 6 7 A ADSP A A VDDQ ADSC VDD A A NC A A NC CY7C1382CV25 (1M x 18) 1 2 A VDDQ A B NC A A C NC A A D DQB NC VSS NC VSS DQPA NC E NC DQB VSS CE1 VSS NC DQA OE ADV VSS DQA VDDQ GW VDD VSS VSS NC NC DQA VDD DQA NC VDDQ CLK VSS NC DQA NC BWA VSS DQA NC NC VDDQ F VDDQ NC VSS G H J NC DQB VDDQ DQB NC VDD BWB VSS NC K NC DQB VSS L M DQB VDDQ NC DQB VSS VSS N DQB NC VSS BWE A1 VSS DQA NC P NC DQPB VSS A0 VSS NC DQA R T U NC NC / 72M VDDQ A A TMS MODE A TDI VDD NC / 36M TCK NC A TDO A A NC NC ZZ VDDQ Document #: 38-05240 Rev. *C Page 4 of 33 CY7C1380CV25 CY7C1382CV25 Pin Configurations (continued) 165-ball fBGA CY7C1380CV25 (512K x 36) 1 A B C D E F G H J K L M N P NC / 288M R 2 A 3 4 5 6 7 8 9 10 11 CE1 BWC BWB CE3 BWE ADSC ADV A NC NC A CE2 BWD BWA CLK GW A NC / 144M NC DQC VDDQ VSS VSS VSS VSS VSS VSS VDDQ VDDQ VSS VDD OE VSS VDD ADSP DQPC DQC VDDQ NC DQB DQPB DQB DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB DQC DQC NC DQD DQC VDDQ VDD VSS VSS VSS VDD DQB DQB DQC VSS DQD VDDQ NC VDDQ VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDDQ VDDQ NC VDDQ DQB NC DQA DQB ZZ DQA DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA DQD DQPD DQD NC VDDQ VDDQ VDD VSS VSS NC VSS A VSS NC VDD VSS VDDQ VDDQ DQA NC DQA DQPA NC NC / 72M A A TDI A1 TDO A A A A MODE NC / 36M A A TMS TCK A A A A 7 8 9 10 11 A A0 CY7C1382CV25 (1M x 18) 1 2 A B C D E F G H J K L M N P NC / 288M A 3 4 5 6 NC CE3 A CE1 CE2 BWB NC NC BWA NC NC NC DQB VDDQ VSS VDD VSS VDDQ R CLK BWE GW ADSC OE ADV ADSP A VSS VSS VSS VSS VSS VDD VDDQ VSS VDDQ NC NC A NC / 144M DQPA DQA NC DQB VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA NC DQB VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA NC NC DQB DQB VSS NC VDDQ NC VDDQ VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDDQ NC VDDQ NC NC DQA DQA ZZ NC DQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC DQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC DQB DQPB NC NC VDDQ VDDQ VDD VSS VSS NC VSS A VSS NC VDD VSS VDDQ VDDQ DQA NC NC NC NC NC / 72M A A TDI A1 TDO A A A A MODE NC / 36M A A TMS A0 TCK A A A A Document #: 38-05240 Rev. *C Page 5 of 33 CY7C1380CV25 CY7C1382CV25 CY7C1380CV25–Pin Definitions Name TQFP BGA fBGA I/O Description InputAddress Inputs used to select one of the R6,P6,A2, P4,N4, Synchronous address locations. Sampled at the rising edge A10,B2, A2,B2, of the CLK if ADSP or ADSC is active LOW, and B10,N6,P3,P4, C2,R2, P8,P9,P10, A3,B3,C3, CE1, CE2, and CE3 [2]are sampled active. A1: A0 P11,R3,R4,R8, T3,T4,A5,B5, are fed to the two-bit counter.. R9,R10,R11 C5, T5,A6,B6,C6,R6 A0, A1, A 37,36,32, 33,34,35, 42,43,44,45, 46,47,48, 49,50,81, 82,99,100 BWA,BWB 93,94,95, 96 L5,G5, G3,L3 B5,A5,A4, B4 GW 88 H4 B7 BWE 87 M4 A7 CLK 89 K4 B6 98 E4 A3 InputChip Enable 1 Input, active LOW. Sampled on Synchronous the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE2[2] 97 - B3 InputChip Enable 2 Input, active HIGH. Sampled on Synchronous the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. CE3[2] 92 - A6 OE 86 F4 B8 InputChip Enable 3 Input, active LOW. Sampled on Synchronous the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device.Not available for AJ package version.Not connected for BGA. Where referenced, CE3 is assumed active throughout this document for BGA. InputOutput Enable, asynchronous input, active Asynchronous LOW. Controls the direction of the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. ADV 83 G4 A9 InputAdvance Input signal, sampled on the rising Synchronous edge of CLK, active LOW. When asserted, it automatically increments the address in a burst cycle. 84 A4 B9 InputAddress Strobe from Processor, sampled on Synchronous the rising edge of CLK, active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. BWC,BWD CE1 ADSP Document #: 38-05240 Rev. *C InputByte Write Select Inputs, active LOW. Synchronous Qualified with BWE to conduct byte writes to the SRAM. Sampled on the rising edge of CLK. InputGlobal Write Enable Input, active LOW. When Synchronous asserted LOW on the rising edge of CLK, a global write is conducted (ALL bytes are written, regardless of the values on BWX and BWE). InputByte Write Enable Input, active LOW. Synchronous Sampled on the rising edge of CLK. This signal must be asserted LOW to conduct a byte write. InputClock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. Page 6 of 33 CY7C1380CV25 CY7C1382CV25 CY7C1380CV25–Pin Definitions (continued) Name TQFP BGA fBGA ADSC 85 B4 A8 InputAddress Strobe from Controller, sampled on Synchronous the rising edge of CLK, active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ZZ 64 T7 H11 InputZZ “sleep” Input, active HIGH. When asserted Asynchronous HIGH places the device in a non-time-critical “sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down. 52,53,56, 57,58,59, 62,63,68, 69,72,73, 74,75,78, 79,2,3,6,7,8,9, 12,13,18,19,22 , 23,24,25, 28,29,51, 80,1,30 K6,L6, M6,N6, K7,L7, N7,P7, E6,F6, G6,H6, D7,E7, G7,H7, D1,E1, G1,H1, E2,F2, G2,H2, K1,L1, N1,P1, K2,L2, M2,N2, P6,D6, D2,P2 M11,L11, K11,J11, J10,K10, L10,M10, D10,E10, F10,G10, D11,E11, F11,G11, D1,E1,F1, G1,D2,E2,F2, G2,J1, K1,L1,M1, J2,K2,L2, M2,N11, C11,C1,N1 I/OBidirectional Data I/O lines. As inputs, they Synchronous feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX are placed in a three-state condition. VDD 15,41,65, 91 J2,C4,J4,R4, J6 VSS 17,40,67, 90 D3,E3, F3,H3, K3,M3, N3,P3, D5,E5, F5,H5, K5,M5, N5,P5 C4,C5,C6,C7, C8,D5,D6,D7, E5,E6,E7,F5, F6,F7,G5,G6, G7,H2,H5,H6, H7,J5,J6,J7, K5,K6,K7, L5,L6,L7, M5,M6,M7,N4, N8 Ground 5,10,21,26,55, 60,71, 76 - - I/O Ground DQs, DQPs VSSQ Document #: 38-05240 Rev. *C I/O Description D4,D8,E4,E8, Power Supply Power supply inputs to the core of the device. F4,F8, G4,G8,H4,H8, J4,J8, K4,K8,L4, L8,M4,M8 Ground for the core of the device. Ground for the I/O circuitry. Page 7 of 33 CY7C1380CV25 CY7C1382CV25 CY7C1380CV25–Pin Definitions (continued) Name TQFP BGA fBGA I/O I/O Power Supply Description Power supply for the I/O circuitry. VDDQ 4,11,20,27,54, 61,70, 77 MODE 31 R3 R1 InputStatic Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. Mode Pin has an internal pull-up. TDO - U5 P7 JTAG serial output Synchronous Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG feature is not being utilized, this pin should be disconnected. This pin is not available on TQFP packages. TDI - U3 P5 JTAG serial Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not input Synchronous being utilized, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages. TMS - U2 R5 JTAG serial Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not input Synchronous being utilized, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages. TCK - U4 R7 JTAG-Clock Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must be connected to VSS. This pin is not available on TQFP packages. NC 14,16,66, 39,38 B1,C1, R1,T1,T2,J3, D4, L4,J5,R5,6T, 6U, B7,C7, R7 A11,B1,C2, C10,H1,H3,H9 ,H10, N2,N5,N7,N10 ,P1,A1,B11,P2 ,R2,N6 A1,F1,J1,M1,U1, C3,C9,D3,D9, A7,F7,J7,M7,U7 E3,E9,F3,F9,G 3, G9,J3,J9, K3,K9,L3, L9,M3,M9,N3, N9 - No Connects. Not internally connected to the die CY7C1382CV25–Pin Definitions Name TQFP BGA A0, A1, A 37,36,32, 33,34,35, 42,43,44, 45,46,47, 48,49,50, 80,81,82, 99,100 P4,N4, A2,B2, C2,R2, T2,A3, B3,C3, T3,A5, B5,C5, T5,A6, B6,C6, R6,T6 BWA,BWB 93,94 G3,L5 Document #: 38-05240 Rev. *C fBGA I/O Description InputAddress Inputs used to select one of the R6,P6,A2, Synchronous address locations. Sampled at the rising A10,A11, edge of the CLK if ADSP or ADSC is active B2,B10,P3,P4,N6,P 8,P9, LOW, and CE1, CE2, and CE3 are sampled P10,P11, active. A1: A0 are fed to the two-bit counter.. R3,R4,R8,R9,R10, R11 B5,A4 InputByte Write Select Inputs, active LOW. Synchronous Qualified with BWE to conduct byte writes to the SRAM. Sampled on the rising edge of CLK. Page 8 of 33 CY7C1380CV25 CY7C1382CV25 CY7C1382CV25–Pin Definitions (continued) Name TQFP BGA fBGA GW 88 H4 B7 InputGlobal Write Enable Input, active LOW. Synchronous When asserted LOW on the rising edge of CLK, a global write is conducted (ALL bytes are written, regardless of the values on BWX and BWE). BWE 87 M4 A7 InputByte Write Enable Input, active LOW. Synchronous Sampled on the rising edge of CLK. This signal must be asserted LOW to conduct a byte write. CLK 89 K4 B6 98 E4 A3 InputChip Enable 1 Input, active LOW. Sampled Synchronous on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE2[2] 97 - B3 InputChip Enable 2 Input, active HIGH. Sampled Synchronous on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. CE3 [2] 92 - A6 OE 86 F4 B8 InputChip Enable 3 Input, active LOW. Sampled Synchronous on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device. Not available for AJ package version.Not connected for BGA. Where referenced, CE3 is assumed active throughout this document for BGA. Output Enable, asynchronous input, active InputAsynchronou LOW. Controls the direction of the I/O pins. When LOW, the I/O pins behave as outputs. s When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. ADV 83 G4 A9 InputAdvance Input signal, sampled on the Synchronous rising edge of CLK, active LOW. When asserted, it automatically increments the address in a burst cycle. 84 A4 B9 InputAddress Strobe from Processor, sampled Synchronous on the rising edge of CLK, active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. 85 P4 A8 InputAddress Strobe from Controller, sampled Synchronous on the rising edge of CLK, active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. CE1 ADSP ADSC Document #: 38-05240 Rev. *C I/O InputClock Description Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. Page 9 of 33 CY7C1380CV25 CY7C1382CV25 CY7C1382CV25–Pin Definitions (continued) Name ZZ TQFP BGA fBGA 64 T7 H11 DQs, DQPs 58,59,62, 63,68,69, 72,73,8,9, 12,13,18, 19,22,23, 74,24 VDD 15,41,65, 91 VSS 17,40,67, 90 Description J10,K10, I/OBidirectional Data I/O lines. As inputs, they P7,K7, L10,M10, Synchronous feed into an on-chip data register that is G7,E7, D11,E11, triggered by the rising edge of CLK. As outputs, F6,H6,L6,N6, F11,G11,J1,K1,L1,M they deliver the data contained in the memory D1, 1,D2,E2,F2, location specified by the addresses presented H1,L1, G2,C11,N1 during the previous clock rise of the read cycle. N1,E2, G2,K2, The direction of the pins is controlled by OE. M2,D6, When OE is asserted LOW, the pins behave P2 as outputs. When HIGH, DQs and DQPX are placed in a three-state condition. C4,J2,J4,J6, D4,D8,E4,E8,F4,F8, Power Supply Power supply inputs to the core of the device. R4 G4,G8,H4, H8,J4,J8, K4,K8,L4, L8,M4,M8 H2,C4,C5,C6,C7,C8 D3,D5, E5,E3,F3,F5, ,D5,D6,D7,E5,E6,E7 , G5, F5,F6,F7, H3,H5, G5,G6,G7, K3,K5,L3,M3, H5,H6,H7,J5,J6,J7, M5, K5,K6,K7, N3,N5, L5,L6,L7, P3,P5 M5,M6,M7,N4,N8 VSSQ 5,10,21,26,55, 60,71, 76 VDDQ 4,11,20,27,54, A1,A7,F1,F7, C3,C9,D3,D9,E3,E9 61,70, J1,J7,M1,M7, , 77 U1,U7 F3,F9,G3, G9,J3,J9, K3,K9,L3, L9,M3,M9,N3,N9 MODE I/O InputZZ “sleep” Input, active HIGH. When Asynchronou asserted HIGH places the device in a s non-time-critical “sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down. - - Ground Ground for the core of the device. I/O Ground Ground for the I/O circuitry. I/O Power Supply Power supply for the I/O circuitry. 31 R3 R1 TDO - U5 P7 JTAG serial Serial data-out to the JTAG circuit. Delivers output data on the negative edge of TCK. If the JTAG Synchronous feature is not being utilized, this pin should be left unconnected. This pin is not available on TQFP packages. TDI - U3 P5 JTAG serial Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature input Synchronous is not being utilized, this pin can be left floating or connected to VDD through a pull up resistor. This pin is not available on TQFP packages. Document #: 38-05240 Rev. *C InputStatic Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. Mode Pin has an internal pull-up. Page 10 of 33 CY7C1380CV25 CY7C1382CV25 CY7C1382CV25–Pin Definitions (continued) TQFP BGA fBGA TMS Name - U2 R5 JTAG serial Serial data-In to the JTAG circuit. Sampled input on the rising edge of TCK. If the JTAG feature Synchronous is not being utilized, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages. TCK - U4 R7 JTAG-Clock Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must be connected to VSS. This pin is not available on TQFP packages. NC 1,2,3,6,7, 14,16,25, 28,29,30, 38,39, 51,52,53, 56,57,66, 75,78,79, 95,96 A5,B1,B4, B1,B7, C1,C2,C10,D1,D10, C1,C7, E1,E10,F1, D2,D4, F10,G1, D7,E1, G10,H1,H3,H9,H10, E6,H2, J2,J11, F2,G1, K2, G6,H7, K11,L2,L1,M2,M11, J3,J5,K1, N2,N7,N10, K6,L4,L2,L7, N5, M6, N11,P1,A1, N2,L7,P1,P6, B11, R1, P2,R2 R5,R7, T1,T4,U6 Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (tCO) is 3.0ns (200-MHz device). The CY7C1380CV25/CY7C1382CV25 supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486 processors. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte Write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BWX) inputs. A Global Write Enable (GW) overrides all Byte Write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed Write circuitry. Three synchronous Chip Selects (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. ADSP is ignored if CE1 is HIGH. Single Read Accesses This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2) CE1, CE2, CE3 are all asserted active, and (3) the Write signals (GW, BWE) are all deserted HIGH. ADSP is ignored if Document #: 38-05240 Rev. *C I/O - Description No Connects. Not internally connected to the die. CE1 is HIGH. The address presented to the address inputs (A) is stored into the address advancement logic and the Address Register while being presented to the memory array. The corresponding data is allowed to propagate to the input of the Output Registers. At the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within 3.0 ns (200-MHz device) if OE is active LOW. The only exception occurs when the SRAM is emerging from a deselected state to a selected state, its outputs are always three-stated during the first cycle of the access. After the first cycle of the access, the outputs are controlled by the OE signal. Consecutive single Read cycles are supported. Once the SRAM is deselected at clock rise by the chip select and either ADSP or ADSC signals, its output will three-state immediately. Single Write Accesses Initiated by ADSP This access is initiated when both of the following conditions are satisfied at clock rise: (1) ADSP is asserted LOW, and (2) CE1, CE2, CE3 are all asserted active. The address presented to A is loaded into the address register and the address advancement logic while being delivered to the memory array. The Write signals (GW, BWE, and BWX) and ADV inputs are ignored during this first cycle. ADSP-triggered Write accesses require two clock cycles to complete. If GW is asserted LOW on the second clock rise, the data presented to the DQs inputs is written into the corresponding address location in the memory array. If GW is HIGH, then the Write operation is controlled by BWE and BWX signals. The CY7C1380CV25/CY7C1382CV25 provides Byte Write capability that is described in the Write Cycle Descriptions table. Asserting the Byte Write Enable input (BWE) with the selected Byte Write (BWX) input, will selectively write to only the desired bytes. Bytes not selected during a Byte Write operation will remain unaltered. A synchronous self-timed Page 11 of 33 CY7C1380CV25 CY7C1382CV25 Write mechanism has been provided to simplify the Write operations. processors that follow a linear burst sequence. The burst sequence is user selectable through the MODE input. Because the CY7C1380CV25/CY7C1382CV25 is a common I/O device, the Output Enable (OE) must be deserted HIGH before presenting data to the DQs inputs. Doing so will three-state the output drivers. As a safety precaution, DQs are automatically three-stated whenever a Write cycle is detected, regardless of the state of OE. Sleep Mode Single Write Accesses Initiated by ADSC ADSC Write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deserted HIGH, (3) CE1, CE2, CE3 are all asserted active, and (4) the appropriate combination of the Write inputs (GW, BWE, and BWX) are asserted active to conduct a Write to the desired byte(s). ADSC-triggered Write accesses require a single clock cycle to complete. The address presented to A is loaded into the address register and the address advancement logic while being delivered to the memory array. The ADV input is ignored during this cycle. If a global Write is conducted, the data presented to the DQs is written into the corresponding address location in the memory core. If a Byte Write is conducted, only the selected bytes are written. Bytes not selected during a Byte Write operation will remain unaltered. A synchronous self-timed Write mechanism has been provided to simplify the Write operations. Because the CY7C1380CV25/CY7C1382CV25 is a common I/O device, the Output Enable (OE) must be deserted HIGH before presenting data to the DQs inputs. Doing so will three-state the output drivers. As a safety precaution, DQs are automatically three-stated whenever a Write cycle is detected, regardless of the state of OE. Burst Sequences The CY7C1380CV25/CY7C1382CV25 provides a two-bit wraparound counter, fed by A1: A0, that implements either an interleaved or linear burst sequence. The interleaved burst sequence is designed specifically to support Intel Pentium applications. The linear burst sequence is designed to support The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Asserting ADV LOW at clock rise will automatically increment the burst counter to the next address in the burst sequence. Both Read and Write burst operations are supported. Interleaved Burst Address Table (MODE = Floating or VDD) . First Address A1: A0 Second Address A1: A0 Third Address A1: A0 Fourth Address A1: A0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 Linear Burst Address Table (MODE = GND) First Address A1: A0 Second Address A1: A0 Third Address A1: A0 Fourth Address A1: A0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 ZZ Mode Electrical Characteristics Parameter Description IDDZZ Snooze mode standby current Test Conditions tZZS Device operation to ZZ ZZ > VDD – 0.2V tZZREC ZZ recovery time ZZ < 0.2V tZZI ZZ Active to snooze current This parameter is sampled tRZZI ZZ Inactive to exit snooze current This parameter is sampled Document #: 38-05240 Rev. *C Min. ZZ > VDD – 0.2V Max. Unit 60mA mA 2tCYC ns 2tCYC ns 2tCYC 0 ns ns Page 12 of 33 CY7C1380CV25 CY7C1382CV25 Truth Table[ 3, 4, 5, 6, 7, 8] Operation Add. Used CE1 CE2 CE3 ZZ ADSP Deselect Cycle, Power-down None H X X L X ADSC L ADV X WRITE OE CLK X X L-H DQ three-state Deselect Cycle, Power-down None L L X L L X X X X L-H three-state Deselect Cycle, Power-down None L X H L L X X X X L-H three-state Deselect Cycle, Power-down None L L X L H L X X X L-H three-state Deselect Cycle, Power-down None L X H L H L X X X L-H three-state Snooze Mode, Power-down None X X X H X X X X X X three-state READ Cycle, Begin Burst External L H L L L X X X L L-H Q READ Cycle, Begin Burst External L H L L L X X X H L-H three-state WRITE Cycle, Begin Burst External L H L L H L X L X L-H D READ Cycle, Begin Burst External L H L L H L X H L L-H Q READ Cycle, Begin Burst External L H L L H L X H H L-H three-state READ Cycle, Continue Burst Next X X X L H H L H L L-H Q READ Cycle, Continue Burst Next X X X L H H L H H L-H three-state READ Cycle, Continue Burst Next H X X L X H L H L L-H Q READ Cycle, Continue Burst Next H X X L X H L H H L-H three-state WRITE Cycle, Continue Burst Next X X X L H H L L X L-H D WRITE Cycle, Continue Burst Next H X X L X H L L X L-H D READ Cycle, Suspend Burst Current X X X L H H H H L L-H Q READ Cycle, Suspend Burst Current X X X L H H H H H L-H three-state READ Cycle, Suspend Burst Current H X X L X H H H L L-H Q READ Cycle, Suspend Burst Current H X X L X H H H H L-H three-state WRITE Cycle,Suspend Burst Current X X X L H H H L X L-H D WRITE Cycle,Suspend Burst Current H X X L X H H L X L-H D Truth Table for Read/Write [5] Function (CY7C1380CV25) Read GW H BWE H BWD X BWC X BWB X BWA X Read H L H H H H Write Byte A – (DQA and DQPA) Write Byte B – (DQB and DQPB) H L H H H L H L H H L H Write Bytes B, A H L H H L L Write Byte C – (DQC and DQPC) H L H L H H Write Bytes C, A H L H L H L Write Bytes C, B H L H L L H Notes: 3. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. 4. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW= L. WRITE = H when all Byte write enable signals, BWE, GW = H. 5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 6. CE1, CE2, and CE3 are available only in the TQFP package. BGA package has only 2 chip selects CE1 and CE2. 7. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE is a don't care for the remainder of the write cycle 8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are three-state when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW). Document #: 38-05240 Rev. *C Page 13 of 33 CY7C1380CV25 CY7C1382CV25 Truth Table for Read/Write (continued)[5] Function (CY7C1380CV25) GW H BWE L BWD H BWC L BWB L BWA L Write Byte D – (DQD and DQPD) H L L H H H Write Bytes D, A H L L H H L Write Bytes D, B H L L H L H Write Bytes D, B, A H L L H L L Write Bytes D, C H L L L H H Write Bytes D, C, A H L L L H L Write Bytes D, C, B H L L L L H Write All Bytes H L L L L L Write All Bytes L X X X X X Write Bytes C, B, A Truth Table for Read/Write[5] Function (CY7C1382CV25) Read Read Write Byte A – (DQA and DQPA) Write Byte B – (DQB and DQPB) Write Bytes B, A Write All Bytes Write All Bytes IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1380CV25/CY7C1382CV25 incorporates a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM. Note that the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC-standard 2.5V I/O logic levels. GW H H H H H H L BWB X H H L L L X BWE H L L L L L X TAP Controller State Diagram 1 TEST-LOGIC RESET 0 RUN-TEST/ IDLE 0 1 SELECT DR-SCAN 1 SELECT IR-SCAN 0 1 CAPTURE-IR 0 0 0 SHIFT-IR 1 1 EXIT1-IR 0 0 PAUSE-IR 1 0 1 EXIT2-DR 0 EXIT2-IR 1 1 UPDATE-DR 1 1 0 PAUSE-DR 0 0 1 EXIT1-DR Disabling the JTAG Feature 1 0 1 CAPTURE-DR SHIFT-DR The CY7C1380CV25/CY7C1382CV25 contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW(VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. BWA X H L H L L X 0 UPDATE-IR 1 0 The 0/1 next to each state represents the value of TMS at the rising edge of TCK. Document #: 38-05240 Rev. *C Page 14 of 33 CY7C1380CV25 CY7C1382CV25 Test Access Port (TAP) Test Clock (TCK) The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test MODE SELECT (TMS) The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see Figure . TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See Tap Controller Block Diagram.) Test Data-Out (TDO) The TDO output ball is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See Tap Controller State Diagram.) TAP Controller Block Diagram 0 Bypass Register 2 1 0 TDI Selection Circuitry Instruction Register 31 30 29 . . . 2 1 0 Selection Circuitry TDO Identification Register x . . . . . 2 1 0 Boundary Scan Register TCK TMS TAP CONTROLLER circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the Tap Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board-level serial test data path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all the input and bidirectional balls on the SRAM. The SRAM has a 75-bit-long register. The boundary scan register is loaded with the contents of the RAM I/O ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the I/O ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. TAP Instruction Set Performing a TAP Reset Overview A RESET is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. Eight different instructions are possible with the three bit instruction register. All combinations are listed in the Instruction Codes table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below. At power-up, the TAP is reset internally to ensure that TDO comes up in a High-Z state. TAP Registers The TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. Registers are connected between the TDI and TDO balls and allow data to be scanned into and out of the SRAM test The TAP controller cannot be used to load address data or control signals into the SRAM and cannot preload the I/O Document #: 38-05240 Rev. *C Page 15 of 33 CY7C1380CV25 CY7C1382CV25 buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/PRELOAD; rather, it performs a capture of the I/O ring when these instructions are executed. When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and bidirectional balls is captured in the boundary scan register. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. The user must be aware that the TAP controller clock can only operate at a frequency up to 10 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. EXTEST EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. EXTEST is not implemented in this SRAM TAP controller, and therefore this device is not compliant to 1149.1. The TAP controller does recognize an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. There is one difference between the two instructions. Unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO balls when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this instruction is not implemented, so the device TAP controller is not fully 1149.1 compliant. Document #: 38-05240 Rev. *C To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller’s capture setup plus hold time (tCS plus tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CLK captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO balls. Note that since the PRELOAD part of the command is not implemented, putting the TAP to the Update-DR state while performing a SAMPLE/PRELOAD instruction will have the same effect as the Pause-DR command. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. Page 16 of 33 CY7C1380CV25 CY7C1382CV25 TAP Timing 1 2 Test Clock (TCK) 3 t TH t TMSS t TMSH t TDIS t TDIH t TL 4 5 6 t CYC Test Mode Select (TMS) Test Data-In (TDI) t TDOV t TDOX Test Data-Out (TDO) DON’T CARE UNDEFINED TAP AC Switching Characteristics Over the operating Range[9, 10] Parameter Description Min. Max. Unit Clock tTCYC TCK Clock Cycle Time 100 ns tTF TCK Clock Frequency tTH TCK Clock HIGH time 40 10 MHz ns tTL TCK Clock LOW time 40 ns Output Times tTDOV TCK Clock LOW to TDO Valid tTDOX TCK Clock LOW to TDO Invalid 20 ns 0 ns 10 ns ns Set-up Times tTMSS TMS Set-up to TCK Clock Rise tTDIS TDI Set-up to TCK Clock Rise 10 Capture Set-up to TCK Rise 10 tCS Hold Times tTMSH TMS hold after TCK Clock Rise tTDIH TDI Hold after Clock Rise 10 ns Capture Hold after Clock Rise 10 ns tCH 10 ns Notes: 9. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 10. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1ns. Document #: 38-05240 Rev. *C Page 17 of 33 CY7C1380CV25 CY7C1382CV25 2.5V TAP AC Test Conditions 2.5V TAP AC Output Load Equivalent 1.25V Input pulse levels ......................................... VSS to 2.5V Input rise and fall time..................................................... 1 ns 50Ω Input timing reference levels .........................................1.25V Output reference levels.................................................1.25V TDO Test load termination supply voltage.............................1.25V Z O= 50Ω 20pF TAP DC Electrical Characteristics And Operating Conditions (0°C < TA < +70°C; Vdd = 2.5V ±0.125V unless otherwise noted)[11] Parameter VOH1 Description Output HIGH Voltage Description IOH = -1.0 mA Conditions VDDQ = 2.5V Min. 2.0 Max. VOH2 Output HIGH Voltage IOH = -100 µA VDDQ = 2.5V 2.1 VOL1 Output LOW Voltage IOL = 8.0 mA VDDQ = 2.5V VOL2 Output LOW Voltage IOL = 100 µA 0.2 V VIH Input HIGH Voltage VDDQ = 2.5V 1.7 VDD + 0.3 V VIL Input LOW Voltage VDDQ = 2.5V -0.3 0.7 V IX Input Load Current -5 5 µA V 0.4 VDDQ = 2.5V GND < VIN < VDDQ Unit V V Identification Register Definitions Instruction Field Revision Number (31:29) Device Depth (28:24) Architecture/Memory type(23:18) Bus Width/Density(17:12) Cypress JEDEC ID Code (11:1) ID Register Presence Indicator (0) CY7C1380CV25 (512Kx36) CY7C1382CV25 (1Mx18) 010 010 Description Describes the version number. 01011 01011 000000 000000 Defines memory type and architecture. Defines width and density. Reserved for internal use. 100101 010101 00000110100 00000110100 1 1 Allows unique identification of SRAM vendor. Indicates the presence of an ID register. Scan Register Sizes Register Name Bit Size (x36) Bit Size (x18) Instruction 3 3 Bypass 1 1 ID 32 32 Boundary Scan Order 72 72 Identification Codes Instruction Code Description EXTEST 000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations. SAMPLE Z 010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. RESERVED 011 Do Not Use: This instruction is reserved for future use. Note: 11. All voltages referenced to VSS (GND). Document #: 38-05240 Rev. *C Page 18 of 33 CY7C1380CV25 CY7C1382CV25 Identification Codes (continued) Instruction Code Description SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. This instruction does not implement 1149.1 preload function and is therefore not 1149.1 compliant. RESERVED 101 Do Not Use: This instruction is reserved for future use. RESERVED 110 Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. 119-Ball BGA Boundary Scan Order CY7C1380CV25 (512K x 36) Bit# Ball ID Bit# Ball ID 1 K4 37 B2 2 38 P4 3 H4 M4 39 N4 4 F4 40 R6 5 B4 41 T5 6 A4 42 T3 7 G4 43 R2 8 C6 44 R3 9 A6 45 P2 10 D6 46 P1 11 D7 47 N2 12 E6 48 L2 13 G6 49 K1 14 H7 50 N1 15 E7 51 M2 16 F6 52 L1 17 G7 53 K2 18 H6 54 Not Bonded (Preset to1) 19 T7 55 H1 20 K7 56 G2 21 L6 57 E2 22 N6 58 D1 23 P7 59 H2 24 K6 60 G1 25 L7 61 F2 26 M6 62 E1 27 N7 63 D2 28 P6 64 A5 29 B5 65 A3 30 B3 66 E4 31 C5 67 Internal 32 C3 68 L3 Document #: 38-05240 Rev. *C Page 19 of 33 CY7C1380CV25 CY7C1382CV25 119-Ball BGA Boundary Scan Order (continued) 33 C2 69 G3 34 A2 70 G5 35 T4 71 L5 36 B6 72 Internal Bit# Ball ID Bit# Ball ID 1 K4 37 B2 P4 3 H4 M4 38 39 N4 4 F4 40 R6 5 B4 41 T5 6 A4 42 T3 7 G4 43 R2 8 C6 44 R3 CY7C1382CV25 (1M x 18) 2 9 A6 45 Not Bonded (Preset to 0) 10 T6 46 Not Bonded (Preset to 0) 11 Not Bonded (Preset to 0) 47 Not Bonded (Preset to 0) 12 Not Bonded (Preset to 0) 48 Not Bonded (Preset to 0) 13 Not Bonded (Preset to 0) 49 P2 14 D6 50 N1 15 E7 51 M2 16 F6 52 L1 17 G7 53 K2 18 H6 54 Not Bonded (Preset to 1) 19 T7 55 H1 20 K7 56 G2 21 L6 57 E2 22 N6 58 D1 23 P7 59 Not Bonded (Preset to 0) 24 Not Bonded (Preset to 0) 60 Not Bonded (Preset to 0) 25 Not Bonded (Preset to 0) 61 Not Bonded (Preset to 0) 26 Not Bonded (Preset to 0) 62 Not Bonded (Preset to 0) 27 Not Bonded (Preset to 0) 63 Not Bonded (Preset to 0) 28 Not Bonded (Preset to 0) 64 A5 29 B5 65 A3 30 B3 66 E4 31 C5 67 Internal CY7C1382CV25 (1M x 18) (continued) Bit# Ball ID Bit# Ball ID 32 C3 68 Not Bonded (Preset to 0) 33 C2 69 Internal 34 A2 70 G3 35 T2 71 L5 36 B6 72 Internal Document #: 38-05240 Rev. *C Page 20 of 33 CY7C1380CV25 CY7C1382CV25 165-Ball fBGA Boundary Scan Order CY7C1380CV25 (512K x 36) Bit# 1 2 Ball ID B6 B7 Bit# 37 38 Ball ID N6 R6 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 A7 B8 A8 B9 A9 B10 A10 C11 E10 F10 G10 D10 D11 E11 F11 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 P6 R4 R3 P4 P3 R1 N1 L2 K2 J2 M2 M1 L1 K1 J1 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Bit# 32 33 34 35 36 Bit# 1 2 3 4 5 Document #: 38-05240 Rev. *C G11 54 H11 55 J10 56 K10 57 L10 58 M10 59 J11 60 K11 61 L11 62 M11 63 N11 64 R11 65 R10 66 R9 67 CY7C1380CV25 (512K x 36) (continued) Ball ID Bit# R8 68 P10 69 P9 70 P8 71 P11 72 CY7C1382CV25 (1M x 18) Ball ID Bit# B6 37 B7 38 A7 39 B8 40 A8 41 Not Bonded (Preset to1) G2 F2 E2 D2 G1 F1 E1 D1 C1 A2 B2 A3 B3 Ball ID B4 A4 A5 B5 A6 Ball ID N6 R6 P6 R4 R3 Page 21 of 33 CY7C1380CV25 CY7C1382CV25 165-Ball fBGA Boundary Scan Order (continued) 6 7 8 9 B9 A9 B10 A10 42 43 44 45 P4 P3 R1 Not Bonded (Preset to 0) 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 A11 Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) C11 D11 E11 F11 G11 H11 J10 K10 L10 M10 Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) R11 R10 R9 R8 P10 P9 P8 P11 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) N1 M1 L1 K1 J1 Not Bonded (Preset to 1) G2 F2 E2 D2 Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) A2 B2 A3 B3 Not Bonded (Preset to 0) Not Bonded (Preset to 0) A4 B5 A6 Document #: 38-05240 Rev. *C Page 22 of 33 CY7C1380CV25 CY7C1382CV25 Maximum Ratings DC Input Voltage ................................... –0.5V to VDD + 0.5V Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015)Latch-up Current > 200 mA Storage Temperature ................................. –65°C to +150°C Operating Range Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VDD Relative to GND........ –0.3V to +4.6V Range Ambient Temperature DC Voltage Applied to Outputs in three-state ....................................... –0.5V to VDDQ + 0.5V Commercial 0°C to +70°C Electrical Characteristics Over the Operating Range Parameter Description Industrial Test Conditions Power Supply Voltage VDDQ I/O Supply Voltage VDDQ = 2.5V VOH Output HIGH Voltage VDDQ = 2.5V, VDD = Min., IOH = –1.0 mA VOL Output LOW Voltage Input HIGH Voltage[12] VIL Input LOW Voltage[12] IX Input Load Current except ZZ and MODE Min. Max. Unit 2.375 2.625 V 2.375 VDD 2.0 VDDQ = 2.5V, VDD = Min., IOL = 1.0 mA 0.4 V 1.7 VDD + 0.3V V VDDQ = 2.5V –0.3 0.7 V –5 5 µA GND ≤ VI ≤ VDDQ Input = VDD Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled IDD VDD Operating Supply Current Automatic CE Power-down Current—TTL Inputs VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC VDD = Max, Device Deselected, VIN ≥ VIH or VIN ≤ VIL f = fMAX = 1/tCYC 5 µA 5 µA µA –30 Input = VSS IOZ µA –30 Input = VDD ISB1 V V VDDQ = 2.5V Input Current of MODE Input = VSS Input Current of ZZ VDDQ [12, 13] VDD VIH VDD 2.5V – 5%/+5% 2.5V – 5% to VDD –40°C to +85°C 5 µA 4.0-ns cycle, 250 MHz 350 mA 4.4-ns cycle, 225 MHz 325 mA 5.0-ns cycle, 200 MHz 300 mA –5 6.0-ns cycle, 167 MHz 275 mA 7.5-ns cycle, 133 MHz 245 mA 4.0-ns cycle, 250 MHz 120 mA 4.4-ns cycle, 225 MHz 110 mA 5.0-ns cycle, 200 MHz 100 mA 6.0-ns cycle, 167 MHz 90 mA 7.5-ns cycle, 133 MHz 85 mA ISB2 Automatic CE VDD = Max, Device Deselected, VIN ≤ All speeds Power-down 0.3V or VIN > VDDQ – 0.3V, f = 0 Current—CMOS Inputs 70 mA ISB3 VDD = Max, Device Deselected, or VIN 4.0-ns cycle, 250 MHz Automatic CE Power-down ≤ 0.3V or VIN > VDDQ – 0.3V 4.4-ns cycle, 225 MHz Current—CMOS Inputs f = fMAX = 1/tCYC 5.0-ns cycle, 200 MHz 105 mA 100 mA 95 mA 6.0-ns cycle, 167 MHz 85 mA 7.5-ns cycle, 133 MHz 80 mA All speeds 80 mA ISB4 Automatic CE Power-down Current—TTL Inputs VDD = Max, Device Deselected, VIN ≥ VIH or VIN ≤ VIL, f = 0 Shaded areas contain advance information. Notes: 12. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > -2V (Pulse width less than tCYC/2). 13. TPower-up: Assumes a linear ramp from 0v to VDD(min.) within 200ms. During this time VIH < VDD and VDDQ < VDD. Document #: 38-05240 Rev. *C Page 23 of 33 CY7C1380CV25 CY7C1382CV25 Thermal Resistance[14] Parameter Description ΘJA Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) Test Conditions TQFP Package BGA Package fBGA Package Unit 31 45 46 °C/W 6 7 3 °C/W Test conditions follow standard test methods and procedures for measuring thermal impedence, per EIA / JESD51. Capacitance[14] Parameter Description Test Conditions CIN Input Capacitance CCLK Clock Input Capacitance CI/O Input/Output Capacitance TQFP Package BGA Package fBGA Package Unit 5 8 9 pF TA = 25°C, f = 1 MHz, VDD = 2.5V. VDDQ = 2.5V 5 8 9 pF 5 8 9 pF AC Test Loads and Waveforms 2.5V I/O Test Load R = 1667Ω 2.5V OUTPUT OUTPUT RL = 50Ω Z0 = 50Ω GND 5 pF R =1538Ω INCLUDING JIG AND SCOPE VL = 1.25V (a) ALL INPUT PULSES VDD 10% 90% 10% 90% ≤ 1ns ≤ 1ns (b) (c) Switching Characteristics Over the Operating Range [19, 20] 250 MHz Parameter tPOWER Description VDD(Typical) to the first 225 MHz 200 MHz 167 MHz 133 MHz Min. Max. Min. Max. Min. Max. Min. Max Min. Max Access[15] 1 1 1 Unit 1 1 ms Clock tCYC Clock Cycle Time 4.0 4.4 5 6 7.5 ns tCH Clock HIGH 1.7 2.0 2.0 2.2 2.5 ns tCL Clock LOW 1.7 2.0 2.0 2.2 2.5 ns Output Times tCO Data Output Valid After CLK Rise tDOH Data Output Hold After CLK Rise 1.0 tCLZ Clock to Low-Z[16, 17, 18] 1.0 tCHZ Clock to High-Z[16, 17, 18] tOEV OE LOW to Output Valid OE LOW to Output Low-Z[16, 17, 18] tOELZ 2.6 2.8 1.0 1.0 2.6 3.4 0 0 ns ns 1.3 3.4 3.0 0 4.2 1.3 1.3 3.0 2.8 0 3.4 1.3 1.3 2.8 2.6 0 3.0 1.3 ns 3.4 ns 4.2 ns ns [16, 17, 18] tOEHZ 2.6 2.8 3.0 3.4 4.0 ns OE HIGH to Output High-Z Shaded areas contain advance information. Notes: 14. Tested initially and after any design or process change that may affect these parameters 15. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation can be initiated. 16. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage. 17. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions 18. This parameter is sampled and not 100% tested. 19. Timing reference level is 1.25V when VDDQ=2.5V. 20. Test conditions shown in (a) of AC Test Loads unless otherwise noted. Document #: 38-05240 Rev. *C Page 24 of 33 CY7C1380CV25 CY7C1382CV25 Switching Characteristics Over the Operating Range (continued)[19, 20] 250 MHz Parameter Description 225 MHz 200 MHz 167 MHz 133 MHz Min. Max. Min. Max. Min. Max. Min. Max Min. Max Unit Set-up Times tAS Address Set-up Before CLK Rise 1.2 1.4 1.4 1.5 1.5 ns tADS ADSC, ADSP Set-up Before CLK Rise 1.2 1.4 1.4 1.5 1.5 ns tADVS ADV Set-up Before CLK Rise GW, BWE, BWX Set-up Before CLK Rise 1.2 1.4 1.4 1.5 1.5 ns tWES 1.2 1.4 1.4 1.5 1.5 ns tDS Data Input Set-up Before CLK Rise 1.2 1.4 1.4 1.5 1.5 ns tCES Chip Enable Set-Up Before CLK Rise 1.2 1.4 1.4 1.5 1.5 ns Address Hold After CLK Rise 0.3 0.4 0.4 0.5 0.5 ns 0.4 0.4 0.5 0.5 ns 0.3 0.4 0.4 0.5 0.5 ns tWEH ADSP , ADSC Hold After CLK Rise ADV Hold After CLK Rise GW,BWE, BWX Hold After CLK Rise 0.3 0.3 0.4 0.4 0.5 0.5 ns tDH Data Input Hold After CLK Rise 0.3 0.4 0.4 0.5 0.5 ns tCEH Chip Enable Hold After CLK Rise 0.3 0.4 0.4 0.5 0.5 ns Hold Times tAH tADH tADVH Document #: 38-05240 Rev. *C Page 25 of 33 CY7C1380CV25 CY7C1382CV25 Switching Waveforms Read Cycle Timing[21] t CYC CLK t CH t ADS t CL t ADH ADSP tADS tADH ADSC tAS tAH A1 ADDRESS A2 tWES A3 Burst continued with new base address tWEH GW, BWE, BWx tCES Deselect cycle tCEH CE tADVS tADVH ADV ADV suspends burst. OE t OEHZ t CLZ Data Out (Q) Q(A1) High-Z tOEV tCO t OELZ tDOH Q(A2) t CHZ Q(A2 + 1) Q(A2 + 2) Q(A2 + 3) Q(A2) Q(A2 + 1) t CO Burst wraps around to its initial state Single READ BURST READ DON’T CARE UNDEFINED Notes: 21. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 22. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW. Document #: 38-05240 Rev. *C Page 26 of 33 CY7C1380CV25 CY7C1382CV25 Switching Waveforms (continued) Write Cycle Timing[21, 22] t CYC CLK tCH tADS tCL tADH ADSP tADS ADSC extends burst tADH tADS tADH ADSC tAS tAH A1 ADDRESS A2 A3 Byte write signals are ignored for first cycle when ADSP initiates burst tWES tWEH BWE, BWX tWES tWEH GW tCES tCEH CE t t ADVS ADVH ADV ADV suspends burst OE tDS Data In (D) High-Z t OEHZ tDH D(A1) D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2) Data Out (Q) BURST READ Single WRITE BURST WRITE DON’T CARE Document #: 38-05240 Rev. *C Extended BURST WRITE UNDEFINED Page 27 of 33 CY7C1380CV25 CY7C1382CV25 Switching Waveforms (continued) Read/Write Cycle Timing[21, 23, 24] tCYC CLK tCL tCH tADS tADH tAS tAH ADSP ADSC ADDRESS A1 A2 A3 A4 A5 A6 D(A5) D(A6) tWES tWEH BWE, BWX tCES tCEH CE ADV OE tDS tCO tDH tOELZ Data In (D) High-Z tCLZ Data Out (Q) Q(A1) High-Z tOEHZ D(A3) Q(A4) Q(A2) Back-to-Back READs Single WRITE Q(A4+1) Q(A4+2) Q(A4+3) BURST READ DON’T CARE Back-to-Back WRITEs UNDEFINED ZZ Mode Timing [25, 26] CLK t ZZ I t ZZREC ZZ t ZZI SUPPLY I DDZZ t RZZI ALL INPUTS (except ZZ) Outputs (Q) DESELECT or READ Only High-Z DON’T CARE Notes: 23. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC. 24. GW is HIGH. Document #: 38-05240 Rev. *C Page 28 of 33 CY7C1380CV25 CY7C1382CV25 Ordering Information Speed (MHz) 250 225 Ordering Code CY7C1380CV25-250AC CY7C1382CV25-250AC Package Name A101 Part and Package Type 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm) CY7C1380CV25-250BGC CY7C1382CV25-250BGC BG119 119 PBGA CY7C1380CV25-250BZC CY7C1382CV25-250BZC BB165A 165 fBGA CY7C1380CV25-225AC A101 Operating Range Commercial 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm) CY7C1382CV25-225AC 200 CY7C1380CV25-225BGC CY7C1382CV25-225BGC BG119 119 PBGA CY7C1380CV25-225BZC CY7C1382CV25-225BZC BB165A 165 fBGA CY7C1380CV25-200AC CY7C1382CV25-200AC CY7C1380CV25-200BGC A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm) BG119 119 PBGA BB165A 165 fBGA CY7C1382CV25-200BGC CY7C1380CV25-200BZC CY7C1382CV25-200BZC 167 CY7C1380CV25-167AC A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm) CY7C1382CV25-167AC CY7C1380CV25-167BGC BG119 119 PBGA BB165A 165 fBGA CY7C1382CV25-167BGC CY7C1380CV25-167BZC CY7C1382CV25-167BZC 133 CY7C1380CV25-133AC A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm) Notes: 25. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 26. DQs are in high-Z when exiting ZZ sleep mode. 167 CY7C1380CV25-167AI CY7C1382CV25-167AI A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm) CY7C1380CV25-167BGI CY7C1382CV25-167BGI BG119 119 PBGA CY7C1380CV25-167BZI BB165A 165 fBGA Industrial CY7C1382CV25-167BZI Shaded areas contain advance information. Please contact your local sales representative for availability of these parts. Document #: 38-05240 Rev. *C Page 29 of 33 CY7C1380CV25 CY7C1382CV25 Package Diagrams 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101 DIMENSIONS ARE IN MILLIMETERS. 16.00±0.20 1.40±0.05 14.00±0.10 100 81 80 1 20.00±0.10 22.00±0.20 0.30±0.08 0.65 TYP. 30 SEE DETAIL 50 0.20 MAX. 1.60 MAX. STAND-OFF 0.05 MIN. 0.15 MAX. 0.25 GAUGE PLANE 0.10 0° MIN. 0°-7° A 51 31 R 0.08 MIN. 0.20 MAX. 12°±1° (8X) SEATING PLANE R 0.08 MIN. 0.20 MAX. 0.60±0.15 0.20 MIN. 1.00 REF. DETAIL Document #: 38-05240 Rev. *C A 51-85050-*A Page 30 of 33 CY7C1380CV25 CY7C1382CV25 Package Diagrams (continued) 119-Lead PBGA (14 x 22 x 2.4 mm) BG119 51-85115-*B Document #: 38-05240 Rev. *C Page 31 of 33 CY7C1380CV25 CY7C1382CV25 Package Diagrams (continued) 165-Ball FBGA (13 x 15 x 1.2 mm) BB165A 51-85122-*C i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05240 Rev. *C Page 32 of 33 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY7C1380CV25 CY7C1382CV25 Document History Page Document Title: CY7C1380CV25/CY7C1382CV25 18-Mbit (512K x 36/1M x 18) Pipelined SRAM Document Number: 38-05240 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 116280 08/29/02 SKX New Data Sheet *A 121543 11/21/02 DSG Updated package diagrams 51-85115 (BG119) to rev. *B and 51-85122 (BB165A) to rev. *C *B 206081 See ECN RKF Final data sheet *C 230388 See ECN VBL Update Ordering Info section: Shade Selection Guide and Characteristics table Changed the title for 119-BGA pin table for CY7C1382CV25 from “512K x 18” to “1M x 18” Modified Identification Register Definitions table: Changed Bit #24 from “0” to “1” and changed “Device Width” to “Architecture/Memory type” Document #: 38-05240 Rev. *C Page 33 of 33