CYPRESS W195B

PRELIMINARY
W195B
Frequency Generator for Integrated Core Logic
Features
SDRAM, APIC, 48MHz Output Skew: ........................ 250 ps
• Maximized EMI suppression using Cypress’s Spread
Spectrum Technology
• Low jitter and tightly controlled clock skew
• Highly integrated device providing clocks required for
CPU, core logic, and SDRAM
• Two copies of CPU clocks
• Nine copies of SDRAM clocks
• Eight copies of PCI clock
• One copy of synchronous APIC clock
• Two copies of 66-MHz outputs
• Two copies of 48-MHz outputs
• One copy of selectable 24- or 48-MHz clock
• One copy of double strength 14.31818-MHz reference
clock
• Power-down control
• I2C interface for turning off unused clocks
Key Specifications
CPU, SDRAM Outputs Cycle-to-Cycle Jitter: ............. 250 ps
APIC, 48MHz, 3V66, PCI Outputs
Cycle-to-Cycle Jitter: .................................................. 500 ps
CPU, 3V66 Output Skew: ........................................... 175 ps
PCI Output Skew: ........................................................500 ps
CPU to SDRAM Skew (@100 MHz): ..................4.5 to 5.5 ns
CPU to 3V66 Skew (@ 66 MHz): ....................... 7.0 to 8.0 ns
3V66 to PCI Skew (3V66 lead):.......................... 1.5 to 3.5 ns
PCI to APIC Skew: ....................................................± 0.5 ns
Table 1. Frequency Selections
FS3 FS2 FS1 FS0 CPU SDRAM 3V66
1
1
1
1 133.6 133.6
66.8
1
1
1
0
Reserved
1
1
0
1 100.2 100.2
66.8
1
1
0
0
66.8
100.2
66.8
1
0
1
1
105
105
70
1
0
1
0
110
110
73.3
1
0
0
1
114
114
76
1
0
0
0
119
119
79.3
0
1
1
1
124
124
82.7
0
1
1
0
129
129
64.5
0
1
0
1
95
95
63.3
0
1
0
0
138
138
69
0
0
1
1
150
150
75
0
0
1
0
75
113
75
0
0
0
1
90
90
60
0
0
0
0
83.3
125
83.3
Block Diagram
Pin Configuration
VDDQ3
X1
X2
REF2X/FS3*
XTAL
OSC
PLL REF FREQ
VDDQ2
SDATA
SCLK
I2C
Logic
FS3*
FS2*
FS1*
FS0*
Divider,
Delay,
and
Phase
Control
Logic
2
CPU0:1
APIC
2
PLL 1
VDDQ3
3V66_0:1
PCI0/FS0*
PCI1/FS1*
PCI2/FS2*
5
PCI3:7
SDRAM0:8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
33.4
33.4
35
36.7
38
39.7
41.3
32.3
31.7
34.5
37.5
37.5
30
41.7
16.7
16.7
17.5
18.3
19
19.8
20.7
16.1
15.8
17.3
18.8
18.8
15
20.8
[1]
W195B
REF2x/FS3*
VDDQ3
X1
X2
GND
VDDQ3
3V66_0
3V66_1
GND
FS0*/PCI0
FS1^/PCI1
FS2*/PCI2
GND
PCI3
PCI4
VDDQ3
PCI5
PCI6
PCI7
GND
48MHz_0
48MHz_1
SI0/24_48#MHz*
VDDQ3
PCI APIC
33.4 16.7
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDQ2
APIC
VDDQ2
CPU0
CPU1
GND
VDDQ3
SDRAM0
SDRAM1
SDRAM2
GND
SDRAM3
SDRAM4
SDRAM5
VDDQ3
SDRAM6
SDRAM7
SDRAM8
GND
PWRDWN#*
SCLK
VDDQ3
GND
SDATA
9
PWRDWN#
PLL2
2
SI0/24_48#MHz*
/2
Cypress Semiconductor Corporation
VDDQ3
48MHz_0:1
Note:
1. Internal 250K pull-up or pull down resistors present on inputs
marked with * or ^ respectively. Design should not rely solely on
internal pull-up or pull down resistor to set I/O pins HIGH or LOW
respectively.
•
3901 North First Street
•
San Jose
•
CA 95134 •
408-943-2600
October 13, 1999, rev. **
PRELIMINARY
W195B
Pin Definitions
Pin No.
Pin
Type
REF2x/FS3
1
I/O
Reference Clock with 2x Drive/Frequency Select 3: 3.3V 14.318-MHz clock output. This pin also serves as the select strap to determine device operating frequency
as described in Table 1.
X1
3
I
Crystal Input: This pin has dual functions. It can be used as an external 14.318MHz crystal connection or as an external reference frequency input.
X2
4
I
Crystal Output: An input connection for an external 14.318-MHz crystal connection. If using an external reference, this pin must be left unconnected.
PCI0/FS0
10
I/O
PCI Clock 0/Frequency Selection 0: 3.3V 33-MHz PCI clock outputs. This pin also
serves as the select strap to determine device operating frequency as described in
Table 1.
PCI1/FS1
11
I/O
PCI Clock 1/Frequency Selection 1: 3.3V 33-MHz PCI clock outputs. This pin also
serves as the select strap to determine device operating frequency as described in
Table 1.
PCI2/FS2
12
I/O
PCI Clock 2/Frequency Selection 2: 3.3V 33-MHz PCI clock outputs. This pin
doubles as the select strap to determine device operating frequency as described
in Table 1.
14, 15, 17, 18,
19
O
PCI Clock 3 through 7: 3.3V 33-MHz PCI clock outputs. PCI0:7 can be individually
turned off via I2C interface.
7,8
O
66-MHz Clock Output: 3.3V output clocks. The operating frequency is controlled
by FS0:3 (see Table 1).
48MHz_0:1
21, 22
O
48-MHz Clock Output: 3.3V fixed 48-MHz, non-spread spectrum clock output.
SIO/
24_48#MHz
23
I/O
Clock Output for Super I/O: This is the input clock for a Super I/O (SIO) device.
During power-up, it also serves as a selection strap. If it is sampled HIGH, the output
frequency for SIO is 24 MHz. If the input is sampled LOW, the output is 48 MHz.
PWRDWN#
29
I
Power Down Control: LVTTL-compatible input that places the device in powerdown mode when held LOW.
45, 44
O
CPU Clock Outputs: Clock outputs for the host bus interface. Output frequencies
depending on the configuration of FS0:3. Voltage swing is set by VDDQ2.
41, 40, 39, 37,
36, 35, 33, 32,
31
O
APIC
47
O
Synchronous APIC Clock Outputs: Clock outputs running synchronous with the
PCI clock outputs. Voltage swing set by VDDQ2.
SDATA
25
I/O
Data pin for I2C circuitry.
SCLK
28
I
Clock pin for I2C circuitry.
VDDQ3
2, 6, 16, 24, 27,
34, 42
P
3.3V Power Connection: Power supply for SDRAM output buffers, PCI output buffers, reference output buffers, and 48-MHz output buffers. Connect to 3.3V.
VDDQ2
46, 48
P
2.5V Power Connection: Power supply for IOAPIC and CPU output buffers. Connect to 2.5V or 3.3V.
5, 9, 13, 20, 26,
30, 38, 43
G
Ground Connections: Connect all ground pins to the common system ground
plane.
Pin Name
PCI3:7
3V66_0:1
CPU0:1
SDRAM0:8,
GND
Pin Description
SDRAM Clock Outputs: 3.3V outputs for SDRAM. The operating frequency is
controlled by FS0:3 (see Table 1).
2
PRELIMINARY
W195B
Output Strapping Resistor
Series Termination Resistor
Clock Load
W195B
Output
Buffer
Power-on
Reset
Timer
Hold
Output
Low
Output Three-state
Q
10 kΩ
D
Data
Latch
Figure 1. Input Logic Selection Through Resistor Load Option
is delivered on the pins. If the power supply has not yet
reached full value, output frequency initially may be below target but will increase to target once supply voltage has stabilized. In either case, a short output clock cycle may be produced from the CPU clock outputs when the outputs are
enabled.
Overview
The W195B is a highly integrated frequency timing generator,
supplying all the required clock sources for an Intel® architecture platform using graphics integrated core logic.
Functional Description
Offsets Among Clock Signal Groups
I/O Pin Operation
Figure 2 and Figure 3 represent the phase relationship among
the different groups of clock outputs from W195B when it is
providing a 66-MHz CPU clock and a 100-MHz CPU clock,
respectively. It should be noted that when CPU clock is operating at 100 MHz, CPU clock output is 180 degrees out of
phase with SDRAM clock outputs.
Pin # 1, 10, 11, 12, 23 are dual-purpose l/O pins. Upon powerup the pin acts as a logic input. An external 10-kΩ strapping
resistor should be used. Figure 1 shows a suggested method
for strapping resistor connections.
After 2 ms, the pin becomes an output. Assuming the power
supply has stabilized by then, the specified output frequency
0 ns
10 ns
30 ns
40 ns
CPU 66 Period
CPU 66-MHz
SDRAM 100-MHz
3V66 66-MHz
20 ns
SDRAM 100 Period
Hub-PC
PCI 33-MHz
REF 14.318-MHz
USB 48-MHz
APIC
Figure 2. Group Offset Waveforms (66.8 CPU Clock, 100.2 SDRAM Clock)
3
PRELIMINARY
0 ns
10 ns
W195B
20 ns
30 ns
40 ns
CPU 100 Period
CPU 100-MHz
SDRAM 100-MHz
SDRAM 100 Period
Hub-PC
3V66 66-MHz
PCI 33-MHz
REF 14.318-MHz
USB 48-MHz
APIC
Figure 3. Group Offset Waveforms (100.2 CPU Clock, 100.2 SDRAM Clock)
Power Down Control
W195B provides one PWRDWN# signal to place the device in low-power mode. In low-power mode, the PLLs are turned off and
all clock outputs are driven LOW.
0ns
25ns
50ns
75ns
Center
1
2
VCO Internal
CPU 100MHz
3V66 66MHz
PCI 33MHz
APIC
PwrDwn
SDRAM 100MHz
REF 14.318MHz
USB 48MHz
Figure 4. PWRDWN# Timing Diagram[2, 3, 4, 5]
Notes:
2. Once the PWRDWN# signal is sampled LOW for two consecutive rising edges of CPU clock, clocks of interest should be held LOW on the next HIGH-to-LOW
transition.
3. PWRDWN# is an asynchronous input and metastable conditions could exist. This signal is synchronized inside W195B.
4. The shaded sections on the SDRAM, REF, and USB clocks indicate “don’t care” states.
5. Diagrams shown with respect to 100 MHz. Similar operation when CPU is 66 MHz.
4
PRELIMINARY
W195B
Spread Spectrum Generator
Where P is the percentage of deviation and F is the frequency
in MHz where the reduction is measured.
The device generates a clock that is frequency modulated in
order to increase the bandwidth that it occupies. By increasing
the bandwidth of the fundamental and its harmonics, the amplitudes of the radiated electromagnetic emissions are reduced. This effect is depicted in Figure 5.
The output clock is modulated with a waveform depicted in
Figure 6. This waveform, as discussed in “Spread Spectrum
Clock Generation for the Reduction of Radiated Emissions” by
Bush, Fessler, and Hardin produces the maximum reduction
in the amplitude of radiated electromagnetic emissions. The
deviation selected for this chip is –0.5% of the selected frequency. Figure 6 details the Cypress spreading pattern.
Cypress does offer options with more spread and greater EMI
reduction. Contact your local Sales representative for details
on these devices.
As shown in Figure 5, a harmonic of a modulated clock has a
much lower amplitude than that of an unmodulated signal. The
reduction in amplitude is dependent on the harmonic number
and the frequency deviation or spread. The equation for the
reduction is
dB = 6.5 + 9*log10(P) + 9*log10(F)
EMI Reduction
Spread
Spectrum
Enabled
NonSpread
Spectrum
Figure 5. Typical Clock and SSFTG Comparison
MIN.
Figure 6. Typical Modulation Profile
5
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
FREQUENCY
MAX.
PRELIMINARY
W195B
1 bit
7 bits
1
1
8 bits
1
Start bit
Slave Address
R/W
Ack
Command Code
Ack
Ack
Data Byte 1
Ack
Data Byte 2
Ack
1 bit
8 bits
1
8 bits
1
...
Byte Count = N
Data Byte N
Ack
Stop
8 bits
1
1
Figure 7. An Example of a Block Write[6]
Serial Data Interface
fer a maximum of 32 data bytes. The slave receiver address
for W195B is 11010010. Figure 7 shows an example of a block
write.
The W195B features a two-pin, serial data interface that can
be used to configure internal register settings that control particular device functions.
The command code and the byte count bytes are required as
the first two bytes of any transfer. W195B expects a command
code of 0000 0000. The byte count byte is the number of additional bytes required for the transfer, not counting the command code and byte count bytes. Additionally, the byte count
byte is required to be a minimum of 1 byte and a maximum of
32 bytes to satisfy the above requirement. Table 2 shows an
example of a possible byte count value.
Data Protocol
The clock driver serial protocol accepts only block writes from
the controller. The bytes must be accessed in sequential order
from lowest to highest byte with the ability to stop after any
complete byte has been transferred. Indexed bytes are not allowed.
A transfer is considered valid after the acknowledge bit corresponding to the byte count is read by the controller. The command code and byte count bytes are ignored by the W195B.
However, these bytes must be included in the data write sequence to maintain proper byte allocation.
A block write begins with a slave address and a write condition.
After the command code the core logic issues a byte count
which describes how many more bytes will follow in the message. If the host had 20 bytes to send. The first byte would be
the number 20 (14h), followed by the 20 bytes of data. The byte
count may not be 0. A block write command is allowed to transTable 2. Example of Possible Byte Count Value
Byte Count Byte
Notes
MSB
LSB
0000
0000
Not allowed. Must have at least one byte.
0000
0001
Data for functional and frequency select register (currently byte 0 in spec)
0000
0010
Reads first two bytes of data. (byte 0 then byte 1)
0000
0011
Reads first three bytes (byte 0, 1, 2 in order)
0000
0100
Reads first four bytes (byte 0, 1, 2, 3 in order)
0000
0101
Reads first five bytes (byte 0, 1, 2, 3, 4 in order)[7]
0000
0110
Reads first six bytes (byte 0, 1, 2, 3, 4, 5 in order)[7]
0000
0111
Reads first seven bytes (byte 0, 1, 2, 3, 4, 5, 6 in order)
0010
0000
Max. byte count supported = 32
Table 3. Serial Data Interface Control Functions Summary
Control Function
Description
Common Application
Output Disable
Any individual clock output(s) can be disabled.
Disabled outputs are actively held LOW.
(Reserved)
Reserved function for future device revision or pro- No user application. Register bit must be written as 0.
duction device testing.
Notes:
6. The acknowledgment bit is returned by the slave/receiver (W195B).
7. Byte 6 and 7 are not defined for W195B.
6
Unused outputs are disabled to reduce EMI and system power. Examples are clock outputs to unused
PCI slots.
PRELIMINARY
W195B
Serial Configuration Map
2. All unused register bits (reserved and N/A) should be written to a “0” level.
1. The serial bits will be read by the clock driver in the following
order:
3. All register bits labeled “Initialize to 0" must be written to
zero during initialization. Failure to do so may result in higher than normal operating current. The controller will read
back the last written value.
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 0: Control Register (1 = Enable, 0= Disable)[8]
Bit
Pin#
Name
Default
Pin Function
Bit 7
-
Reserved
0
Reserved
Bit 6
-
Reserved
0
Reserved
Bit 5
-
Reserved
0
Reserved
Bit 4
-
Reserved
0
Reserved
Bit 3
-
Reserved
0
Reserved
Bit 2
23
24/48MHz
1
(Active/Inactive)
Bit 1
21, 22
Bit 0
-
48MHz
1
(Active/Inactive)
Reserved
0
Reserved
Byte 1: Control Register (1 = Enable, 0= Disable)[8]
Bit
Pin#
Name
Default
Pin Description
Bit 7
32
SDRAM7
1
(Active/Inactive)
Bit 6
33
SDRAM6
1
(Active/Inactive)
Bit 5
35
SDRAM5
1
(Active/Inactive)
Bit 4
36
SDRAM4
1
(Active/Inactive)
Bit 3
37
SDRAM3
1
(Active/Inactive)
Bit 2
39
SDRAM2
1
(Active/Inactive)
Bit 1
40
SDRAM1
1
(Active/Inactive)
Bit 0
41
SDRAM0
1
(Active/Inactive)
Byte 2: Control Register (1 = Enable, 0= Disable)[8]
Bit
Pin#
Name
Default
Pin Description
Bit 7
19
PCI7
1
(Active/Inactive)
Bit 6
18
PCI6
1
(Active/Inactive)
Bit 5
17
PCI5
1
(Active/Inactive)
Bit 4
15
PCI4
1
(Active/Inactive)
Bit 3
14
PCI3
1
(Active/Inactive)
Bit 2
12
PCI2
1
(Active/Inactive)
Bit 1
11
PCI1
1
(Active/Inactive)
Bit 0
-
Reserved
0
Reserved
Note:
8. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be
configured during the normal modes of operation.
7
PRELIMINARY
W195B
Byte 3: Reserved Register (1 = Enable, 0= Disable)
Bit
Pin#
Name
Default
Pin Description
Bit 7
-
Reserved
0
Reserved
Bit 6
-
Reserved
0
Reserved
Bit 5
-
Reserved
0
Reserved
Bit 4
-
Reserved
0
Reserved
Bit 3
-
Reserved
0
Reserved
Bit 2
-
Reserved
0
Reserved
Bit 1
-
Reserved
0
Reserved
Bit 0
-
Reserved
0
Reserved
Byte 4: Reserved Register (1 = Enable, 0= Disable)
Bit
Pin#
Name
Default
Pin Function
Bit 7
-
SEL3
0
See Table 4
Bit 6
-
SEL2
0
See Table 4
Bit 5
-
SEL1
0
See Table 4
Bit 4
-
SEL0
0
See Table 4
Bit 3
-
FS(0:3) Override
0
0 = Select operating frequency by FS(0:3) strapping
1 = Select operating frequency by SEL(0:4) bit settings
Bit 2
-
SEL4
0
See Table 4
Bit 1
-
Reserved
0
Reserved
Bit 0
-
Reserved
0
Reserved
Byte 5: Reserved Register (1 = Enable, 0= Disable)
Bit
Pin#
Name
Default
Pin Description
Bit 7
-
Reserved
0
Reserved
Bit 6
-
Reserved
0
Reserved
Bit 5
-
Reserved
0
Reserved
Bit 4
-
Reserved
0
Reserved
Bit 3
-
Reserved
0
Reserved
Bit 2
-
Reserved
0
Reserved
Bit 1
-
Reserved
0
Reserved
Bit 0
-
Reserved
0
Reserved
Byte 6: Reserved Register (1 = Enable, 0= Disable)
Bit
Pin#
Name
Default
Pin Description
Bit 7
-
Reserved
0
Reserved
Bit 6
-
Reserved
0
Reserved
Bit 5
-
Reserved
0
Reserved
Bit 4
-
Reserved
0
Reserved
Bit 3
-
Reserved
0
Reserved
Bit 2
-
Reserved
0
Reserved
Bit 1
-
Reserved
0
Reserved
Bit 0
-
Reserved
0
Reserved
8
PRELIMINARY
W195B
Table 4. Additional Frequency Selections through Serial Data Interface Data Bytes
Input Conditions
Output Frequency
Data Byte 4, Bit 3 = 1
Bit 2
SEL_4
Bit 7
SEL_3
Bit 6
SEL_2
Bit 5
SEL_1
Bit 4
SEL_0
CPU
SDRAM
3V66
PCI
APIC
Spread
Spectrum
1
1
1
1
1
133.6
133.6
66.8
33.4
16.7
±0.5%
1
1
1
1
0
1
1
1
0
1
100.2
100.2
66.8
33.4
16.7
±0.5%
1
1
1
0
0
66.8
100.2
66.8
33.4
16.7
±0.5%
1
1
0
1
1
107
107
71.3
35.7
17.8
±0.5%
1
1
0
1
0
112
112
74.7
37.3
18.7
±0.5%
1
1
0
0
1
117
117
78
39
19.5
±0.5%
1
1
0
0
0
121
121
80.7
40.3
20.2
±0.5%
1
0
1
1
1
155
155
77.5
38.8
19.4
±0.5%
1
0
1
1
0
145
145
72.5
36.3
18.1
±0.5%
1
0
1
0
1
136
136
68
34
17
±0.5%
1
0
1
0
0
140
140
70
35
17.5
±0.5%
1
0
0
1
1
72
108
72
36
18
±0.5%
1
0
0
1
0
130
130
65
32.5
16.3
±0.5%
1
0
0
0
1
127
127
63.5
31.8
15.9
±0.5%
1
0
0
0
0
125
125
62.5
31.3
15.6
±0.5%
0
1
1
1
1
133.6
133.6
66.8
33.4
16.7
OFF
0
1
1
1
0
0
1
1
0
1
100.2
100.2
66.8
33.4
16.7
OFF
0
1
1
0
0
66.8
100.2
66.8
33.4
16.7
OFF
0
1
0
1
1
105
105
70
35
17.5
OFF
Reserved
Reserved
0
1
0
1
0
110
110
73.3
36.7
18.3
OFF
0
1
0
0
1
114
114
76
38
19
OFF
0
1
0
0
0
119
119
79.3
39.7
19.8
OFF
0
0
1
1
1
124
124
82.7
41.3
20.7
OFF
0
0
1
1
0
129
129
64.5
32.3
16.1
OFF
0
0
1
0
1
95
95
63.3
31.7
15.8
OFF
0
0
1
0
0
138
138
69
34.5
17.3
OFF
0
0
0
1
1
150
150
75
37.5
18.8
OFF
0
0
0
1
0
75
113
75
37.5
18.8
OFF
0
0
0
0
1
90
90
60
30
15
OFF
0
0
0
0
0
83.3
125
83.3
41.7
20.8
OFF
9
PRELIMINARY
W195B
DC Electrical Characteristics
DC parameters must be sustainable under steady state (DC) conditions.
Absolute Maximum DC Power Supply
Parameter
Description
Min.
Max.
Unit
VDDQ3
3.3V Core Supply Voltage
–0.5
4.6
V
VDDQ2
2.5V I/O Supply Voltage
–0.5
3.6
V
TS
Storage Temperature
–65
150
°C
Min.
Max.
Unit
Absolute Maximum DC I/O
Parameter
Description
Vi/o3
3.3V Core Supply Voltage
–0.5
4.6
V
Vi/o2
2.5V I/O Supply Voltage
–0.5
3.6
V
ESD prot.
2.5V I/O Supply Voltage
2000
V
DC Operating Requirements
Parameter
Description
Condition
Min.
Max.
Unit
VDD3
3.3V Core Supply Voltage
3.3V±5%
3.135
3.465
V
VDDQ3
3.3V I/O Supply Voltage
3.3V±5%
3.135
3.465
V
VDDQ2
2.5V I/O Supply Voltage
2.5V±5%
2.375
2.625
V
VDD3
VDD3 = 3.3V±5%
Vih3
3.3V Input High Voltage
Vil3
3.3V Input Low Voltage
Iil
Input Leakage Current[9]
Voh2
Vol2
2.0
VDD+0.3
V
VSS–0.3
0.8
V
0<Vin<VDDQ3
–5
+5
µA
2.5V Output High Voltage
Ioh=(–1 mA)
2.0
2.5V Output Low Voltage
Iol=(1 mA)
Voh3
3.3V Output High Voltage
Ioh=(–1 mA)
Vol3
3.3V Output Low Voltage
Iol=(1 mA)
VDDQ2 = 2.5V±5%
V
0.4
V
VDDQ3 = 3.3V±5%
2.4
V
0.4
V
VDDQ3 = 3.3V±5%
Vpoh3
PCI Bus Output High Voltage
Ioh=(–1 mA)
Vpol3
PCI Bus Output Low Voltage
Iol=(1 mA)
Cin
Input Pin Capacitance
Cxtal
Xtal Pin Capacitance
Cout
Output Pin Capacitance
Lpin
Pin Inductance
Ta
Ambient Temperature
2.4
0.55
V
5
pF
22.5
pF
6
pF
0
7
nH
0
70
°C
13.5
No Airflow
Note:
9. Input Leakage Current does not include inputs with pull-up or pull-down resistors.
10
V
PRELIMINARY
W195B
AC Electrical Characteristics
TA = 0°C to +70°C, VDDQ3 = 3.3V±5%, V DDQ2= 2.5V±5%
fXTL = 14.31818 MHz
Spread Spectrum function turned off
Parameter
Description
66.6-MHz Host
100-MHz Host
Min.
Max.
Min.
Max.
Unit
Notes
TPeriod
Host/CPUCLK Period
15.0
15.5
10.0
10.5
ns
10
THIGH
Host/CPUCLK High Time
5.2
N/A
3.0
N/A
ns
13
TLOW
Host/CPUCLK Low Time
5.0
N/A
2.8
N/A
ns
14
TRISE
Host/CPUCLK Rise Time
0.4
1.6
0.4
1.6
ns
TFALL
Host/CPUCLK Fall Time
0.4
1.6
0.4
1.6
ns
TPeriod
SDRAM CLK Period
10.0
10.5
10.0
10.5
ns
10
THIGH
SDRAM CLK High Time
3.0
N/A
3.0
N/A
ns
13
TLOW
SDRAM CLK Low Time
2.8
N/A
2.8
N/A
ns
14
TRISE
SDRAM CLK Rise Time
0.4
1.6
0.4
1.6
ns
TFALL
SDRAM CLK Fall Time
0.4
1.6
0.4
1.6
ns
TPeriod
APIC CLK Period
60.0
64.0
60.0
64.0
ns
10
THIGH
APIC CLK High Time
25.5
N/A
25.5
N/A
ns
13
TLOW
APIC CLK Low Time
25.3
N/A
25.3
N/A
ns
14
TRISE
APIC CLK Rise Time
0.4
1.6
0.4
1.6
ns
TFALL
APIC CLK Fall Time
0.4
1.6
0.4
1.6
ns
TPeriod
3V66 CLK Period
15.0
16.0
15.0
16.0
ns
10, 12
THIGH
3V66 CLK High Time
5.25
N/A
5.25
N/A
ns
13
TLOW
3V66 CLK Low Time
5.05
N/A
5.05
N/A
ns
14
TRISE
3V66 CLK Rise Time
0.5
2.0
0.5
2.0
ns
TFALL
3V66 CLK Fall Time
0.5
2.0
0.5
2.0
ns
TPeriod
PCI CLK Period
30.0
N/A
30.0
N/A
ns
10, 11
THIGH
PCI CLK High Time
12.0
N/A
12.0
N/A
ns
13
TLOW
PCI CLK Low Time
12.0
N/A
12.0
N/A
ns
14
TRISE
PCI CLK Rise Time
0.5
2.0
0.5
2.0
ns
TFALL
PCI CLK Fall Time
0.5
2.0
0.5
2.0
ns
tpZL, tpZH
Output Enable Delay (All outputs)
1.0
10.0
1.0
10.0
ns
tpLZ, tpZH
Output Disable Delay (All outputs)
1.0
10.0
1.0
10.0
ns
tstable
All Clock Stabilization from Power-Up
3
3
ms
Notes:
10. Period, jitter, offset, and skew measured on rising edge at 1.25 for 2.5V clocks and at 1.5V for 3.3V clocks.
11. THIGH is measured at 2.0V for 2.5V outputs, 2.4V for 3.3V outputs.
12. TLOW is measured at 0.4V for all outputs.
13. The time specified is measured from when VDDQ3 achieves its nominal operating level (typical condition VDDQ3 = 3.3V) until the frequency output is stable and
operating within specification.
14. TRISE and TFALL are measured as a transition through the threshold region Vol = 0.4V and Voh = 2.0V (1 mA) JEDEC specification.
11
PRELIMINARY
W195B
Group Skew and Jitter Limits
Output Group
Pin-Pin Skew Max
Cycle-Cycle Jitter
Duty Cycle
Nom Vdd
Skew, Jitter
Measure Point
CPU
175 ps
250 ps
45/55
2.5V
1.25V
SDRAM
250 ps
250 ps
45/55
3.3V
1.5V
APIC
250 ps
500 ps
45/55
2.5V
1.25V
48MHz
250 ps
500 ps
45/55
3.3V
1.5V
3V66
175 ps
500 ps
45/55
3.3V
1.5V
PCI
500 ps
500 ps
45/55
3.3V
1.5V
REF
N/A
1000 ps
45/55
3.3V
1.5V
Output
Buffer
Test Point
Test Load
Clock Output Wave
TPERIOD
Duty Cycle
THIGH
2.0
2.5V Clocking
Interface
1.25
0.4
TLOW
TRISE
TFALL
TPERIOD
Duty Cycle
THIGH
2.4
3.3V Clocking
Interface
1.5
0.4
TLOW
TRISE
TFALL
Figure 8. Output Buffer
Ordering Information
Ordering Code
W195B
Package
Name
H
Package Type
48-pin SSOP (300 mils)
Intel is a registered trademark of Intel Corporation.
Document #: 38-00815
12
PRELIMINARY
W195B
Package Diagram
48-Pin Shrink Small Outline Package (SSOP, 300 mils)
© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
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