ETC W238

W238
FTG for Integrated Core Logic with 133-MHz FSB
Features
APIC, 48-MHz, SDRAM Output Skew: ........................250 ps
• Maximized EMI suppression using Cypress’s Spread
Spectrum technology
• Low jitter and tightly controlled clock skew
• Highly integrated device providing clocks required for
CPU, core logic, and SDRAM
• Two copies of CPU clock at 66/100/133 MHz
• Thirteen copies of SDRAM clocks at 100/133 MHz
• Five copies of PCI clock compliant to PCI spec 2-1 and
capable of driving a maximum load of 40pf
• One copy of synchronous APIC clock
• Two copies of 48-MHz clock (non-spread spectrum) optimized for USB reference input and video dot clock
• Three copies of 66-MHz fixed clock
• One copy of 14.31818-MHz reference clock
• Power down control
• SMBus interface for turning off unused clocks
CPU, 3V66 Output Skew:............................................175 ps
PCI Output Skew:........................................................500 ps
CPU to SDRAM Skew (@ 133 MHz):.........................±0.5 ns
CPU to SDRAM Skew (@ 100 MHz):.................4.5 to 5.5 ns
CPU to 3V66 Skew (@ 66 MHz): .......................7.0 to 8.0 ns
3V66 to PCI Skew (3V66 lead):..........................1.5 to 3.5 ns
PCI to APIC Skew: .....................................................±0.5 ns
Table 1. Pin Selectable Functions
Tristate#
FSEL1
FSEL0
Function
SDRAM
0
X
0
Three -State
Three-State
0
X
1
Test
Test
1
0
0
66 MHz
100 MHz
1
0
1
100 MHz
100 MHz
Key Specifications
1
1
0
133 MHz
133 MHz
CPU, SDRAM Outputs Cycle-to-Cycle Jitter:.............. 250 ps
1
1
1
133 MHz
100 MHz
APIC, 48-MHz, 3V66, PCI Outputs
Cycle-to-Cycle Jitter:................................................... 500 ps
Pin Configuration [1]
Block Diagram
VDDQ3
X1
X2
REF/FSEL1
XTAL
OSC
PLL REF FREQ
VDDQ2
SMBus
Logic
CPU0:1
2
APIC0:1
2
VDDQ3
FSEL0:1
PLL 1
3V66_0:1
2
3V66_AGP
PCI0_ICH
PCI1:4
4
13
SDRAM0:12
PWRDWN#/TRISTATE#
VDDQ3
USB
PLL2
DOT
Cypress Semiconductor Corporation
Document #: 38-07219 Rev. *A*
•
3901 North First Street
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
W238
SDATA
SCLK
Divider,
Delay,
and
Phase
Control
Logic
APIC
VDDQ2
GND
REF/FSEL1
VDDQ3
X1
X2
GND
VDDQ3
3V66_0
3V66_1
3V66_AGP
GND
PCI_ICH
PCI1
PCI2
VDDQ3
GND
PCI3
PCI4
FSEL0
GNDA
VDDA
SCLK
SDATA
GND
VDDQ3
USB
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
VDDQ2
CPU0
CPU1
GND
SDRAM0
SDRAM1
VDDQ3
GND
SDRAM2
SDRAM3
SDRAM4
SDRAM5
VDDQ3
GND
SDRAM6
SDRAM7
SDRAM8
SDRAM9
VDDQ3
GND
SDRAM10
SDRAM11
VDDQ3
GND
SDRAM12
PWRDWN#/TRISTATE#
DOT
Note:
1. Internal pull-down resistors present on input marked with *.
Design should not solely rely on internal pull-down resister to
set I/O pin LOW.
•
San Jose
•
CA 95134 • 408-943-2600
Revised December 15, 2002
W238
Pin Definitions
Pin No.
Pin
Type
REF/FSEL1
4
I/O
X1
6
I
Crystal Input: This pin has dual functions. It can be used as an external
14.318-MHz crystal connection or as an external reference frequency input.
X2
7
I
Crystal Output: An input connection for an external 14.318-MHz crystal. If using
an external reference, this pin must be left unconnected.
PCI0_ICH,
PCI1:4
14, 15, 16, 19,
20
O
PCI Clock 0 through 4: 3.3V 33-MHz PCI clock outputs. PCI1:4 can be individually
turned off via SMBus interface.
3V66_0:1
3V66_AGP
10, 11, 12
O
66-MHz Clock Output: 3.3V fixed 66-MHz clock.
USB
28
O
USB Clock Output: 3.3V fixed 48-MHz, non-spread spectrum USB clock outputs.
DOT
29
O
Dot Clock Output: 3.3V 48-MHz, non-spread spectrum signal.
FSEL0
21
I
Clock Function Selection Pins: LVTTL-compatible input to select device functions. See Table 1 for detailed descriptions.
PWRDWN#/
TRISTATE#
30
I
TRISTATE#/PWRDWN#: During power-up, this pin defaults to the TRISTATE# input function to enable the TRISTATE# and test modes listed in Table 1. Approximately 1 ms to 2 ms after power on and the TRISTATE#/PWRDWN# input is HIGH,
this pin will change to the PWRDWN# input function and TRISTATE# functionality
is disabled. On the other hand, if the status of the TRISTATE#/PWRDWN# input
pin is LOW during power-on, this pin will be functioned as the TRISTATE# input
function until the input becomes HIGH and the function of this input pin will become
PWRDWN#.
54, 53
O
CPU Clock Outputs: Clock outputs for the host bus interface and integrated test
port. Output frequencies run at 66 MHz, 100 MHz, or 133 MHz, depending on the
configuration of FSEL0:1 and TRISTATE#. Voltage swing set by VDDQ2.
51, 50, 47, 46,
45, 44, 41, 40,
39, 38, 35, 34,
31
O
SDRAM Clock Outputs: 3.3V outputs running to 133 MHz. SDRAM0:7 can be
individually turned off via SMBus interface.
APIC
1
O
Synchronous APIC Clock Outputs: Clock outputs running synchronous with the
PCI clock outputs (33 MHz). Voltage swing set by VDDQ2.
SDATA
25
I/O
Data pin for SMBus circuitry.
SCLK
24
I
Clock pin for SMBus circuitry.
5, 9, 17, 27, 33,
37, 43, 49
P
3.3V Power Connection: Power supply for SDRAM output buffers, PCI output
buffers, 3V66 output buffers, reference output buffers, and 48-MHz output buffers.
Connect to 3.3V.
23
O
3.3V Power Connection: Power supply for core logic, PLL circuitry. Connect to
3.3V.
VDDQ2
2, 55
P
2.5V Power Connection: Power supply for IOAPIC and CPU output buffers. Connect to 2.5V or 3.3V.
GNDA
22
G
Ground Connections: Ground for core logic, PLL circuitry.
3, 8, 13, 18, 26,
32, 36, 42, 48,
52, 56
G
Ground Connections: Connect all ground pins to the common system ground
plane.
Pin Name
CPU0:1
SDRAM0:12
VDDQ3
VDDA
GND
Document #: 38-07219 Rev. *A*
Pin Description
Reference Clock/Function Select: 3.3V 14.318-MHz clock output. This pin also
serves as a strap option for CPU frequency selection. See Table 1 for detailed
descriptions.
Page 2 of 17
W238
VDD
Output Strapping Resistor
Series Termination Resistor
10 kΩ
(Load Option 1)
Clock Load
W238
Output
Buffer
Power-on
Reset
Timer
Hold
Output
Low
Output Three-state
Q
10kΩ
(Load Option 0)
D
Data
Latch
Figure 1. Input Logic Selection Through Resistor Load Option
Overview
The W238 is a highly integrated frequency timing generator,
supplying all the required clock sources for an Intel® architecture platform using graphics integrated core logic.
Functional Description
I/O Pin Operation
REF/SEL1 is a dual-purpose l/O pin. Upon power-up the pin
acts as a logic input. CPU clock outputs will be determined by
the status of FSEL0:1 input pins. An external 10-kΩ strapping
resistor should be used. Figure 1 shows a suggested method
for strapping resistor connections.
After 2 ms, the pin becomes an output. Assuming the power
supply has stabilized by then, the specified output frequency
is delivered on the pins. If the power supply has not yet
reached full value, output frequency initially may be below target but will increase to target once supply voltage has stabilized. In either case, a short output clock cycle may be produced from the CPU clock outputs when the outputs are
enabled.
Pin Selectable Functions
Table 1 outlines the device functions selectable through
Tristate# and FSEL0:1. Specific outputs available at each pin
are detailed in Table 2 below.
Table 2. CK Solano Truth Table
Tristate#
FSEL1
FSEL0
CPU
SDRAM
3V66
PCI
48MHz
REF
APIC
Notes
0
X
0
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
2
0
X
1
TCLK/4
TCLK/4
TCLK/6
TCLK/12
TCLK/2
TCLK
TCLK/12
4, 5
1
0
0
66 MHz
100 MHz
66 MHz
33 MHz
48 MHz
14.318 MHz
33 MHz
3, 6, 7
1
0
1
100 MHz
100 MHz
66 MHz
33 MHz
48 MHz
14.318 MHz
33 MHz
3, 6, 7
1
1
1
133 MHz
133MHz
66 MHz
33 MHz
48 MHz
14.318 MHz
33 MHz
2, 5, 6
1
1
1
133 MHz
100 MHz
66 MHz
33 MHz
48 MHz
14.318 MHz
33 MHz
2, 5, 6
Notes:
2. Provided for board-level “bed of nails” testing.
3. “Normal” mode of operation.
4. TCLK is a test clock overdriven on the XTAL_IN input during test mode.
5. Required for DC output impedance verification.
6. Range of reference frequency allowed is min. = 14.316 MHz, nominal = 14.31818 MHz, max. = 14.32 MHz.
7. Frequency accuracy of 48 MHz must be +167 PPM to match USB default.
Document #: 38-07219 Rev. *A*
Page 3 of 17
W238
Offsets Among Clock Signal Groups
Figure 2 and Figure 3 represent the phase relationship among
the different groups of clock outputs from W238 when it is providing a 66-MHz CPU clock and a 100-MHz CPU clock, re10 ns
0 ns
20 ns
spectively. It should be noted that when CPU clock is operating
at 100 MHz, CPU clock output is 180 degrees out of phase
with SDRAM clock outputs.
30 ns
40 ns
CPU 66 Period
CPU 66-MHz
SDRAM 100-MHz
SDRAM 100 Period
Hub-PCI
3V66 66-MHz
PCI 33-MHz
REF 14.318-MHz
USB 48-MHz
APIC 33-MHz
Figure 2. Group Offset Waveforms (66-MHz CPU/100-MHz SDRAM)
10 ns
0 ns
CPU 100-MHz
30 ns
40 ns
CPU 100 Period
SDRAM 100-MHz
3V66 66-MHz
20 ns
SDRAM 100 Period
Hub-PCI
PCI 33-MHz
REF 14.318-MHz
USB 48-MHz
APIC 33-MHz
Figure 3. Group Offset Waveforms (100-MHz CPU/100-MHz SDRAM)
Document #: 38-07219 Rev. *A*
Page 4 of 17
W238
10 ns
0 ns
20 ns
30 ns
40 ns
Cycle Repeats
CPU 133-MHz
SDRAM 100-MHz
3V66 66-MHz
PCI 33-MHz
APIC 33-MHz
REF 14.318-MHz
USB 48-MHz
DOT 48-MHz
Figure 4. Group Offset Waveforms (133-MHz CPU/100-MHz SDRAM)
0 ns
CPU 100-MHz
10 ns
20 ns
30 ns
40 ns
Cycle Repeat
SDRAM 133-MHz
3V66 66-MHz
PCI 33-MHz
APIC 3-3MHz
REF 14.318-MHz
USB 48-MHz
DOT 48-MHz
Figure 5. Group Offset Waveform (133-MHz CPU/133-MHz SDRAM)
Document #: 38-07219 Rev. *A*
Page 5 of 17
W238
Power Down Control
W238 provides one PWRDWN# signal to place the device in low-power mode. In low-power mode, the PLLs are turned off and
all clock outputs are driven LOW.
0ns
25ns
50ns
75ns
Center
1
2
VCO Internal
CPU 100MHz
3V66 66MHz
PCI 33MHz
APIC 33MHz
PwrDwn
SDRAM 100MHz
REF 14.318MHz
USB 48MHz
Figure 6. W238 PWRDWN# Timing Diagram[8, 9, 10, 11]
Table 3. W238 Maximum Allowed Current
Max. 2.5V supply consumption
Max. discrete cap loads,
VDDQ2 = 2.625V
All static inputs = VDDQ3 or VSS
Max. 3.3V supply consumption
Max. discrete cap loads
VDDQ3 = 3.465V
All static inputs = VDDQ3 or VSS
Powerdown Mode
(PWRDWN# = 0)
100 µA
500 µA
Full Active 66 MHz
FSEL1:0 = 00 (PWRDWN# =1)
30 mA
280 mA
Full Active 100 MHz
FSEL1:0 = 01 (PWRDWN# =1)
40 mA
280 mA
Full Active 133 MHz
FSEL1:0 = 10, 11 (PWRDWN# =1)
50 mA
400 mA
W238
Condition
Notes:
8. Once the PWRDWN# signal is sampled LOW for two consecutive rising edges of CPU, clocks of interest will be held LOW on the next HIGH-to-LOW transition.
9. PWRDWN# is an asynchronous input and metastable conditions could exist. This signal is synchronized inside W238.
10. The shaded sections on the SDRAM, REF, and USB clocks indicate “Don’t Care” states.
11. Diagrams shown with respect to 100 MHz. Similar operation when CPU is 66 MHz.
Document #: 38-07219 Rev. *A*
Page 6 of 17
W238
Spread Spectrum Frequency Timing Generator
Where P is the percentage of deviation and F is the frequency
in MHz where the reduction is measured.
The device generates a clock that is frequency modulated in
order to increase the bandwidth that it occupies. By increasing
the bandwidth of the fundamental and its harmonics, the amplitudes of the radiated electromagnetic emissions are reduced. This effect is depicted in Figure 7.
The output clock is modulated with a waveform depicted in
Figure 8. This waveform, as discussed in “Spread Spectrum
Clock Generation for the Reduction of Radiated Emissions” by
Bush, Fessler, and Hardin produces the maximum reduction
in the amplitude of radiated electromagnetic emissions. The
deviation selected for this chip is –0.5% of the selected frequency. Figure 8 details the Cypress spreading pattern.
Cypress does offer options with more spread and greater EMI
reduction. Contact your local Sales representative for details
on these devices.
As shown in Figure 7, a harmonic of a modulated clock has a
much lower amplitude than that of an unmodulated signal. The
reduction in amplitude is dependent on the harmonic number
and the frequency deviation or spread. The equation for the
reduction is:
dB = 6.5 + 9*log10(P) + 9*log10(F)
Spread Spectrum clocking is activated or deactivated by selecting the appropriate value for bit 3 in data byte 0 of the
SMBus data stream. Refer to page 9 for more details.
EMI Reduction
Spread
Spectrum
Enabled
NonSpread
Spectrum
Figure 7. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
FREQUENCY
MAX.
MIN.
Figure 8. Typical Modulation Profile
Document #: 38-07219 Rev. *A*
Page 7 of 17
W238
1 bit
7 bits
1
1
8 bits
1
Start bit
Slave Address
R/W
Ack
Command Code
Ack
Ack
Data Byte 1
Ack
Data Byte 2
Ack
1 bit
8 bits
1
8 bits
1
...
Byte Count = N
Data Byte N
Ack
Stop
8 bits
1
1
Figure 9. An Example of a Block Write[12]
Serial Data Interface
The W238 features a two-pin, serial data interface that can be
used to configure internal register settings that control particular device functions.
Data Protocol
The clock driver serial protocol accepts only block writes from
the controller. The bytes must be accessed in sequential order
from lowest to highest byte with the ability to stop after any
complete byte has been transferred. Indexed bytes are not
allowed.
A block write begins with a slave address and a write condition.
After the command code the core logic issues a byte count
which describes how many more bytes will follow in the message. If the host had 20 bytes to send, the first byte would be
the number 20 (14h), followed by the 20 bytes of data. The
byte count may not be 0. A block write command is allowed to
transfer a maximum of 32 data bytes. The slave receiver address for W238 is 11010010. Figure 9 shows an example of a
block write.
The command code and the byte count bytes are required as
the first two bytes of any transfer. W238 expects a command
code of 0000 0000. The byte count byte is the number of additional bytes required for the transfer, not counting the command code and byte count bytes. Additionally, the byte count
byte is required to be a minimum of 1 byte and a maximum of
32 bytes to satisfy the above requirement. Table 4 shows an
example of a possible byte count value.
A transfer is considered valid after the acknowledge bit corresponding to the byte count is read by the controller. The command code and byte count bytes are ignored by the W238.
However, these bytes must be included in the data write sequence to maintain proper byte allocation.
Table 4. Example of Possible Byte Count Value
Byte Count Byte
Notes
MSB
LSB
0000
0000
Not allowed. Must have at least one byte.
0000
0001
Data for functional and frequency select register (currently byte 0 in spec)
0000
0010
Reads first two bytes of data. (byte 0 then byte1)
0000
0011
Reads first three bytes (byte 0, 1, 2 in order)
0000
0100
Reads first four bytes (byte 0, 1, 2, 3 in order)
0000
0101
Reads first five bytes (byte 0, 1, 2, 3, 4 in order)[13]
0000
0110
Reads first six bytes (byte 0, 1, 2, 3, 4, 5 in order)[13]
0000
0111
Reads first seven bytes (byte 0, 1, 2, 3, 4, 5, 6 in order)
0010
0000
Max. byte count supported = 32
Table 5. Serial Data Interface Control Functions Summary
Control Function
Description
Common Application
Output Disable
Any individual clock output(s) can be disabled.
Disabled outputs are actively held LOW.
Unused outputs are disabled to reduce EMI and system power. Examples are clock outputs to unused
PCI slots.
Spread Spectrum
Enabling
Enables or disables spread spectrum clocking.
For EMI reduction.
(Reserved)
Reserved function for future device revision or pro- No user application. Register bit must be written as 0.
duction device testing.
Notes:
12. The acknowledgment bit is returned by the slave/receiver (W238).
13. Data Bytes 3 to 7 are reserved.
Document #: 38-07219 Rev. *A*
Page 8 of 17
W238
W238 Serial Configuration Map
2. All unused register bits (reserved and N/A) should be written to a “0” level.
1. The serial bits will be read by the clock driver in the following
order:
3. All register bits labeled “Initialize to 0" must be written to
zero during initialization. Failure to do so may result in higher than normal operating current. The controller will read
back the written value.
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 0: Control Register (1 = Enable, 0 = Disable)[14]
Bit
Pin#
Name
Default
Pin Function
Bit 7
-
Reserved
0
Reserved
Bit 6
-
Reserved
0
Reserved
Bit 5
-
Reserved
0
Reserved
Bit 4
-
Reserved
0
Reserved
Bit 3
-
Spread Spectrum
(1 = On/0 = Off)[15]
0
(Disabled/Enabled)
Bit 2
29
DOT
1
(Active/Inactive)
Bit 1
28
USB
1
(Active/Inactive)
Bit 0
-
Reserved
0
Reserved
Byte 1: Control Register (1 = Enable, 0 = Disable)[14]
Bit
Pin#
Name
Default
Pin Description
Bit 7
40
SDRAM7
1
(Active/Inactive)
Bit 6
41
SDRAM6
1
(Active/Inactive)
Bit 5
44
SDRAM5
1
(Active/Inactive)
Bit 4
45
SDRAM4
1
(Active/Inactive)
Bit 3
46
SDRAM3
1
(Active/Inactive)
Bit 2
47
SDRAM2
1
(Active/Inactive)
Bit 1
50
SDRAM1
1
(Active/Inactive)
Bit 0
51
SDRAM0
1
(Active/Inactive)
Notes:
Byte 2: Control Register (1 = Enable, 0 = Disable)
Bit
Pin#
Name
Default
Pin Description
Bit 7
12
3V66_AGP
1
(Active/Inactive)
Bit 6
31
SDRAM12
1
(Active/Inactive)
Bit 5
34
SDRAM11
1
(Active/Inactive)
Bit 4
35
SDRAM10
1
(Active/Inactive)
Bit 3
38
SDRAM9
1
(Active/Inactive)
Bit 2
39
SDRAM8
1
(Active/Inactive)
Bit 1
15
PCI1
1
(Active/Inactive)
Bit 0
--
Reserved
1
(Active/Inactive)
Notes:
14. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be
configured during the normal modes of operation.
15. Spread Spectrum percentage is –0.5%.
Document #: 38-07219 Rev. *A*
Page 9 of 17
W238
Byte 3: Reserved Register (1 = Enable, 0 = Disable)
Bit
Pin#
Name
Default
Pin Description
Bit 7
-
Reserved
0
Reserved
Bit 6
-
Reserved
0
Reserved
Bit 5
-
Reserved
0
Reserved
Bit 4
-
Reserved
0
Reserved
Bit 3
--
Reserved
0
Reserved
Bit 2
--
Reserved
0
Reserved
Bit 1
30
PWRDWN#/
TRISTATE#
1
1 = PWRDWN#
0 = TRISTATE#
Bit 0
--
SDRAM 133 Mode Enable
Disabled =’0’, Enabled =’1’
0
(Disabled/Enabled)
Byte 4: Reserved Register (1 = Enable, 0 = Disable)
Bit
Pin#
Name
Default
Pin Function
Bit 7
-
Reserved
0
Reserved
Bit 6
-
Reserved
0
Reserved
Bit 5
-
Reserved
0
Reserved
Bit 4
-
Reserved
0
Reserved
Bit 3
-
Reserved
0
Reserved
Bit 2
20
PCI4
1
Active/Inactive
Bit 1
19
PCI3
1
Active/Inactive
Bit 0
16
PCI2
1
Active/Inactive
Byte 5: Reserved Register (1 = Enable, 0 = Disable)
Bit
Pin#
Name
Default
Pin Description
Bit 7
-
Reserved
0
Reserved
Bit 6
-
Reserved
0
Reserved
Bit 5
-
Reserved
0
Reserved
Bit 4
-
Reserved
0
Reserved
Bit 3
-
Reserved
0
Reserved
Bit 2
-
Reserved
0
Reserved
Bit 1
-
Reserved
0
Reserved
Bit 0
-
Reserved
0
Reserved
Byte 6: Reserved Register (1 = Enable, 0 = Disable)
Bit
Pin#
Name
Default
Pin Description
Bit 7
-
Reserved
0
Reserved
Bit 6
-
Reserved
0
Reserved
Bit 5
-
Reserved
0
Reserved
Bit 4
-
Reserved
0
Reserved
Bit 3
-
Reserved
0
Reserved
Bit 2
-
Reserved
0
Reserved
Bit 1
-
Reserved
0
Reserved
Bit 0
-
Reserved
0
Reserved
Document #: 38-07219 Rev. *A*
Page 10 of 17
W238
DC Electrical Characteristics [17]
Absolute Maximum DC Power Supply
Parameter
Description
Min.
Max.
Unit
VDD3
3.3V Core Supply Voltage
–0.5
4.6
V
VDDQ2
2.5V I/O Supply Voltage
–0.5
3.6
V
VDDQ3
3.3V Supply Voltage
–0.5
4.6
V
TS
Storage Temperature
–65
150
°C
Min.
Max.
Unit
4.6
V
Absolute Maximum DC I/O
Parameter
Description
Vih3
3.3V Input High Voltage
–0.5
Vil3
3.3V Input Low Voltage
–0.5
V
ESD prot.
Input ESD Protection
2000
V
17
DC Operating Requirements
Parameter
Description
Condition
Min.
Typ.
Max.
Unit
VDD3
3.3V Core Supply Voltage
3.3V±5%
3.135
3.465
V
VDDQ3
3.3V I/O Supply Voltage
3.3V±5%
3.135
3.465
V
VDDQ2
2.5V I/O Supply Voltage
2.5V±5%
2.375
2.625
V
Vih3
3.3V Input High Voltage
VDD3
2.0
VDD + 0.3
V
Vil3
3.3V Input Low Voltage
VSS – 0.3
0.8
V
Iil
Input Leakage Current[16]
0<Vin<VDD3
–5
+5
µA
Voh2
2.5V Output High Voltage
Ioh=(–1 mA)
2.0
Vol2
2.5V Output Low Voltage
Iol=(1 mA)
Voh3
3.3V Output High Voltage
Ioh=(–1 mA)
Vol3
3.3V Output Low Voltage
Iol=(1 mA)
VDD3 = 3.3V±5%
VDDQ2 = 2.5V±5%
V
0.4
V
VDDQ3 = 3.3V±5%
2.4
V
0.4
V
VDDQ3 = 3.3V±5%
Vpoh3
PCI Bus Output High Voltage
Ioh=(–1 mA)
Vpol3
PCI Bus Output Low Voltage
Iol=(1 mA)
Cin
Input Pin Capacitance
Cxtal
Xtal Pin Capacitance
Cout
Output Pin Capacitance
Lpin
Pin Inductance
Ta
Ambient Temperature
IOL
Output Low Current
Document #: 38-07219 Rev. *A*
2.4
V
0.55
13.5
0
V
5
pF
22.5
pF
6
pF
7
nH
No Airflow
0
70
°C
PCI0:7
VOL = 1.5V
20
40
90
mA
REF2X/FS3
VOL = 1.5V
20
40
90
mA
48 MHz
VOL = 1.5V
20
40
90
mA
24 MHz
VOL = 1.5V
20
40
90
mA
SDRAM0:12
VOL = 1.5V
60
100
160
mA
CPU0:1
VOL = 1.25V
25
50
95
mA
Page 11 of 17
W238
DC Operating Requirements
Parameter
IOH
Description
Output High Current
Condition
Min.
Typ.
Max.
Unit
PCI0:7
VOH= 1.5V
20
40
90
mA
REF2X/FS3
VOH= 1.5V
20
40
90
mA
48 MHz
VOH= 1.5V
20
40
90
mA
24 MHz
VOH= 1.5V
20
40
90
mA
SDRAM0:12
VOH= 1.5V
60
100
160
mA
25
50
95
CPU0:1
VOH= 1.25V
Note:
16. Input Leakage Current does not include inputs with pull-up or pull-down resistors.
17. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
Document #: 38-07219 Rev. *A*
mA
Page 12 of 17
W238
AC Electrical Characteristics
TA = 0°C to +70°C, VDDQ3 = 3.3V±5%, VDDQ2= 2.5V±5%
fXTL = 14.31818 MHz
Spread Spectrum function turned off
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output.[18]
Parameter
Description
66.6-MHz Host
100-MHz Host
133-MHz Host
Min.
Max.
Min.
Max.
Min.
Max.
Unit
15.0
15.5
10.0
10.5
7.5
8.0
ns
18
Notes
TPeriod
Host/CPUCLK Period
THIGH
Host/CPUCLK High Time
5.2
N/A
3.0
N/A
1.87
N/A
ns
21
TLOW
Host/CPUCLK Low Time
5.0
N/A
2.8
N/A
1.67
N/A
ns
22
TRISE
Host/CPUCLK Rise Time
0.4
1.6
0.4
1.6
0.4
1.6
ns
TFALL
Host/CPUCLK Fall Time
0.4
1.6
0.4
1.6
0.4
1.6
ns
TPeriod
SDRAM CLK Period
10.0
10.5
10.0
10.5
10.0
10.5
ns
18
THIGH
SDRAM CLK High Time
3.0
N/A
3.0
N/A
3.0
N/A
ns
21
TLOW
SDRAM CLK Low Time
2.8
N/A
2.8
N/A
2.8
N/A
ns
22
TRISE
SDRAM CLK Rise Time
0.4
1.6
0.4
1.6
0.4
1.6
ns
TFALL
SDRAM CLK Fall Time
0.4
1.6
0.4
1.6
0.4
1.6
ns
TPeriod
APIC 33-MHz CLK Period
30.0
N/A
30.0
N/A
30.0
N/A
ns
18
THIGH
APIC 33-MHz CLK High Time
12.0
N/A
12.0
N/A
12.0
N/A
ns
21
TLOW
APIC 33-MHz CLK Low Time
12.0
N/A
12.0
N/A
12.0
N/A
ns
22
TRISE
APIC CLK Rise Time
0.4
1.6
0.4
1.6
0.4
1.6
ns
TFALL
APIC CLK Fall Time
0.4
1.6
0.4
1.6
0.4
1.6
ns
TPeriod
3V66 CLK Period
15.0
16.0
15.0
16.0
15.0
16.0
ns
18, 20
THIGH
3V66 CLK High Time
5.25
N/A
5.25
N/A
5.25
N/A
ns
21
TLOW
3V66 CLK Low Time
5.05
N/A
5.05
N/A
5.05
N/A
ns
22
TRISE
3V66 CLK Rise Time
0.5
2.0
0.5
2.0
0.5
2.0
ns
TFALL
3V66 CLK Fall Time
0.5
2.0
0.5
2.0
0.5
2.0
ns
TPeriod
PCI CLK Period
30.0
N/A
30.0
N/A
30.0
N/A
ns
18, 19
THIGH
PCI CLK High Time
12.0
N/A
12.0
N/A
12.0
N/A
ns
21
TLOW
PCI CLK Low Time
12.0
N/A
12.0
N/A
12.0
N/A
ns
22
TRISE
PCI CLK Rise Time
0.5
2.0
0.5
2.0
0.5
2.0
ns
TFALL
PCI CLK Fall Time
0.5
2.0
0.5
2.0
0.5
2.0
ns
tpZL, tpZH
Output Enable Delay (All outputs)
1.0
10.0
1.0
10.0
1.0
10.0
ns
tpLZ, tpZH
Output Disable Delay
(All outputs)
1.0
10.0
1.0
10.0
1.0
10.0
ns
tstable
All Clock Stabilization from
Power-Up
3
ms
3
3
Notes:
18. Period, jitter, offset, and skew measured on rising edge at 1.25 for 2.5V clocks and at 1.5V for 3.3V clocks.
19. THIGH is measured at 2.0V for 2.5V outputs, 2.4V for 3.3V outputs.
20. TLOW is measured at 0.4V for all outputs.
21. The time specified is measured from when VDDQ3 achieves its nominal operating level (typical condition VDDQ3 = 3.3V) until the frequency output is stable and
operating within specification.
22. TRISE and TFALL are measured as a transition through the threshold region Vol = 0.4V and Voh = 2.0V (1 mA) JEDEC specification.
Document #: 38-07219 Rev. *A*
Page 13 of 17
W238
Group Skew and Jitter Limits
Output Group
Pin-Pin Skew
Max.
Cycle-Cycle
Jitter
Duty Cycle
Nom Vdd
Skew, Jitter
Measure Point
Typical Output
Impedance
CPU
175 ps
250 ps
45/55
2.5V
1.25V
31Ω
SDRAM
250 ps
250 ps
45/55
3.3V
1.5V
22Ω
APIC
250 ps
500 ps
45/55
2.5V
1.25V
21Ω
48MHz
250 ps
500 ps
45/55
3.3V
1.5V
USB 31Ω
Dot 22Ω
3V66
175 ps
500 ps
45/55
3.3V
1.5V
31Ω
PCI
500 ps
500 ps
45/55
3.3V
1.5V
31Ω
REF
N/A
1000 ps
45/55
3.3V
1.5V
21Ω
Output
Buffer
Test Point
Test Load
Clock Output Wave
TPERIOD
Duty Cycle
THIGH
2.0
2.5V Clocking
Interface
1.25
0.4
TLOW
TRISE
TFALL
TPERIOD
Duty Cycle
THIGH
2.4
3.3V Clocking
Interface
1.5
0.4
TLOW
TRISE
TFALL
Figure 10. Output Buffer
Ordering Information
Ordering Code
Package
Name
W238
Document #: 38-07219 Rev. *A*
H
Package Type
56-pin SSOP (300 mils)
Page 14 of 17
W238
Layout Diagram
+2.5V Supply
+3.3V Supply
FB
FB
VDDQ2
VDDQ3
C4
0.005 µF
G
G
C1
G
C2
G
G
10 µF
G
1
2
3
4
5
6
7
8
9
10
G
VDDQ3
5Ω
C5 G
G C6
G
10 µF
0.005 µF
G
G
56
55
G
54
53
G 52
51
50
VDDQ3
V49
G 48
47
G 46
45
44
VDDQ3
V43
G 42
41
40
39
G 38
VDDQ3 V
37
G 36
35
34
VDDQ3
V33
G 32
31
30
G
29
C2
G
VDDQ2
VDDQ2
V
V
G
VDDQ3
V
G
VDDQ3
V
G
11
12
13 G
14
15 G
16 VDDQ3
17 V
18 G
19
20
21 G
22 VDDQ3
23 V Core
24
25 G
26
27
28 G
W238
G
C1
C3
G
G
G
G
G
FB = Dale ILB1206 - 300 (300Ω @ 100 MHz)
C1 & C3 = 10–22 µF
C2 & C4 = 0.005 µF
G = VIA to GND plane layer
C5 = 47 µF
C6 = 0.1 µF
V =VIA to respective supply plane layer
Note: Each supply plane or strip should have a ferrite bead and capacitors
Document #: 38-07219 Rev. *A*
Page 15 of 17
W238
Package Diagram
56-Pin Shrink Small Outline Package (SSOP, 300 mils)
Summary of nominal dimensions in inches:
Body Width: 0.296
Lead Pitch: 0.025
Body Length: 0.625
Body Height: 0.102
Document #: 38-07219 Rev. *A*
Page 16 of 17
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
W238
Document Title: W238 FTG for Integrated Core Logic with 133-MHz FSB
Document Number: 38-07219
REV.
ECN NO.
Issue
Date
Orig. of
Change
**
110484
10/21/01
SZV
Change from Spec number: 38-00881 to 38-07219
*A
122836
12/15/02
RBI
Added power-up requirements to electrical characteristics information.
Document #: 38-07219 Rev. *A*
Description of Change
Page 17 of 17