PRELIMINARY W147G Frequency Generator for Integrated Core Logic Features Key Specifications • Maximized EMI suppression using Cypress’s Spread Spectrum Technology • Low jitter and tightly controlled clock skew • Highly integrated device providing clocks required for CPU, core logic, and SDRAM • Three copies of CPU clock at 66/100 MHz • Nine copies of 100-MHz SDRAM clocks • Eight copies of PCI clock • Two copies of synchronous APIC clock • Two copies of 48-MHz clock (non-spread spectrum) optimized for USB reference input and video dot clock • Two copies of 66-MHz fixed clock • One copy of 14.31818-MHz reference clock • Power-down control • I2C interface for turning off unused clocks CPU, SDRAM Outputs Cycle-to-Cycle Jitter: ..............250 ps APIC, 48MHz, 3V66, PCI Outputs Cycle-to-Cycle Jitter: ...................................................500 ps APIC, 48MHz, SDRAM Output Skew: .........................250 ps CPU, 3V66 Output Skew:............................................175 ps PCI Output Skew:........................................................500 ps CPU to SDRAM Skew (@ 100 MHz):.................4.5 to 5.5 ns CPU to 3V66 Skew (@ 66 MHz): .......................7.0 to 8.0 ns 3V66 to PCI Skew (3V66 lead):..........................1.5 to 3.5 ns PCI to APIC Skew: .....................................................±0.5 ns Table 1. Pin Selectable Functions Block Diagram SEL1 SEL0 Function 0 0 Three-state 0 1 Test 1 0 66-MHz CPU 1 1 100-MHz CPU Pin Configuration VDDQ3 X1 X2 REF/APICDIV XTAL OSC PLL REF FREQ VDDQ2 I2C Logic Divider, Delay, and Phase Control Logic 2 CPU0:1 CPU2_ITP 2 APIC0:1 VDDQ3 SEL0:1 PLL 1 2 3V66_0:1 PCI0_ICH PCI1:7 7 DCLK PWRDWN# SDRAM0:7 8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 W147G SDATA SCLK REF/APICDIV VDDQ3 X1 X2 GND GND 3V66_0 3V66_1 VDDQ3 VDDQ3 PCI0_ICH PCI1 PCI2 GND PCI3 PCI4 GND PCI5 PCI6 PCI7 VDDQ3 VDD3 GND GND USB DOT VDDQ3 SEL0 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 GND APIC0 APIC1 VDDQ2 CPU0 VDDQ2 CPU1 CPU2_ITP GND GND SDRAM0 SDRAM1 VDDQ3 SDRAM2 SDRAM3 GND SDRAM4 SDRAM5 VDDQ3 SDRAM6 SDRAM7 GND DCLK VDDQ3 PWRDWN# SCLK SDATA SEL1 VDDQ3 USB PLL2 DOT Cypress Semiconductor Corporation Document #: 38-07165 Rev. *A • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 21,2002 PRELIMINARY W147G Pin Definitions Pin Name Pin No. Pin Type REF/APICDIV 1 I/O X1 3 I Crystal Input: This pin has dual functions. It can be used as an external 14.318-MHz crystal connection as an external reference frequency input. X2 4 I Crystal Output: An input connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. PCI0_ICH, PCI1:7 11, 12, 13, 15, 16, 18, 19. 20 O PCI Clock 0 through 7: 3.3V 33-MHz PCI clock outputs. PCI1:7 can be individually turned off via I2C interface. 3V66_0:1 7, 8 O 66-MHz Clock Output: 3.3V fixed 66-MHz clock. Pin Description Reference Clock: 3.3V 14.318-MHz clock output. This pin doubles as the select strap for APIC clock frequency. If strapped LOW during power up, APIC clock runs at half PCI clock speed. Otherwise, APIC clocks run at PCI clock speed. USB 25 O USB Clock Output: 3.3V fixed 48-MHz, non-spread spectrum USB clock outputs. DOT 26 O Dot Clock Output: 3.3V 48-MHz, non-spread spectrum signal. 28, 29 I Clock Function Selection pins: LVTTL-compatible input to select device functions. See Table 1 for detailed descriptions. PWRDWN# 32 I Power Down Control: LVTTL-compatible asynchronous input that places the device in power-down mode when held LOW. CPU2_ITP, CPU0:1 49, 52, 50 O CPU Clock Outputs: Clock outputs for the host bus interface and integrated test port. Output frequencies run at 66 MHz or 100 MHz depending on the configuration of SEL0:1. Voltage swing set by VDDQ2. SDRAM0:7, DCLK 46, 45, 43, 42, 40, 39, 37, 36, 34 O APIC0:1 55, 54 O Sychronous APIC Clock Outputs: Clock outputs running divide synchronous with the PCI clock outputs. Output frequency is controlled by the strap option on REF. Voltage swing set by VDDQ2. SDATA 30 I/O Data pin for I2C circuitry. SCLK 31 I Clock pin for I2C circuitry. 2, 9, 10, 21, 27, 33, 38, 44 P 3.3V Power Connection: Power supply for SDRAM output buffers, PCI output buffers, 3V66 output buffers, reference output buffers, and 48-MHz output buffers. Connect to 3.3V. 22 P 3.3V Power Connection: Power supply for core logic, PLL circuitry. Connect to 3.3V. 51, 53 P 2.5V Power Connection: Power supply for IOAPIC and CPU output buffers. Connect to 2.5V or 3.3V. 5, 6, 14, 17, 23, 24, 35, 41, 47, 48, 56 G Ground Connections: Connect all ground pins to the common system ground plane. SEL0:1 VDDQ3 VDD3 VDDQ2 GND Document #: 38-07165 Rev. *A SDRAM Clock Outputs: 3.3V outputs running at 100 MHz. SDRAM0:7 can be individually turned off via I2C interface. Page 2 of 13 PRELIMINARY W147G VDD Output Strapping Resistor Series Termination Resistor 10 kΩ (Load Option 1) Clock Load W147G Power-on Reset Timer Output Buffer Hold Output Low Output Three-state Q 10kΩ (Load Option 0) D Data Latch Figure 1. Input Logic Selection Through Resistor Load Option Overview The W147G is a highly integrated frequency timing generator, supplying all the required clock sources for an Intel® architecture platform using graphics integrated core logic. Functional Description I/O Pin Operation REF/APICDIV is a dual purpose l/O pin. Upon power-up the pin acts as a logic input. If the pin is strapped to a LOW state externally, APIC clock outputs will run divide synchronously at half PCI clock speed. If it is pulled HIGH, APIC clock will run synchronous to PCI clocks. An external 10-kΩ strapping resistor should be used. Figure 1 shows a suggested method for strapping resistor connections. After 2 ms, the pin becomes an output. Assuming the power supply has stabilized by then, the specified output frequency is delivered on the pins. If the power supply has not yet reached full value, output frequency initially may be below target but will increase to target once supply voltage has stabilized. In either case, a short output clock cycle may be produced from the CPU clock outputs when the outputs are enabled. Pin Selectable Functions Table 1 outlines the device functions selectable through SEL0:1. Specific outputs available at each pin is detailed in Table 2 below. The SEL0 pin requires a 220Ω pull-up resistor to 3.3V for the W147G to sense the maximum host bus frequency of the processor and configure itself accordingly. Table 2. CK Whitney Truth Table CPU SDRAM 3V66 PCI 48MHz REF APIC[1] Notes SEL1 SEL0 0 0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 2 0 1 TCLK/2 TCLK/2 TCLK/3 TCLK/6 TCLK/2 TCLK TCLK/6 4, 5 1 0 66 MHz 100 MHz 66 MHz 33 MHz 48 MHz 14.318 MHz 16.67 MHz 3, 6, 7 1 1 100 MHz 100 MHz 66 MHz 33 MHz 48 MHz 14.318 MHz 16.67 MHz 3, 6, 7 Notes: 1. APIC clock frequency determined by the strap option on the REF/APICDIV input pin. 2. Provided for board level “bed of nails” testing. 3. “Normal” mode of operation. 4. TCLK is a test clock overdriven on the XTAL_IN input during test mode. 5. Required for DC output impedance verification. 6. Range of reference frequency allowed is: min. = 14.316 MHz, nominal = 14.31818 MHz, max. = 14.32 MHz. 7. Frequency accuracy of 48 MHz must be +167 PPM to match USB default. Document #: 38-07165 Rev. *A Page 3 of 13 PRELIMINARY Offsets Among Clock Signal Groups Figure 2 and Figure 3 represent the phase relationship among the different groups of clock outputs from W147G when it is providing a 66-MHz CPU clock and a 100-MHz CPU clock, 10 ns 0 ns 20 ns W147G respectively. It should be noted that when CPU clock is operating at 100 MHz, CPU clock output is 180 degrees out of phase with SDRAM clock outputs. 30 ns 40 ns CPU 66 Period CPU 66-MHz SDRAM 100-MHz SDRAM 100 Period Hub-PCI 3V66 66-MHz PCI 33-MHz REF 14.318-MHz USB 48-MHz APIC 33-MHz Figure 2. Group Offset Waveforms (66-MHz CPU Clock) 0 ns CPU 100-MHz 10 ns 30 ns 40 ns CPU 100 Period SDRAM 100-MHz 3V66 66-MHz 20 ns SDRAM 100 Period Hub-PCI PCI 33-MHz REF 14.318-MHz USB 48-MHz APIC 33-MHz Figure 3. Group Offset Waveforms (100-MHz CPU Clock) Document #: 38-07165 Rev. *A Page 4 of 13 PRELIMINARY W147G Power Down Control W147G provides one PWRDWN# signal to place the device in low-power mode. In low-power mode, the PLLs are turned off and all clock outputs are driven LOW. 0ns 25ns 50ns 75ns Center 1 2 VCO Internal CPU 100MHz 3V66 66MHz PCI 33MHz APIC 33MHz PwrDwn SDRAM 100MHz REF 14.318MHz USB 48MHz Figure 4. W147G PWRDWN# Timing Diagram[8, 9, 10, 11] Table 3. W147G Maximum Allowed Current Max. 2.5V supply consumption Max. discrete cap loads, VDDQ2 = 2.625V All static inputs = VDDQ3 or VSS Max. 3.3V supply consumption Max. discrete cap loads VDDQ3 = 3.465V All static inputs = VDDQ3 or VSS Powerdown Mode (PWRDWN# = 0) 100 µA 200 µA Full Active 66 MHz SEL1,0 = 10 (PWRDWN# =1) 70 mA 280 mA Full Active 100 MHz SEL1,0 =11 (PWRDWN# = 1) 100 mA 280 mA W147 Condition Notes: 8. Once the PWRDWN# signal is sampled LOW for two consecutive rising edges of CPU clock, clocks of interest should be held LOW on the next HIGH-to-LOW transition. 9. PWR_DWN# is an asynchronous input and metastable conditions could exist. This signal is synchronized inside W147G. 10. The shaded sections on the SDRAM, REF, and USB clocks indicate “don’t care” states. 11. Diagrams shown with respect to 100 MHz. Similar operation when CPU is 66 MHz. Document #: 38-07165 Rev. *A Page 5 of 13 PRELIMINARY W147G Spread Spectrum Clocking Where P is the percentage of deviation and F is the frequency in MHz where the reduction is measured. The device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. By increasing the bandwidth of the fundamental and its harmonics, the amplitudes of the radiated electromagnetic emissions are reduced. This effect is depicted in Figure 5. The output clock is modulated with a waveform depicted in Figure 6. This waveform, as discussed in “Spread Spectrum Clock Generation for the Reduction of Radiated Emissions” by Bush, Fessler, and Hardin produces the maximum reduction in the amplitude of radiated electromagnetic emissions. The deviation selected for this chip is –0.5% of the selected frequency. Figure 6 details the Cypress spreading pattern. Cypress does offer options with more spread and greater EMI reduction. Contact your local Sales representative for details on these devices. As shown in Figure 5, a harmonic of a modulated clock has a much lower amplitude than that of an unmodulated signal. The reduction in amplitude is dependent on the harmonic number and the frequency deviation or spread. The equation for the reduction is dB = 6.5 + 9*log10(P) + 9*log10(F) Spread Spectrum clocking is activated or deactivated by selecting the appropriate value for bit 3 in data byte 0 of the I2C data stream. Refer to page 8 for more details. EMI Reduction Spread Spectrum Enabled NonSpread Spectrum Figure 5. Typical Clock and SSFTG Comparison 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% FREQUENCY MAX. MIN. Figure 6. Typical Modulation Profile Document #: 38-07165 Rev. *A Page 6 of 13 PRELIMINARY W147G 1 bit 7 bits 1 1 8 bits 1 Start bit Slave Address R/W Ack Command Code Ack Ack Data Byte 1 Ack Data Byte 2 Ack 1 bit 8 bits 1 8 bits 1 ... Byte Count = N Data Byte N Ack Stop 8 bits 1 1 Figure 7. An Example of a Block Write[12] Serial Data Interface The W147G features a two-pin, serial data interface that can be used to configure internal register settings that control particular device functions. Data Protocol The clock driver serial protocol accepts only block writes from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. Indexed bytes are not allowed. A block write begins with a slave address and a write condition. After the command code the core logic issues a byte count which describes how many more bytes will follow in the message. If the host had 20 bytes to send, the first byte would be the number 20 (14h), followed by the 20 bytes of data. The byte count may not be 0. A block write command is allowed to transfer a maximum of 32 data bytes. The slave receiver address for W147G is 11010010. Figure 7 shows an example of a block write. The command code and the byte count bytes are required as the first two bytes of any transfer. W147G expects a command code of 0000 0000. The byte count byte is the number of additional bytes required for the transfer, not counting the command code and byte count bytes. Additionally, the byte count byte is required to be a minimum of 1 byte and a maximum of 32 bytes to satisfy the above requirement. Table 4 shows an example of a possible byte count value. A transfer is considered valid after the acknowledge bit corresponding to the byte count is read by the controller. The command code and byte count bytes are ignored by the W147G. However, these bytes must be included in the data write sequence to maintain proper byte allocation. Table 4. Example of Possible Byte Count Value Byte Count Byte Notes MSB LSB 0000 0000 Not allowed. Must have at least one byte. 0000 0001 Data for functional and frequency select register (currently byte 0 in spec) 0000 0010 Reads first two bytes of data. (byte 0 then byte 1) 0000 0011 Reads first three bytes (byte 0, 1, 2 in order) 0000 0100 Reads first four bytes (byte 0, 1, 2, 3 in order) 0000 0101 Reads first five bytes (byte 0, 1, 2, 3, 4 in order)[13] 0000 0110 Reads first six bytes (byte 0, 1, 2, 3, 4, 5 in order)[13] 0000 0111 Reads first seven bytes (byte 0, 1, 2, 3, 4, 5, 6 in order) 0010 0000 Max byte count supported = 32 Table 5. Serial Data Interface Control Functions Summary Control Function Description Common Application Output Disable Any individual clock output(s) can be disabled. Disabled outputs are actively held LOW. Unused outputs are disabled to reduce EMI and system power. Examples are clock outputs to unused PCI slots. Spread Spectrum Enabling Enables or disables spread spectrum clocking. For EMI reduction. (Reserved) Reserved function for future device revision or pro- No user application. Register bit must be written as 0. duction device testing. Notes: 12. The acknowledgment bit is returned by the slave/receiver (W147G). 13. Data Bytes 3 to 7 are reserved. Document #: 38-07165 Rev. *A Page 7 of 13 PRELIMINARY W147G W147G Serial Configuration Map 2. All unused register bits (reserved and N/A) should be written to a “0” level. 1. The serial bits will be read by the clock driver in the following order: 3. All register bits labeled “Initialize to 0" must be written to zero during initialization. Failure to do so may result in higher than normal operating current. Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0 4. Only Byte 0, 1 and 2 are defined in W147G Byte 3 to Byte 7 are reserved and must be written to “zero.” Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 0: Control Register (1 = Enable, 0= Disable)[14] Bit Pin# Name Pin Description Bit 7 - Reserved (Active/Inactive) Bit 6 - Reserved (Active/Inactive) Bit 5 - Reserved (Active/Inactive) Bit 4 - Reserved (Active/Inactive) Bit 3 - Spread Spectrum (1=On/0=Off) (Active/Inactive) Bit 2 26 DOT (Active/Inactive) Bit 1 25 USB (Active/Inactive) Bit 0 49 CPU2_ITP (Active/Inactive) Byte 1: Control Register (1 = Enable, 0= Disable)[14] Bit Pin# Name Pin Description Bit 7 36 SDRAM7 (Active/Inactive) Bit 6 37 SDRAM6 (Active/Inactive) Bit 5 39 SDRAM5 (Active/Inactive) Bit 4 40 SDRAM4 (Active/Inactive) Bit 3 42 SDRAM3 (Active/Inactive) Bit 2 43 SDRAM2 (Active/Inactive) Bit 1 45 SDRAM1 (Active/Inactive) Bit 0 46 SDRAM0 (Active/Inactive) Byte 2: Control Register (1 = Enable, 0= Disable)[14] Bit Pin# Name Pin Description Bit 7 20 PCI7 (Active/Inactive) Bit 6 19 PCI6 (Active/Inactive) Bit 5 18 PCI5 (Active/Inactive) Bit 4 16 PCI4 (Active/Inactive) Bit 3 15 PCI3 (Active/Inactive) Bit 2 13 PCI2 (Active/Inactive) Bit 1 12 PCI1 (Active/Inactive) Bit 0 - Reserved (Active/Inactive) Note: 14. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. Document #: 38-07165 Rev. *A Page 8 of 13 PRELIMINARY W147G DC Electrical Characteristics[15] DC parameters must be sustainable under steady state (DC) conditions. Absolute Maximum DC Power Supply Parameter Description Min. Max. Unit VDD3 3.3V Core Supply Voltage –0.5 4.6 V VDDQ2 2.5V I/O Supply Voltage –0.5 3.6 V VDDQ3 3.3V Supply Voltage –0.5 4.6 V TS Storage Temperature –65 150 °C Min. Max. Unit –0.5 4.6 V Absolute Maximum DC I/O Parameter Description Vih3 3.3V Input High Voltage Vil3 3.3V Input Low Voltage –0.5 V ESD prot. Input ESD Protection 2000 V DC Operating Requirements Condition Min. Max. Unit VDD3 Parameter 3.3V Core Supply Voltage Description 3.3V±5% 3.135 3.465 V VDDQ3 3.3V I/O Supply Voltage 3.3V±5% 3.135 3.465 V VDDQ2 2.5V I/O Supply Voltage 2.5V±5% 2.375 2.625 V Vih3 3.3V Input High Voltage VDD3 2.0 VDD+0.3 V Vil3 3.3V Input Low Voltage VSS–0.3 0.8 V 0<Vin<VDDQ3 –5 +5 µA 2.0 VDD3 = 3.3V±5% Iil Input Leakage Current [16] VDDQ2 = 2.5V±5% Voh2 2.5V Output High Voltage Ioh=(–1 mA) Vol2 2.5V Output Low Voltage Iol=(1 mA) Voh3 3.3V Output High Voltage Ioh=(–1 mA) Vol3 3.3V Output Low Voltage Iol=(1 mA) V 0.4 V VDDQ3 = 3.3V±5% 2.4 V 0.4 V VDDQ3 = 3.3V±5% Vpoh3 PCI Bus Output High Voltage Ioh=(–1 mA) Vpol3 PCI Bus Output Low Voltage Iol=(1 mA) Cin Input Pin Capacitance Cxtal Xtal Pin Capacitance Cout Output Pin Capacitance Lpin Pin Inductance 2.4 V 0.55 V 5 pF 13.5 22.5 pF 6 pF 0 7 nH Ambient Temperature No Airflow 0 70 Ta Note: 15. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 16. Input Leakage Current does not include inputs with pull-up or pull-down resistors. Document #: 38-07165 Rev. *A °C Page 9 of 13 PRELIMINARY W147G AC Electrical Characteristics[15] TA = 0°C to +70°C, VDDQ3 = 3.3V±5%, VDDQ2= 2.5V±5% fXTL = 14.31818 MHz Spread Spectrum function turned off AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output.[17] Parameter Description 66.6-MHz Host 100-MHz Host Min. Max. Min. Max. Unit Notes TPeriod Host/CPUCLK Period 15.0 15.5 10.0 10.5 ns 17 THIGH Host/CPUCLK High Time 5.2 N/A 3.0 N/A ns 20 TLOW Host/CPUCLK Low Time 5.0 N/A 2.8 N/A ns 21 TRISE Host/CPUCLK Rise Time 0.4 1.6 0.4 1.6 ns TFALL Host/CPUCLK Fall Time 0.4 1.6 0.4 1.6 ns TPeriod SDRAM CLK Period 10.0 10.5 10.0 10.5 ns 17 THIGH SDRAM CLK High Time 3.0 N/A 3.0 N/A ns 20 TLOW SDRAM CLK Low Time 2.8 N/A 2.8 N/A ns 21 TRISE SDRAM CLK Rise Time 0.4 1.6 0.4 1.6 ns TFALL SDRAM CLK Fall Time 0.4 1.6 0.4 1.6 ns TPeriod APIC CLK Period 60.0 64.0 60.0 64.0 ns 17 THIGH APIC CLK High Time 25.5 N/A 25.5 N/A ns 20 TLOW APIC CLK Low Time 25.3 N/A 25.3 N/A ns 21 TRISE APIC CLK Rise Time 0.4 1.6 0.4 1.6 ns TFALL APIC CLK Fall Time 0.4 1.6 0.4 1.6 ns TPeriod 3V66 CLK Period 15.0 16.0 15.0 16.0 ns 17, 19 THIGH 3V66 CLK High Time 5.25 N/A 5.25 N/A ns 20 TLOW 3V66 CLK Low Time 5.05 N/A 5.05 N/A ns 21 TRISE 3V66 CLK Rise Time 0.5 2.0 0.5 2.0 ns TFALL 3V66 CLK Fall Time 0.5 2.0 0.5 2.0 ns TPeriod PCI CLK Period 30.0 N/A 30.0 N/A ns THIGH PCI CLK High Time 12.0 N/A 12.0 N/A ns 20 TLOW PCI CLK Low Time 12.0 N/A 12.0 N/A ns 21 TRISE PCI CLK Rise Time 0.5 2.0 0.5 2.0 ns TFALL PCI CLK Fall Time 0.5 2.0 0.5 2.0 ns tpZL, tpZH Output Enable Delay (All outputs) 1.0 10.0 1.0 10.0 ns tpLZ, tpZH Output Disable Delay (All outputs) 1.0 10.0 1.0 10.0 ns tstable All Clock Stabilization from Power-Up 3 ms 3 17, 18 Notes: 17. Period, jitter, offset, and skew measured on rising edge at 1.25 for 2.5V clocks and at 1.5V for 3.3V clocks. 18. THIGH is measured at 2.0V for 2.5V outputs, 2.4V for 3.3V outputs. 19. TLOW is measured at 0.4V for all outputs. 20. The time specified is measured from when VDDQ3 achieves its nominal operating level (typical condition VDDQ3 = 3.3V) until the frequency output is stable and operating within specification. 21. TRISE and TFALL are measured as a transition through the threshold region Vol = 0.4V and Voh = 2.0V (1 mA) JEDEC specification. Document #: 38-07165 Rev. *A Page 10 of 13 PRELIMINARY W147G Group Skew and Jitter Limits Output Group Pin-Pin Skew Max Cycle-Cycle Jitter Duty Cycle Nom Vdd Skew, Jitter Measure Point CPU 175 ps 250 ps 45/55 2.5V 1.25V SDRAM 250 ps 250 ps 45/55 3.3V 1.5V APIC 250 ps 500 ps 45/55 2.5V 1.25V 48MHz 250 ps 500 ps 45/55 3.3V 1.5V 3V66 175 ps 500 ps 45/55 3.3V 1.5V PCI 500 ps 500 ps 45/55 3.3V 1.5V REF N/A 1000 ps 45/55 3.3V 1.5V Output Buffer Test Point Test Load Clock Output Wave TPERIOD Duty Cycle THIGH 2.0 2.5V Clocking Interface 1.25 0.4 TLOW TRISE TFALL TPERIOD Duty Cycle THIGH 2.4 3.3V Clocking Interface 1.5 0.4 TLOW TRISE TFALL Figure 8. Output Buffer Ordering Information Ordering Code Package Name W147G H Package Type 56-pin SSOP (300 mils) Intel is a registered trademark of Intel Corporation. Document #: 38-07165 Rev. *A Page 11 of 13 PRELIMINARY W147G Package Diagram 56-Pin Shrink Small Outline Package (SSOP, 300 mils) Summary of nominal dimensions in inches: Body Width: 0.296 Lead Pitch: 0.025 Body Length: 0.625 Body Height: 0.102 Document #: 38-07165 Rev. *A Page 12 of 13 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY W147G Document Title: W147G Frequency Generator for Integrated Core Logic Document Number: 38-07165 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 110275 11/05/01 SZV Change from Spec number: 38-00820 to 38-07165 *A 122806 12/21/02 RBI Add Power up Requirements to Operating Conditions Information Document #: 38-07165 Rev. *A Page 13 of 13