Data Sheet

AK8180B
2.5V, 3.3V LVCMOS 1:9
Clock Fanout Buffer
AK8180B
Features
Description
The AK8180B is a member of AKM’s LVCMOS
clock fanout buffer family designed for telecom,
networking and computer applications, requiring a
range of clocks with high performance and low
skew. The AK8180B distributes 9 buffered clocks
up to 350MHz. The 9 outputs can drive terminated
50 W clock lines. The CLK_STOP control allows
the output signal to start and stop only in a logic
low state. The OE control sets the outputs to
high-impedance mode.
9 LVCMOS outputs
Selectable LVCMOS inputs
2.5V or 3.3V power supply
Clock frequency up to 350MHz
Output-to-output skew : 150ps max
Synchronous output stop in logic state
High-impedance output control
Drive up to 18 series terminated clock lines
Operating Temperature Range: -40 to +85℃
Package: 32-pin LQFP (Pb free)
Pin compatible with MPC9447
AK8180B are derived from AKM’s long-termexperienced clock device technology, and enable
clock output to perform low skew. The AK8180B is
available in a 7mm x 7mm 32-pin LQFP package.
Block Diagram
CCLK0
Q0
0
CLK
STOP
GND
CCLK1
1
Q1
Q2
GND
Q3
VDD
Q4
CLK_SEL
Q5
Q6
VDD
CLK_STOP
SYNC
Q7
Q8
VDD
OE
All pull-up/down resisters = 25k
MS1301-E-00
May-2011
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AK8180B
Pin Descriptions
Package: 32-Pin LQFP(Top View)
Pin No.
Pin Name
Pin
Type
Pullup
/down
Description
1
GND
--
--
2
CLK_SEL
IN
PU
Clock Input Select
Ground
3
CCLK0
IN
PD
Clock Input (LVCMOS)
4
CCLK1
IN
PD
Clock Input (LVCMOS)
5
CLK_STOP
IN
PU
Clock Output Disable (Active low)
6
OE
IN
PU
Clock Output Enable (Disable=High impedance)
7
VDD
--
--
Power supply
8,
GND
--
--
Ground
9
GND
--
--
Ground
10
VDD
--
--
Power supply
11
Q8
OUT
--
Clock output
12
GND
--
--
Ground
PU: Pull up PD: Pull down
(continued on next page)
May-2011
MS1301-E-00
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AK8180B
Pin No.
Pin Name
Pin
Type
Pullup
/down
Description
13
Q7
OUT
--
Clock output
14
VDD
--
--
Power supply
15
Q6
OUT
--
Clock output
16
GND
--
--
Ground
17
GND
--
--
Ground
18
VDD
--
--
Power supply
19
Q5
OUT
--
Clock output
20
GND
--
--
Ground
21
Q4
OUT
--
Clock output
22
VDD
--
--
Power supply
23
Q3
OUT
--
Clock output
24
GND
--
--
Ground
25
GND
--
--
Ground
26
Q2
OUT
--
Clock output
27
VDD
--
--
Power supply
28
Q1
OUT
--
Clock output
29
GND
--
--
Ground
30
Q0
OUT
--
Clock output
31
VDD
--
--
Power supply
32
GND
--
--
Ground
Ordering Information
Part Number
Marking
Shipping
Packaging
Package
Temperature
Range
AK8180B
AK8180B
Tape and Reel
32-pin LQFP
-40 to 85 ℃
MS1301-E-00
May-2011
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AK8180B
Absolute Maximum Rating
Over operating free-air temperature range unless otherwise noted (1)
Items
Supply voltage
Input voltage
Symbol
Ratings
Unit
VDD
-0.3 to 4.6
V
Vin
GND-0.3 to VDD+0.3
V
IIN
±10
mA
Tstg
-55 to 130
°C
Input current (any pins except supplies)
Storage temperature
Note
(1) Stress beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
These are stress ratings only. Functional operation of the device at these or any other conditions beyond those
indicated under “Recommended Operating Conditions” is not implied. Exposure to absolute-maximum-rating
conditions for extended periods may affect device reliability. Electrical parameters are guaranteed only over the
recommended operating temperature range.
ESD Sensitive Device
This device is manufactured on a CMOS process, therefore, generically susceptible to
damage by excessive static voltage. Failure to observe proper handling and
installation procedures can cause damage. AKM recommends that this device is handled with
appropriate precautions.
Recommended Operation Conditions
Parameter
Operating temperature
Supply voltage (1)
Conditions
Symbol
Min
Ta
Typ
-40
VDD
VDD±5%
(1) Power of 2.5V or 3.3V requires to be supplied from a single source.
should be located close to each VDD pin.
Max
Unit
85
°C
2.375
2.5
2.625
3.135
3.3
3.465
V
A decoupling capacitor of 0.01mF for power supply line
General Specification
Parameter
Symbol
Conditions
Min
Typ
Unit
Output Termination Voltage
VTT
ESD Protection 1
MM
Machine model
200
V
ESD Protection 2
HBM
Human Body Model
2000
V
200
mA
Latch-Up Immunity
Power Dissipation Capacitance
VDD/2
Max
LU
Per output
Input Capacitance
May-2011
V
10
pF
4.0
pF
MS1301-E-00
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AK8180B
Power Supply Current <3.3V>
Parameter
Full operation
(1)(2)
Min
CCLK0=350MHz
CLK_SEL=L
IDD1
(1) The outputs have no loads.
Conditions
Symbol
(1)
Quiescent state
VDD= 3.3V±5%, Ta: -40 to +85℃
IDD2
Typ
Max
Unit
120
140
mA
1.0
2.0
mA
MAX
Unit
(2) All inputs are in default state by the internal pull up/down resisters.
DC Characteristics <3.3V>
All specifications at VDD= 3.3V±5%,
Parameter
Ta: -40 to +85℃, unless otherwise noted
Symbol
Conditions
MIN
TYP
High Level Input Voltage
VIH
LVCMOS
2.0
VDD+0.3
V
Low Level Input Voltage
VIL
LVCMOS
-0.3
0.8
V
IL 1
Vin=GND or VDD
-300
+300
μA
Input Current
(1)
High Level Output Voltage
Low Level Output Voltage
VOH
IOH= -24mA
VOL
IOL= +24mA
IOL= +12mA
(2)
2.4
V
0.55
0.30
Output Impedance
V
W
17
(1) Input pull-up / pull down resistors influence input current.
(2) The AK8180B is capable of driving 50 W transmission lines of the incident edge. Each output drives one 50 W parallel
terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 W series
terminated transmission lines(for VDD=3.3V) or one 50 W series terminated transmission line(for VDD=2.5V).
AC Characteristics <3.3V> (1)
All specifications at VDD= 3.3V±5%,
Parameter
Ta: -40 to +85℃, unless otherwise noted
Symbol
Input Frequency
Conditions
MIN
fIN
Pin: CCLK
0
tpwIN
Pin: CCLK
1.4
trIN,tfOUT
Pin: CCLK
Output Frequency
fOUT
Pin: Q0-8
Propagation Delay
tPLH, tPHL
CCLK to any Q
Input Pulse Width
Input Rise/Fall time
(3)
TYP
Unit
350
MHz
ns
0.8 to 2.0V
0
0.8
MAX
1.6
1.0
ns
350
MHz
2.8
ns
Output Disable Time
tPLZ,tPHZ
11
ns
Output Enable Time
tPZL,tPZH
11
ns
Setup Time
tS
CCLK to CLK_STOP
0.0
ns
Hold Time
tH
CCLK to CLK_STOP
1.0
ns
Output-to-Output Skew
tskPP
150
ps
Device-to-Device Skew
tskD
2.0
ns
Output Pulse Skew (4)
tskO
CCLK
300
ps
Output Duty Cycle
DCOUT
fOUT < 170MHz
55
%
Output Rise/Fall Time
tr, tf
0.55 to 2.4V
Cycle-to-Cycle Jitter
tJITCC
1σ
DCREF =50%
45
50
0.1
1.0
6
ns
ps
(1) AC characteristics apply for parallel output termination of 50 W to VTT.
(2) Vcmr(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within
the Vcmr range and the input swing lies within the Vpp(AC) specification. Violation of Vcmr or Vpp impacts tPLH/PHL and tskD.
(3) Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew,
input pulse width, output duty cycle and maximum frequency specifications.
(4) Output pulse skew tskO is the absolute difference of the propagation delay times:| tPLH - tPHL |.
MS1301-E-00
May-2011
-5-
AK8180B
Power Supply Current <2.5V>
Parameter
Full operation
(1)(2)
Min
CCLK0=350MHz
CLK_SEL=L
IDD1
(1) The outputs have no loads.
Conditions
Symbol
(1)
Quiescent state
VDD= 2.5V±5%, Ta: -40 to +85℃
IDD2
Typ
Max
Unit
95
115
mA
0.7
1.3
mA
MAX
Unit
VDD+0.3
V
(2) All inputs are in default state by the internal pull up/down resisters.
DC Characteristics <2.5V>
All specifications at VDD= 2.5V±5%,
Parameter
Ta: -40 to +85℃, unless otherwise noted
Symbol
Conditions
MIN
TYP
VIH
LVCMOS
VIL
LVCMOS
-0.3
0.7
V
IL 1
Vin=GND or VDD
-300
+300
μA
High Level Output Voltage
VOH
IOH= -15mA
Low Level Output Voltage
VOL
IOL= +15mA
High Level Input Voltage
Low Level Input Voltage
Input Current
(1)
1.7
(2)
1.8
V
0.6
Output Impedance
V
W
19
(1) Input pull-up / pull down resistors influence input current.
(2) The AK8180B is capable of driving 50 W transmission lines of the incident edge. Each output drives one 50 W parallel
terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 W series
terminated transmission lines(for VDD=3.3V) or one 50 W series terminated transmission lines(for VDD=2.5V).
AC Characteristics <2.5V> (1)
All specifications at VDD= 2.5V±5%,
Parameter
Ta: -40 to +85℃, unless otherwise noted
Symbol
Input Frequency
Conditions
MIN
TYP
MAX
Unit
350
MHz
fIN
Pin: CCLK
0
tpwIN
Pin: CCLK
1.4
trIN,tfOUT
Pin: CCLK
Output Frequency
fOUT
Pin: Q0-8
Propagation Delay
tPLH, tPHL
CCLK to any Q
Output Disable Time
tPLZ,tPHZ
Output Enable Time
tPZL,tPZH
Setup Time
tS
CCLK to CLK_STOP
0.0
ns
Hold Time
tH
CCLK to CLK_STOP
1.0
ns
Output-to-Output Skew
tskPP
Input Pulse Width
Input Rise/Fall time
(3)
ns
0.8 to 2.0V
0
0.9
1.8
1.0
ns
350
MHz
3.6
ns
11
ns
11
Device-to-Device Skew
tskD
Output Pulse Skew (4)
tskO
CCLK
Output Duty Cycle
DCOUT
DCREF =50%
45
Output Rise/Fall Time
tr, tf
0.6 to 1.8V
0.1
Cycle-to-Cycle Jitter
tJITCC
1σ
50
150
ps
2.7
ns
200
ps
55
%
1.0
10
ns
ns
ps
(1) AC characteristics apply for parallel output termination of 50 W to VTT.
(2) Vcmr(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within
the Vcmr range and the input swing lies within the Vpp(AC) specification. Violation of Vcmr or Vpp impacts tPLH/PHL and tskD.
(3) Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew,
input pulse width, output duty cycle and maximum frequency specifications.
(4) Output pulse skew tskO is the absolute difference of the propagation delay times:| tPLH - tPHL |.
May-2011
MS1301-E-00
-6-
AK8180B
Figure 1 CCLK AC Test Reference
Figure 2 Propagation Delay Test Reference
Figure 3 Output-to-Output Skew
Figure 4 Output Pulse Skew Test Reference
MS1301-E-00
May-2011
-7-
AK8180B
VDD
VDD/2
VDD=3.3V VDD=2.5V
GND
2.4V
0.55V
tP
1.8V
0.6V
T0
tF
DC = tP / T0 x 100%
tR
The time from the PLL controlled edge to the non
controlled edge, divided by the time between PLL
controlled edges, expressed as a percentage.
Figure 5 Output Duty Cycle
Figure 6 Output Translation Test Reference
VDD
CCLK
PCLK
VDD/2
GND
TN
VDD
CLK_STOPN
VDD/2
TJIT(CC) = | TN – TN+1 |
GND
tS
TN+1
The variation in cycle time of a signal between adjacent
cycles, over a random sample of adjacent cycle pairs.
tH
Figure 7 Setup and Hold Time Test Reference
Figure 8 Cycle-to-Cycle Jitter
May-2011
MS1301-E-00
-8-
AK8180B
Function Table
The following table shows the inputs/outputs clock state configured through the control pins.
Table 1: Control-Pin-Setting Function Table
Control Pin
Default
CLK_SEL
1
OE
1
CLK_STOP
1
0
CCLK0 input selected
Outputs disabled. (high impedance)
1
CCLK1 input selected
Outputs enabled
Outputs synchronously stopped in
Outputs active
logic low state.
Application example of CLK_STOP
MS1301-E-00
May-2011
-9-
AK8180B
Package Information
· Mechanical data :
32-lead LQFP
9.00±0.20
7.00
17
25
16
32
9
7.00
9.00±0.20
24
0.37±0.05
0.20
M
0゜~7゜
1.60MAX
0.80
8
1.35~1.45
1
0.60±0.10
0.10 S
May-2011
0.05~0.15
0.09~0.20
S
MS1301-E-00
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AK8180B
· Marking
a:
b:
c:
#1 Pin Index
Part number
Date code (7 digits)
24
17
25
16
AK8180B
b
XXXXXXX
a
c
32
9
1
8
(1) AKM is the brand name of AKM’s IC’s.
AKM and the logo -
- are the brand of AKM’s IC’s and identify that AKM
continues to offer the best choice for high performance mixed-signal solution under
this brand.
· RoHS Compliance
All integrated circuits form Asahi Kasei Microdevices Corporation (AKM)
assembled in “lead-free” packages* are fully compliant with RoHS.
(*) RoHS compliant products from AKM are identified with “Pb free” letter indication on
product label posted on the anti-shield bag and boxes.
MS1301-E-00
May-2011
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AK8180B
IMPORTANT NOTICE
 These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
 Descriptions of external circuits, application circuits, software and other related information contained in this
document are provided only to illustrate the operation and application examples of the semiconductor products. You
are fully responsible for the incorporation of these external circuits, application circuits, software and other related
information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third
parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent,
intellectual property, or other rights in the application or use of such information contained herein.
 Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
 AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it,
and which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety
or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or
perform may reasonably be expected to result in loss of life or in significant injury or damage to person or
property.
 It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places
the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer
or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all
claims arising from the use of said product in the absence of such notification.
May-2011
MS1301-E-00
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