ASM2I99446 July 2005 rev 0.4 2.5V and 3.3V LVCMOS Clock Distribution Buffer Features Configurable is specified for the extended temperature range of -40°C to 10 outputs LVCMOS clock 85°C. distribution buffer The ASM2I99446 is a full static fanout buffer design Compatible to single, dual and mixed 3.3V/2.5V supporting clock frequencies up to 250MHz. The signals Voltage supply are generated and retimed on-chip to ensure minimal skew Wide range output clock frequency up to 250MHz between the three output banks. Two independent Designed for mid-range to high-performance LVCMOS compatible clock inputs are available. This telecom, networking and computer applications feature supports redundant clock sources or the addition of Supports applications requiring clock redundancy a test clock into the system design. Each of the three Max. output skew of 200pS (150pS within one output banks can be individually supplied by 2.5V or 3.3V bank) supporting mixed voltage applications. The FSELx pins Selectable output configurations per output bank choose between division of the input reference frequency Tristatable outputs by one or two. The frequency divider can be set individually 32 lead LQFP & TQFP Packages Ambient operating temperature range of for each of the three output banks. The ASM2I99446 can - -40 to 85°C be reset and the outputs are disabled by deasserting the MR/OE pin (logic high state). Asserting MR/OE will enable the outputs. Functional Description All inputs accept LVCMOS signals while the outputs The ASM2I99446 is a 2.5V and 3.3V compatible 1:10 clock provide LVCMOS compatible levels with the capability to distribution buffer designed for low-voltage mid-range to drive terminated 50Ω transmission lines. Please consult the high-performance telecom, networking and computing ASM2I99456 specification for a 1:10 mixed voltage buffer applications. Both 3.3V, 2.5V and dual supply voltages are with LVPECL compatible inputs. For series terminated supported for mixed-voltage applications. The ASM2I99446 transmission lines, each of the ASM2I99446 outputs can offers 10 low-skew outputs and 2 selectable inputs for clock drive one or two traces giving the devices an effective redundancy. The outputs are configurable and support 1:1 fanout of 1:20. The device is packaged in a and 1:2 output to input frequency ratios. The ASM2I99446 32-lead LQFP and TQFP Packages. 7x7mm2 Alliance Semiconductor 2575, Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com Notice: The information in this document is subject to change without notice. ASM2I99446 July 2005 rev 0.4 Block Diagram VCC 25K 0 VCC 25K 1 CCLK0 CCLK1 CCLK_SEL CLK 0 CLK-2 1 25K QA0 QA1 QA2 QB0 0 QB1 1 QB2 QC0 FSELA 25K FSELB 0 QC1 1 QC2 QC3 25K FSELC 25K MR/OE 25K Pin Configuration VCCC VCCB QB2 GND QB1 VCCB QB0 GND 32 – LEAD PACKAGE PINOUT -- Top View 24 23 22 21 20 19 18 17 VCCA 25 16 QC3 QA2 26 15 GND GND 27 14 QC2 QA1 28 13 VCCC VCCA 29 12 QC1 QA0 30 11 GND GND 31 10 QC0 MR/OE 32 9 VCCC 1 2 3 4 5 6 7 8 CCLK_SEL VCC CCLK0 CCLK1 FSELA FSELB FSELC GND ASM2I99446 2.5V and 3.3V LVCMOS Clock Distribution Buffer Notice: The information in this document is subject to change without notice. 2 of 14 ASM2I99446 July 2005 rev 0.4 Table 1: Pin Configuration Pin Number 3,4 5,6,7 32 8,11,15,20,24,27,31 25,29 18,22 9,13,17 2 Pin I/O Type CCLK0, CCLK1 Input LVCMOS LVCMOS clock inputs FSELA, FSELB, FSELC Input LVCMOS Input LVCMOS - Supply Output bank divide select input Internal reset and output (high impedance) control Negative voltage supply (GND) - Supply Positive voltage supply for output banks MR/OE GND VCCA, VCCB, VCCC VCC Function - Supply 30,28, 26 QA0 - QA2 Output LVCMOS Bank A outputs Positive voltage supply for core (VCC) 23,21,19 QB0 - QB2 Output LVCMOS Bank B outputs 10,12,14,16 QC0 - QC3 Output LVCMOS Bank C outputs Note: VCCB is internally connected to VCC. Table 2: Supported Single and Dual Supply Configurations VCC1 VCCA2 VCCB3 VCCC4 GND 3.3V 3.3V 3.3V 3.3V 0V Mixed voltage supply 3.3V 3.3V or 2.5V 3.3V 3.3V or 2.5V 0V 2.5V 2.5V 2.5V 2.5V 2.5V 0V Supply voltage configuration 3.3V Note: 1 VCC is the positive power supply of the device core and input circuitry. VCC voltage defines the input threshold and levels 2 VCCA is the positive power supply of the bank A outputs. VCCA voltage defines bank A output levels 3 VCCB is the positive power supply of the bank B outputs. VCCB voltage defines bank B output levels. VCCB is internally connected to 4 VCCC is the positive power supply of the bank B outputs. VCCC voltage defines bank C output levels. VCC. Table 3: Function Table (Controls) Control Default 0 1 CCLK_SEL FSELA FSELB FSELC 0 0 0 0 CCLK0 fQA0:2 = fREF FQBO:2 = fREF FQCO:3 = fREF CCLK1 f QA0:2 = fREF ÷2 f QBO:2 = fREF ÷2 f QCO:3 = fREF ÷2 MR/OE 0 Outputs enabled Internal reset Outputs disabled (tristate) Table 4: Absolute Maximum Ratings1 Symbol Characteristics Min Max Unit VCC Supply Voltage -0.3 3.6 V VIN DC Input Voltage -0.3 VCC+0.3 V VOUT DC Output Voltage -0.3 VCC+0.3 V IIN DC Input Current ±20 mA IOUT DC Output Current ±50 mA TS Storage temperature 125 °C -65 Condition Note: 1 These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability. 2.5V and 3.3V LVCMOS Clock Distribution Buffer Notice: The information in this document is subject to change without notice. 3 of 14 ASM2I99446 July 2005 rev 0.4 Table 5: General Specifications Symbol Characteristics Min Typ Max VCC ÷2 Unit VTT Output Termination Voltage MM ESD Protection (Machine Model) 200 V HBM ESD Protection (Human Body Model) 2000 V LU Latch–Up Immunity 200 mA CPD Power Dissipation Capacitance 10 pF CIN Input Capacitance 4.0 pF Condition V Per output Table 6: DC CHARACTERISTICS (VCC = VCCA = VCCB = VCCC = 3.3V ±5%, TA = –40°C to +85°C) Symbol VIH VIL IIN Characteristics Input High Voltage Input Low Voltage Min 2.0 -0.3 Typ Input Current 1 Max VCC + 0.3 0.8 200 VOH Output High Voltage 2.4 VOL Output Low Voltage ZOUT ICCQ3 Output Impedance Maximum Quiescent Supply Current 0.55 0.30 14 - 17 2.0 Unit V V Condition LVCMOS LVCMOS µA VIN=GND or VIN=VCC V V V Ω mA IOH=-24 mA2 3 IOL= 24mA IOL= 12mA All VCC Pins Note: 1 Input pull-up / pull-down resistors influence input current. 2 The ASM2I99446 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated to a termination voltage of VTT. Alternatively, the device drives up to two 50Ω series terminated transmission lines. 3 ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open. 2.5V and 3.3V LVCMOS Clock Distribution Buffer Notice: The information in this document is subject to change without notice. transmission line 4 of 14 ASM2I99446 July 2005 rev 0.4 Table 7: AC CHARACTERISTICS (VCC = VCCA = VCCB = VCCC = 3.3V ±5%, TA = –40°C to +85°C)1 Symbol Characteristics Max Unit Condition 2502 2 250 125 MHz MHz MHz nS FSELx=0 FSELx=1 1.03 4.45 4.2 nS nS nS Output Disable Time 10 nS Output Enable Time Output-to-output Skew 10 nS 150 200 350 pS pS pS 2.25 200 53 55 nS pS % % DCREF = 50% DCREF = 25%-75% 1.0 nS 0.55 to 2.4V fref Input Frequency fMAX Maximum Output Frequency tP, REF Reference Input Pulse Width tr, tf tPLH tPHL tPLZ, HZ CCLK Input Rise/Fall Time tPZL, LZ tsk(O) tsk(PP) tSK(P) DCQ tr, tf Min ÷1 output ÷2 output CCLK0,1 to any Q CCLK0,1 to any Q Propagation delay Typ 0 0 0 1.4 2.2 2.2 Within one bank Any output Bank, Same output divider Any output, Any output divider Device-to-device Skew Output pulse skew4 ÷1 output Output Duty Cycle ÷2 output 47 45 Output Rise/Fall Time 0.1 2.8 2.8 50 50 0.8 to 2.0V Note: 1 AC characteristics apply for parallel output termination of 50Ω to VTT 2 The ASM2I99446 is functional up to an input and output clock frequency of 350MHz and is characterized up to 250MHz. 3 Violation of the 1.0nS maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width, output duty cycle and maximum frequency specifications. 4 Output pulse skew is the absolute difference of the propagation delay times | tpLH - tpHL |. Table 8: DC CHARACTERISTICS (VCC = VCCA = VCCB = VCCC = 2.5V ±5%, TA = –40°C to +85°C) Symbol Characteristics Min VIH VIL Input High Voltage Input Low Voltage 1.7 -0.3 VOH Output High Voltage 1.8 VOL Output Low Voltage ZOUT Output Impedance IIN ICCQ3 Input Current2 Maximum Quiescent Supply Current Typ Max Unit VCC + 0.3 0.7 V V LVCMOS LVCMOS V IOH=-15 mA V IOL= 15 mA 0.6 17 - 202 Condition 1 Ω ±200 2.0 µA mA VIN=GND or VIN=VCC All VCC Pins Note: 1 The ASM2I99446 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50Ω series terminated transmission lines per output. 2 Input pull-up / pull-down resistors influence input current. 3 ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open. 2.5V and 3.3V LVCMOS Clock Distribution Buffer Notice: The information in this document is subject to change without notice. 5 of 14 ASM2I99446 July 2005 rev 0.4 Table 9: AC CHARACTERISTICS (VCC = VCCA = VCCB = VCCC = 2.5V ±5%, TA = –40°C to +85°C)1,2 Symbol Characteristics fref Input Frequency fMAX Maximum Output Frequency Min Typ 0 0 0 ÷1 output ÷2 output Max Unit 2503 2 250 125 MHz MHz MHz FSELx=0 FSELx=1 tP, REF Reference Input Pulse Width tr, tf CCLK Input Rise/Fall Time tPLH tPHL Propagation delay tPLZ, HZ Output Disable Time 10 nS tPZL, LZ Output Enable Time Output-to-output Skew 10 nS tsk(PP) Within one bank Any output Bank, Same output divider Any output, Any output divider Device-to-device Skew 150 200 350 3.0 pS pS pS nS tSK(P) Output pulse skew5 200 pS DCQ Output Duty Cycle 55 % DCREF = 50% tr, tf Output Rise/Fall Time 1.0 nS 0.6 to 1.8V tsk(O) 1.4 Condition CCLK0,1 to any Q CCLK0,1 to any Q nS 2.6 2.6 ÷1 or ÷2 output 45 50 0.1 1.04 nS 5.6 5.5 nS nS 0.7 to 1.7V Note: 1 AC characteristics apply for parallel output termination of 50Ω to VTT. 2 AC specifications are design targets, final specification is pending device characterization. 3 The ASM2I99446 is functional up to an input and output clock frequency of 350MHz and is characterized up to 250MHz. 4 Violation of the 1.0nS maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width, output duty cycle and maximum frequency specifications. 5 Output pulse skew is the absolute difference of the propagation delay times: | tpLH - tpHL |. Table 10: AC CHARACTERISTICS (VCC = 3.3V + 5%, VCCA, VCCB, VCCC = 2.5V + 5% or 3.3V + 5%, TA = –40°C to +85°C)1,2 Symbol Characteristics Min Typ Max Unit 150 250 350 2.5 pS pS pS nS Condition Output-to-output Skew tsk(PP) Within one bank Any output Bank, Same output divider Any output, Any output divider Device-to-device Skew tPLH,HL Propagation delay tsk(O) CCLK0,1 to any Q See 3.3V table 3 tSK(P) Output pulse skew DCQ Output Duty Cycle ÷1 or ÷2 output 45 50 250 pS 55 % DCREF = 50% Note: 1 AC characteristics apply for parallel output termination of 50Ω to VTT. 2 For all other AC specifications, refer to 2.5V or 3.3V tables according to the supply voltage of the output bank. 3 Output pulse skew is the absolute difference of the propagation delay times: | tpLH - tpHL |. 2.5V and 3.3V LVCMOS Clock Distribution Buffer Notice: The information in this document is subject to change without notice. 6 of 14 ASM2I99446 July 2005 rev 0.4 APPLICATIONS INFORMATION impedance mismatch seen looking into the driver. The parallel combination of the 36Ω series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: Driving Transmission Lines The ASM2I99446 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20Ω the drivers can drive either parallel or series terminated transmission lines. In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50Ω resistance to VCC÷2. ASM2I99446 OUTPUT BUFFER IN 14Ω RS = 36Ω || 36Ω R0 = 14Ω VL = 3.0 ( 25 ÷ (18+14+25)) = 1.31V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.5V. It will then increment towards the quiescent 3.0V in steps separated by one round trip delay (in this case 4.0nS). 3.0 2.5 OutA tD = 3.8956 2.0 In 1.5 1.0 OUTA 0 2 ASM2I99446 OUTPUT BUFFER IN Z0=50Ω RS=36Ω RS=36Ω 4 6 8 10 12 14 TIME (nS) OUTB0 14Ω OutB tD = 3.9386 0.5 Z0=50Ω RS=36Ω Z0 = 50Ω || 50Ω VOLTAGE (V) This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the ASM2I99446 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 3. “Single versus Dual Transmission Lines” illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme the fanout of the ASM2I99446 clock driver is effectively doubled due to its capability to drive multiple lines. VL = VS ( Z0 ÷ (RS+R0 +Z0)) Z0=15Ω OUTB1 Figure 3. Single versus Dual Transmission Lines The waveform plots in Figure 4. “Single versus Dual Line Termination Waveforms” show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the ASM2I99446 output buffer is more than sufficient to drive 50Ω transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43pS exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the ASM2I99446. The output waveform in Figure 4 “Single versus Dual Line Termination Waveforms” shows a step in the waveform. This step is caused by the Figure 4. Single versus Dual Waveforms Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 5. “Optimized Dual Line Termination” should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. ASM2I99446 OUTPUT BUFFER IN RS=22Ω 14Ω RS=22Ω Z0=50Ω Z0=50Ω 14Ω + 22Ω║22Ω = 50Ω║50Ω 25Ω = 25Ω Figure 5. Optimized Dual Line Termination 2.5V and 3.3V LVCMOS Clock Distribution Buffer Notice: The information in this document is subject to change without notice. 7 of 14 ASM2I99446 July 2005 rev 0.4 ASM2I99446 Z0=50Ω Pulse Generator Z=50Ω Z0=50Ω RT=50Ω RT=50Ω VTT Figure 6. CCLK0, 1 ASM2I99446 AC test reference for VCC = 3.3V and VCC = 2.5V VCC CCLK VCC ÷2 GND VCC = 3.3V VCC = 2.5V 2.4 1.8V 0.55 0.6V VCC QX t(LH) tR tF VCC ÷2 Figure 7. Output Transition Time Test Reference GND t(HL) Figure 8. Propagation Delay (tPD) Test Reference VCC VCC CCLK VCC ÷2 GND VCC ÷2 GND VCC VOH VCC ÷2 tSK(LH) tSK(HL) QX VCC ÷2 t(LH) GND t(HL) GND tSK(P) │tPLH- tPHL │ The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device Figure 10. Propagation Delay (tSK(P)) Test Reference Figure 9. Output–to–Output Skew tSK(LH,HL) VCC VCC ÷2 GND TJIT(CC) = |TN -TN + 1| TN tP TN + 1 The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs T0 DC (tP ÷T0 Χ 100%) Figure 12. Cycle–to–Cycle Jitter The time from the PLL controlled edge to the non-controlled edge, divided by the time between PLL controlled edges, expressed as a percentage. Figure 11. Output Duty Cycle (DC) Reference 2.5V and 3.3V LVCMOS Clock Distribution Buffer Notice: The information in this document is subject to change without notice. 8 of 14 ASM2I99446 July 2005 rev 0.4 Power Consumption of the ASM2I99446 and Thermal Management The ASM2I99446 AC specification is guaranteed for the entire operating frequency range up to 250MHz. The ASM2I99446 power consumption and the associated long-term reliability may decrease the maximum frequency limit, depending on operating conditions such as clock frequency, supply voltage, output loading, ambient temperature, vertical convection and thermal conductivity of package and board. This section describes the impact of these parameters on the junction temperature and gives a guideline to estimate the ASM2I99446 die junction temperature and the associated device reliability. Table 11. Die junction temperature and MTBF Junction temperature (°C) MTBF (Years) 100 20.4 110 9.1 120 4.2 130 2.0 Increased power consumption will increase the die junction temperature and impact the device reliability (MTBF). According to the system-defined tolerable MTBF, the die junction temperature of the ASM2I99446 needs to be controlled and the thermal impedance of the board/package should be optimized. The power dissipated in the ASM2I99446 is represented in equation 1. Where ICCQ is the static current consumption of the ASM2I99446, CPD is the power dissipation capacitance per output, (Μ)ΣCL represents the external capacitive output load, N is the number of active outputs (N is always 12 in case of the ASM2I99446). The ASM2I99446 supports driving transmission lines to maintain high signal integrity and tight timing parameters. Any transmission line will hide the lumped capacitive load at the end of the board trace, therefore, ΣCL is zero for controlled transmission line systems and can be eliminated from equation 1. Using parallel termination output termination results in equation 2 for power dissipation. In equation 2, P stands for the number of outputs with a parallel or thevenin termination, VOL, IOL, VOH and IOH are a function of the output termination technique and DCQ is the clock signal duty cycle. If transmission lines are used ΣCL is zero in equation 2 and can be eliminated. In general, the use of controlled transmission line techniques eliminates the impact of the lumped capacitive loads at the end lines and greatly reduces the power dissipation of the device. Equation 3 describes the die junction temperature TJ as a function of the power consumption. Where Rthja is the thermal impedance of the package (junction to ambient) and TA is the ambient temperature. According to Table 11, the junction temperature can be used to estimate the long-term device reliability. Further, combining equation 1 and equation 2 results in a maximum operating frequency for the ASM2I99446 in a series terminated transmission line system, equation 4. 2.5V and 3.3V LVCMOS Clock Distribution Buffer Notice: The information in this document is subject to change without notice. 9 of 14 ASM2I99446 July 2005 rev 0.4 TJ,MAX should be selected according to the MTBF system requirements and Table 11. Rthja can be derived from Table 12. The Rthja represent data based on 1S2P boards, using 2S2P boards will result in a lower thermal impedance than indicated below. Table 12. Thermal package impedance of the 32LQFP Convection, LFPM Still air 100 lfpm 200 lfpm 300 lfpm 400 lfpm 500 lfpm Rthja (1P2S board), °C/W 86 76 71 68 66 60 Rthja (2P2S board), °C/W 61 56 54 53 52 49 If the calculated maximum frequency is below 350 MHz, it becomes the upper clock speed limit for the given application conditions. The following eight derating charts describe the safe frequency operation range for the ASM2I99446. The charts were calculated for a maximum tolerable die junction temperature of 110°C (120°C), corresponding to an estimated MTBF of 9.1 years (4 years), a supply voltage of 3.3V and series terminated transmission line or capacitive loading. Depending on a given set of these operating conditions and the available device convection a decision on the maximum operating frequency can be made. 2.5V and 3.3V LVCMOS Clock Distribution Buffer 14 Notice: The information in this document is subject to change without notice. 10 of ASM2I99446 July 2005 rev 0.4 Package Information 32-lead TQFP Package SECTION A-A Dimensions Symbol Inches Min Max Millimeters Min Max A …. 0.0472 … 1.2 A1 0.0020 0.0059 0.05 0.15 A2 0.0374 0.0413 0.95 1.05 D 0.3465 0.3622 8.8 9.2 D1 0.2717 0.2795 6.9 7.1 E 0.3465 0.3622 8.8 9.2 E1 0.2717 0.2795 6.9 7.1 L 0.0177 0.0295 0.45 0.75 L1 0.03937 REF 1.00 REF T 0.0035 0.0079 0.09 0.2 T1 0.0038 0.0062 0.097 0.157 b 0.0118 0.0177 0.30 0.45 b1 0.0118 0.0157 0.30 0.40 R0 0.0031 0.0079 0.08 0.2 a 0° 7° 0° 7° e 0.031 BASE 0.8 BASE 2.5V and 3.3V LVCMOS Clock Distribution Buffer 14 Notice: The information in this document is subject to change without notice. 11 of ASM2I99446 July 2005 rev 0.4 32-lead LQFP Package SECTION A-A Dimensions Symbol Inches Min Max Millimeters Min Max A …. 0.0630 … 1.6 A1 0.0020 0.0059 0.05 0.15 A2 0.0531 0.0571 1.35 1.45 D 0.3465 0.3622 8.8 9.2 D1 0.2717 0.2795 6.9 7.1 E 0.3465 0.3622 8.8 9.2 E1 0.2717 0.2795 6.9 7.1 L 0.0177 0.0295 0.45 0.75 L1 0.03937 REF 1.00 REF T 0.0035 0.0079 0.09 0.2 T1 0.0038 0.0062 0.097 0.157 b 0.0118 0.0177 0.30 0.45 b1 0.0118 0.0157 0.30 0.40 R0 0.0031 0.0079 0.08 0.20 e a 0.031 BASE 0° 7° 0.8 BASE 0° 7° 2.5V and 3.3V LVCMOS Clock Distribution Buffer 14 Notice: The information in this document is subject to change without notice. 12 of ASM2I99446 July 2005 rev 0.4 Ordering Information Part Number Marking Package Type Operating Range ASM2I99446-32-LT ASM2I99446L 32-pin LQFP, Tray Industrial ASM2I99446-32-LR ASM2I99446L 32-pin LQFP,Tape and Reel Industrial ASM2I99446G-32-LT ASM2I99446GL 32-pin LQFP, Tray, Green Industrial ASM2I99446G-32-LR ASM2I99446GL 32-pin LQFP, Tape and Reel, Green Industrial ASM2I99446-32-ET ASM2I99446E 32-pin TQFP, Tray Industrial ASM2I99446-32-ER ASM2I99446E 32-pin TQFP,Tape and Reel Industrial ASM2I99446G-32-ET ASM2I99446GE 32-pin TQFP, Tray, Green Industrial ASM2I99446G-32-ER ASM2I99446GE 32-pin TQFP,Tape and Reel, Green Industrial Device Ordering Information A S M 2 I 9 9 4 4 6 G - 3 2 - L R R = Tape & reel, T = Tube or Tray O = SOT S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70 DEVICE PIN COUNT F = LEAD FREE AND RoHS COMPLIANT PART G = GREEN PACKAGE PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved ALLIANCE SEMICONDUCTOR MIXED SIGNAL PRODUCT Licensed under US patent #5,488,627, #6,646,463 and #5,631,920. 2.5V and 3.3V LVCMOS Clock Distribution Buffer 14 Notice: The information in this document is subject to change without notice. 13 of ASM2I99446 July 2005 rev 0.4 Alliance Semiconductor Corporation 2575, Augustine Drive, Santa Clara, CA 95054 Tel# 408-855-4900 Fax: 408-855-4999 www.alsc.com Copyright © Alliance Semiconductor All Rights Reserved Part Number: ASM2I99446 Document Version: 0.4 Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to Alliance Semiconductor, dated 11-11-2003 © Copyright 2003 Alliance Semiconductor Corporation. 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Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. 2.5V and 3.3V LVCMOS Clock Distribution Buffer 14 Notice: The information in this document is subject to change without notice. 14 of