MOTOROLA MPC9443

MOTOROLA
Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA
2.5V and 3.3V LVCMOS Clock
Order Number: MPC9443/D
Rev 2, 05/2002
MPC9443
Freescale Semiconductor, Inc...
Fanout Buffer
The MPC9443 is a 2.5V and 3.3V compatible 1:16 clock distribution
buffer designed for low-voltage high-performance telecom, networking
and computing applications. The device supports 3.3V, 2.5V and dual
supply voltage (mixed-voltage) applications. The MPC9443 offers 16
low-skew outputs which are divided into 4 individually configurable banks.
Each output bank can be individually supplied by 2.5V or 3.3V,
individually set to run at 1X or 1/2X of the input clock frequency or be
disabled (logic low output state). Two selectable LVPECL compatible
inputs support differential clock distribution systems. In addition, one
selectable LVCMOS input is provided for LVCMOS clock distribution
systems. The MPC9443 is specified for the extended temperature range
of –40 to +85°C.
Features
• Configurable 16 outputs LVCMOS clock distribution buffer
• Compatible to single, dual and mixed 3.3V/2.5V voltage supply
• Output clock frequency up to 350 MHz
• Designed for high-performance telecom, networking and computer
applications
• Supports applications requiring clock redundancy
•
•
•
•
•
•
LOW VOLTAGE SUPPLY 2.5V
AND 3.3V LVCMOS CLOCK
FANOUT BUFFER
FA SUFFIX
48–LEAD LQFP PACKAGE
CASE 932–03
Max. output skew of 250 ps (125 ps within one bank)
Selectable output configurations per output bank
Individually per-bank high–impedance tristate
Output disable (stop in logic low state) control
48 ld LQFP package
Ambient operating temperature range of –40 to 85°C
Functional Description
The MPC9443 is a full static design supporting clock frequencies up to 350 MHz. The signals are generated and retimed
on-chip to ensure minimal skew between the four output banks.
Two independent LVPECL compatible clock inputs are available. This feature supports redundant differential clock sources. In
addition, the MPC9443 supports single-ended LVCMOS clock distribution systems. Each of the four output banks can be
individually supplied by 2.5V or 3.3V, supporting mixed voltage applications. The FSELx pins choose between division of the
input reference frequency by one or two. The frequency divider can be set individually for each output bank. The MPC9443 output
banks are in high–impedance state by deasserting the OEN pins. Asserting OEN will the enable output banks. Please see the
Output High–Impedance Control table on page 4 for details. The outputs can be synchronously stopped (logic low state). The
outputs provide LVCMOS compatible levels with the capability to drive terminated 50 Ω transmission lines. For series terminated
transmission lines, each of the MPC9443 outputs can drive one or two traces giving the devices an effective fanout of 1:32 at VCC
= 3.3V. The device is packaged in a 7x7 mm2 48-lead LQFP package.
 Motorola, Inc. 2002
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MPC9443
PCLK0
PCLK0
PCLK1
PCLK1
CCLK
PCLK_SEL
CCLK_SEL
(pulldown)
Bank A
0
(pullup)
(pulldown)
0
CLK
0
1
CLK ÷ 2
1
QA0
1
QA1
(pullup)
QA2
(pulldown)
QA3
QA4
(pulldown)
Bank B
(pulldown)
QB0
0
QB1
1
QB2
Freescale Semiconductor, Inc...
FSELA
(pulldown)
FSELB
(pulldown)
FSELC
(pulldown)
FSELD
(pulldown)
Bank C
QC0
0
QC1
1
QC2
QD0
Bank D
QD1
0
QD2
CLK_STOP
OE0
OE1
1
(pulldown)
QD3
QD4
(pulldown)
5
(pulldown)
GND
GND
QC2
QC1
QC0
VCCC
VCC
VCCB
QB2
QB1
QB0
GND
Figure 1. MPC9443 Logic Diagram
VCCA
37
36 35 34 33 32 31 30 29 28 27 26 25
24
QA4
38
23
QD0
QA3
39
22
QD1
VCCD
40
21
QD2
41
20
GND
QA1
42
19
QD3
QA0
43
18
QD4
VCCA
44
17
VCCD
FSELA
45
16
CLK_STOP
FSELB
46
15
OE0
FSELC
47
14
GND
48
13
10 11 12
OE1
GND
3
4
5
6
7
8
9
FSELD
CCLK
CCLK_SEL
GND
PCLK0
PCLK0
VCC
PCLK_SEL
PCLK1
2
PCLK1
1
VCC
MPC9443
GND
QA2
GND
Figure 2. 48–Lead Package Pinout (Top View)
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TIMING SOLUTIONS
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MPC9443
Table 1: Pin Configuration
Freescale Semiconductor, Inc...
Pin
I/O
Type
Function
CCLK
Input
LVCMOS
LVCMOS clock inputs
PCLK0, PCLK0
Input
LVCMOS
LVPECL differential clock input
PCLK1, PCLK1
Input
LVCMOS
LVPECL differential clock input
FSELA, FSELB, FSELC, FSELD
CCLK_SEL
Input
LVCMOS
Output bank divide select input
Input
LVCMOS
LVCMOS/LVPECL clock input select
PCLK_SEL
Input
LVCMOS
PCLK0/PCLK1 clock input select
OE0, OE1
Input
LVCMOS
Output tristate control
CLK_STOP
Input
LVCMOS
Synchronous output enable/disable (clock stop) control
GND
Supply
Negative voltage supply
VCCA, VCCB, VCCC, VCCD
VCC
Supply
Positive voltage supply output bank (VCC)
Supply
Positive voltage supply core (VCC)
QA0 to QA4
Output
LVCMOS
Bank A outputs
QB0 to QB2
Output
LVCMOS
Bank B outputs
QC0 to QC2
Output
LVCMOS
Bank C outputs
QD0 to QD4
Output
LVCMOS
Bank D outputs
Table 2: Supported Single and Dual Supply Configurations
VCCa
Supply voltage
configuration
a.
b.
c.
d.
e.
VCCAb
VCCBc
VCCCd
VCCDe
GND
3.3V supply
3.3V
3.3V
3.3V
3.3V
3.3V
0V
Mixed mode supply
3.3V
3.3V or 2.5V
3.3V or 2.5V
3.3V or 2.5V
3.3V or 2.5V
0V
2.5V supply
2.5V
2.5V
2.5V
2.5V
2.5V
0V
VCC is the positive power supply of the device core and input circuitry. VCC voltage defines the input threshold and levels
VCCA is the positive power supply of the bank A outputs. VCCA voltage defines bank A output levels
VCCB is the positive power supply of the bank B outputs. VCCB voltage defines bank B output levels
VCCC is the positive power supply of the bank C outputs. VCCC voltage defines bank C output levels
VCCD is the positive power supply of the bank D outputs. VCCD voltage defines bank D output levels
Table 3: Function Table (Controls)
Control
Default
0
CCLK_SEL
0
PCLK or PCLK1 active (LVPECL clock mode)
CCLK active (LVCMOS clock mode)
PCLK_SEL
0
PCLK0 active, PCLK1 inactive
PCLK1 active, PCLK0 inactive
FSELA
FSELB
0
fQA0:4 = fREF
fQB0:2 = fREF
fQA0:4 = fREF ÷ 2
fQB0:2 = fREF ÷ 2
FSELC
FSELD
0
0
fQC0:2 = fREF
fQD0:4 = fREF
fQC0:2 = fREF ÷ 2
fQD0:4 = fREF ÷ 2
CLK_STOP
0
Normal operation
Outputs are synchronously disabled (stopped) in logic
low state
OE0, OE1
00
TIMING SOLUTIONS
0
1
Asynchronous output enable control. See Table 4. OEN
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MPC9443
Table 4: Output High–Impedance Control (OEN)a
OE0
a.
OE1
QA0 to QA4
QC0 to QC2
QB0 to QB2
Total number of
enabled outputs
QD0 to QD4
0
0
Enabled
Enabled
Enabled
Enabled
16
0
1
Enabled
Disabled (tristate)
Disabled (tristate)
Enabled
10
1
0
Enabled
Enabled
Disabled (tristate)
Disabled (tristate)
8
1
1
Disabled (tristate)
Disabled (tristate)
Disabled (tristate)
Disabled (tristate)
0
OEN will tristate (high impedance) output banks independent on the logic state of the output and the status of CLK_STOP.
Table 5: Absolute Maximum Ratingsa
Freescale Semiconductor, Inc...
Symbol
Characteristics
Min
Max
Unit
VCC
Supply Voltage
-0.3
3.6
V
VIN
DC Input Voltage
-0.3
VCC+0.3
V
DC Output Voltage
-0.3
VCC+0.3
V
±20
mA
±50
mA
125
°C
VOUT
IIN
DC Input Current
IOUT
DC Output Current
TS
Storage temperature
-65
Condition
a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions
or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not
implied.
Table 6: General Specifications
Symbol
Characteristics
Min
Typ
VCC ÷ 2
Max
Unit
VTT
MM
Output termination voltage
ESD protection (Machine model)
200
V
HBM
ESD protection (Human body model)
2000
V
Latch-up immunity
200
LU
V
mA
CPD
Power dissipation capacitance
10
pF
CIN
Input capacitance
4.0
pF
MOTOROLA
Condition
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Per output
TIMING SOLUTIONS
Freescale Semiconductor, Inc.
MPC9443
± 5%, TA = –40 to +85°C)
Table 7: DC Characteristics (VCC = VCCA = VCCB = VCCC = VCCD = 3.3V
Symbol
VIH
VIL
VPP
VCMRa
IIN
VOH
VOL
ZOUT
ICCQd
Freescale Semiconductor, Inc...
a.
b.
c.
d.
Characteristics
Min
Input High Voltage
2.0
Input Low Voltage
-0.3
Peak-to-peak Input Voltage
PCLK0, 1
250
Common Mode Range
Input Currentb
PCLK0, 1
1.1
Output High Voltage
Typ
LVCMOS
V
LVCMOS
mV
LVPECL
V
LVPECL
µA
VIN=GND or VIN=VCC
IOH=-24 mAc
IOL= 24mAc
IOL= 12mA
2.4
V
0.55
0.30
Output Impedance
V
V
W
19
Condition
Maximum Quiescent Supply Current
2.0
mA
All VCC Pins
VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range
and the input swing lies within the VPP (DC) specification.
Input pull-up / pull-down resistors influence input current.
The MPC9443 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated
transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50Ω series terminated transmission lines (for
VCC=3.3V) or one 50Ω series terminated transmission line (for VCC=2.5V).
ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open.
fref
fMAX
Characteristics
Min
Input Frequency
Maximum Output Frequency
± 5%, TA = –40 to +85°C)a
Typ
Max
Unit
Condition
0
350
MHz
÷1 output
÷2 output
0
0
350
175
MHz
MHz
FSELx=0
FSELx=1
VPP
VCMRb
tP, REF
Peak-to-peak Input Voltage
PCLK0,1
500
1000
mV
LVPECL
Common Mode Range
PCLK0,1
1.3
VCC-0.8
V
LVPECL
tr, tf
tPLH
tPHL
tPLH
tPHL
CCLK Input Rise/Fall Time
tPLZ, HZ
tPZL, LZ
tS, tH
tsk(LH, HL)
tsk(PP)
tSK(P)
DCQ
d.
e.
f.
g.
V
Output Low Voltage
Symbol
c.
Unit
VCC-0.6
200
Table 8: AC Characteristics (VCC = VCCA = VCCB = VCCC = VCCD = 3.3V
a.
b.
Max
VCC + 0.3
0.8
Reference Input Pulse Width
Propagation Delay
1.4
PCLK0,1 to any Q
PCLK0,1 to any Q
CCLK to any Q
CCLK to any Q
ns
2.5
2.4
2.1
1.9
Output Disable Time
Output Enable Time
Setup, hold time (reference clock to CLK_STOP)
ns
5.0
5.2
4.2
4.6
ns
ns
ns
ns
10
ns
10
ns
500
45
45
0.8 to 2.0V
ps
Output-to-output Skewd
Within one bank
Any output, same output divider
Any output, any output divider
Device-to-device Skew (LH)e
Using PCLK0,1
Using CCLK
Device-to-device Skew (LH, HL)f Using PCLK0,1
Using CCLK
Output pulse skewg
Using PCLK0,1
Using CCLK
Output Duty Cycle fQ<140 MHz and using CCLK
fQ<250 MHz and using PCLK0,1
Output Rise/Fall Time
1.0c
50
50
125
225
250
2.5
2.1
2.8
2.7
ps
ps
ps
300
400
ps
ps
55
55
%
%
ns
ns
ns
ns
DCREF = 50%
tr, tf
0.1
1.0
ns
0.55 to 2.4V
AC characteristics apply for parallel output termination of 50Ω to VTT.
VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range
and the input swing lies within the VPP (AC) specification.
Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input
pulse width, output duty cycle and maximum frequency specifications.
tsk(LH, HL) includes both device skew referenced to the rising output edge and device skew referenced to the falling output edge.
Device-to-device skew referenced to the rising output edge.
Device-to-device skew referenced to the rising output edge or referenced to the falling output edge.
Output pulse skew is the absolute difference of the propagation delay times: | tpLH - tpHL |.
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Freescale Semiconductor, Inc.
MPC9443
± 5%, TA = –40 to +85°C)
Table 9: DC Characteristics (VCC = VCCA = VCCB = VCCC = VCCD = 2.5V
Symbol
VIH
VIL
VPP
VCMRa
IIN
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VOH
VOL
Characteristics
Min
Input High Voltage
1.7
Input Low Voltage
-0.3
Peak-to-peak Input Voltage
PCLK0,1
250
Common Mode Range
Input Currentb
PCLK0,1
1.1
Output High Voltage
Typ
Max
Unit
VCC + 0.3
0.7
V
LVCMOS
V
LVCMOS
mV
LVPECL
V
LVPECL
µA
VIN=GND or VIN=VCC
IOH= -15 mAc
IOL= 15 mAc
VCC-0.7
200
1.8
V
Output Low Voltage
0.6
V
W
Condition
ZOUT
Output Impedance
22
ICCQd
Maximum Quiescent Supply Current
2.0
mA
All VCC Pins
a.
VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range
and the input swing lies within the VPP (DC) specification.
b. Input pull-up / pull-down resistors influence input current.
c. The MPC9443 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated
transmission line to a termination voltage of VTT. Alternatively, the device drives one 50Ω series terminated transmission lines at
VCC=2.5V.
d. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open.
Table 10: AC Characteristics (VCC = VCCA = VCCB = VCCC = VCCD = 2.5
Symbol
fref
fMAX
Unit
Condition
350
MHz
0
0
350
175
MHz
MHz
FSELx=0
FSELx=1
VPP
VCMRb
tP, REF
Peak-to-peak input voltage
PCLK0,1
500
1000
mV
LVPECL
Common Mode Range
PCLK0,1
1.1
VCC-0.7
V
LVPECL
tr, tf
tPLH
tPHL
tPLH
tPHL
CCLK Input Rise/Fall Time
tsk(PP)
tSK(p)
DCQ
d.
e.
f.
g.
Max
0
tsk(LH, HL)
Input Frequency
Typ
÷1 output
÷2 output
tS, tH
c.
Min
Maximum Output Frequency
tPLZ, HZ
tPZL, LZ
a.
b.
Characteristics
± 5%, TA = –40 to +85°C)a
Reference Input Pulse Width
Propagation delay
1.4
PCLK0,1 to any Q
PCLK0,1 to any Q
CCLK to any Q
CCLK to any Q
ns
2.8
2.7
2.2
2.1
Output Disable Time
Output Enable Time
Setup, hold time (reference clock to CLK_STOP)
Output-to-output Skewd
Within one bank
Any output, same output divider
Any output, any output divider
Device-to-device Skew (LH)e
Using PCLK0,1
Using CCLK
Device-to-device Skew (LH, HL)f Using PCLK0,1
Using CCLK
g
Output pulse skew
Using PCLK0,1
Using CCLK
500
Output Duty Cycle fQ<140 MHz and using CCLK
fQ<250 MHz and using PCLK0,1
Output Rise/Fall Time
45
45
1.0c
ns
6.0
6.2
5.3
5.5
ns
ns
ns
ns
10
ns
10
ns
0.8 to 2.0V
ps
50
50
125
225
250
3.2
3.1
3.5
3.4
ps
ps
ps
300
400
ps
ps
55
55
%
%
ns
ns
ns
ns
DCREF = 50%
tr, tf
0.1
1.0
ns
0.6 to 1.8V
AC characteristics apply for parallel output termination of 50Ω to VTT.
VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range
and the input swing lies within the VPP (AC) specification.
Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input
pulse width, output duty cycle and maximum frequency specifications.
tsk(LH, HL) includes both device skew referenced to the rising output edge and device skew referenced to the falling output edge.
Device-to-device skew referenced to the rising output edge.
Device-to-device skew referenced to the rising output edge or referenced to the falling output edge.
Output pulse skew is the absolute difference of the propagation delay times: | tpLH - tpHL |.
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Table 11: DC Characteristics
(VCC = 3.3V ± 5%, any VCCA,B,C,D = 2.5V
Symbol
VIH
VIL
IIN
VOH
VOL
Freescale Semiconductor, Inc...
VPP
VCMRc
ZOUT
± 5% or 3.3V ± 5% (mixed), TA = –40 to +85°C)
Characteristics
Min
Input high voltage
2.0
Input low voltage
Input currenta
-0.3
Output High Voltage
2.5V output
3.3V output
Output Low Voltage
2.5V output
3.3V output
Max
Unit
VCC + 0.3
0.8
V
LVCMOS
V
LVCMOS
200
µA
1.7
2.0
V
0.6
0.55
Peak-to-peak input voltage
PCLK0,1
250
Common Mode Range
PCLK0,1
1.1
Output impedance
Typ
VCC-0.6
2.5V output
3.3V output
22
19
V
Condition
IOH= -15 mAb
IOH= -24 mAb
IOL= 15 mAb
IOL= 24 mAb
mV
LVPECL
V
LVPECL
W
W
CPD
Power Dissipation Capacitance
10
pF
Per Output
ICCQd
Maximum Quiescent Supply Current
2.0
mA
All VCC Pins
a. Input pull-up / pull-down resistors influence input current.
b. The MPC9443 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated
transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50Ω series terminated transmission lines
(for VCC=3.3V) or one 50Ω series terminated transmission line (for VCC=2.5V).
c.
VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range
and the input swing lies within the VPP (DC) specification.
d. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open.
Table 12: AC Characteristics
(VCC = 3.3V ± 5%, any VCCA,B,C,D = 2.5V
Symbol
tsk(LH, HL)
tsk(PP)
tPLH, HL
tSK(P)
c.
d.
Characteristics
Output-to-output SkewcAny output, same output divider
Any output, any output divider
Min
Typ
Device-to-device Skew
See 3.3V AC table
Propogation Delay
See 3.3V AC table
Output pulse skewd
Using PCLK0,1
Using CCLK
Max
Unit
275
350
ps
ps
400
500
ps
ps
Condition
DCREF = 50%
45
50
fQ<140 MHz and using CCLK
55
%
45
50
fQ<250 MHz and using PCLK0,1
55
%
AC characteristics apply for parallel output termination of 50Ω to VTT.
This table only specifies AC parameter im mixed voltage supply conditions that vary from the corresponding AC tables. All other
parameters, see the 3.3V (for 3.3V outputs) or 2.5V AC table (for 2.5V outputs).
tsk(LH, HL) includes both device skew referenced to the rising output edge and device skew referenced to the falling output edge.
Output pulse skew is the absolute difference of the propagation delay times: | tpLH - tpHL |.
DCQ
a.
b.
± 5% or 3.3V ± 5% (mixed), TA = –40 to +85°C)a b
Output Duty Cycle
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MPC9443
APPLICATIONS INFORMATION
The MPC9443 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 20Ω the
drivers can drive either parallel or series terminated
transmission lines at VCC = 3.3V. For more information on
transmission lines the reader is referred to application note
AN1091. In most high performance clock networks
point-to-point distribution of signals is the method of choice.
In a point-to-point scheme either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50Ω resistance to VCC÷2.
This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each
output of the MPC9443 clock driver. For the series terminated
case however there is no DC current draw, thus the outputs
can drive multiple series terminated lines. Figure 3. “Single
versus Dual Transmission Lines” illustrates an output driving
a single series terminated line versus two series terminated
lines in parallel. When taken to its extreme the fanout of the
MPC9443 clock driver is effectively doubled due to its
capability to drive multiple lines (at VCC = 3.3V).
MPC9443
OUTPUT
BUFFER
IN
19Ω
MPC9443
OUTPUT
BUFFER
IN
= VS ( Z0 ÷ (RS+R0 +Z0))
= 50Ω || 50Ω
= 31Ω || 31Ω
= 19Ω
= 3.0 ( 25 ÷ (15.5+19+25)
= 1.26V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.52V. It will then increment
towards the quiescent 3.0V in steps separated by one round
trip delay (in this case 4.0ns).
VL
Z0
RS
R0
VL
3.0
2.5
OutA
tD = 3.8956
OutB
tD = 3.9386
2.0
In
1.5
1.0
0.5
RS = 31Ω
ZO = 50Ω
0
OutA
2
4
6
8
TIME (nS)
10
12
14
Figure 4. Single versus Dual Waveforms
RS = 31Ω
ZO = 50Ω
OutB0
19Ω
RS = 31Ω
ZO = 50Ω
OutB1
Figure 3. Single versus Dual Transmission Lines
The waveform plots in Figure 4. “Single versus Dual Line
Termination Waveforms” show the simulation results of an
output driving a single line versus two lines. In both cases the
drive capability of the MPC9443 output buffer is more than
sufficient to drive 50Ω transmission lines on the incident
edge. Note from the delay measurements in the simulations a
delta of only 43ps exists between the two differently loaded
outputs. This suggests that the dual line driving need not be
used exclusively to maintain the tight output-to-output skew
of the MPC9443. The output waveform in Figure 4. “Single
versus Dual Line Termination Waveforms” shows a step in
the waveform, this step is caused by the impedance
mismatch seen looking into the driver. The parallel
combination of the 31Ω series resistor plus the output
MOTOROLA
impedance does not match the parallel combination of the
line impedances. The voltage wave launched down the two
lines will equal:
VOLTAGE (V)
Freescale Semiconductor, Inc...
Driving Transmission Lines
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines the
situation in Figure 5. “Optimized Dual Line Termination”
should be used. In this case the series terminating resistors
are reduced such that when the parallel combination is added
to the output buffer impedance the line impedance is perfectly
matched.
MPC9443
OUTPUT
BUFFER
RS = 12Ω
ZO = 50Ω
RS = 12Ω
ZO = 50Ω
19Ω
19Ω + 12Ω k 12Ω = 50Ω k 50Ω
25Ω = 25Ω
Figure 5. Optimized Dual Line Termination
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TIMING SOLUTIONS
Freescale Semiconductor, Inc.
MPC9443
In equation 2, P stands for the number of outputs with a
parallel or thevenin termination, VOL, IOL, VOH and IOH are a
function of the output termination technique and DCQ is the
clock signal duty cyle. If transmission lines are used ΣCL is
zero in equation 2 and can be eliminated. In general, the use
of controlled transmission line techniques eliminates the
impact of the lumped capacitive loads at the end lines and
greatly reduces the power dissipation of the device. Equation
3 describes the die junction temperature TJ as a function of
the power consumption.
Freescale Semiconductor, Inc...
Power Consumption of the MPC9443 and Thermal
Management
The MPC9443 AC specification is guaranteed for the
entire operating frequency range up to 350 MHz. The
MPC9443 power consumption and the associated long-term
reliability may decrease the maximum frequency limit,
depending on operating conditions such as clock frequency,
supply voltage, output loading, ambient temperture, vertical
convection and thermal conductivity of package and board.
This section describes the impact of these parameters on the
junction temperature and gives a guideline to estimate the
MPC9443 die junction temperature and the associated
device reliability. For a complete analysis of power
consumption as a function of operating conditions and
associated long term device reliability please refer to the
application note AN1545. According the AN1545, the
long-term device reliability is a function of the die junction
temperature:
Where Rthja is the thermal impedance of the package
(junction to ambient) and TA is the ambient temperature.
According to Table 13, the junction temperature can be used
to estimate the long-term device reliability. Further, combining
equation 1 and equation 2 results in a maximum operating
frequency for the MPC9443 in a series terminated
transmission line system.
Junction temperature (°C)
MTBF (Years)
100
20.4
TJ,MAX should be selected according to the MTBF system
requirements and Table 13. Rthja can be derived from Table
14. The Rthja represent data based on 1S2P boards, using
2S2P boards will result in a lower thermal impedance than
indicated below.
110
9.1
Table 14: Thermal package impedance of the 48ld LQFP
120
4.2
130
2.0
Table 13: Die junction temperature and MTBF
Convection, LFPM
Rthja (1P2S
board), K/W
Rthja (2P2S
board), K/W
Still air
69
53
64
50
Increased power consumption will increase the die
junction temperature and impact the device reliability
(MTBF). According to the system-defined tolerable MTBF, the
die junction temperature of the MPC9443 needs to be
controlled and the thermal impedance of the board/package
should be optimized. The power dissipated in the MPC9443
is represented in equation 1.
100 lfpm
200 lfpm
300 lfpm
400 lfpm
500 lfpm
Where ICCQ is the static current consumption of the
MPC9443, CPD is the power dissipation capacitance per
output, (Μ)ΣCL represents the external capacitive output
load, N is the number of active outputs (N is always 16 in case
of the MPC9443). The MPC9443 supports driving
transmission lines to maintain high signal integrity and tight
timing parameters. Any transmission line will hide the lumped
capacitive load at the end of the board trace, therefore, ΣCL is
zero for controlled transmission line systems and can be
eliminated from equation 1. Using parallel termination output
termination results in equation 2 for power dissipation.
P TOT
+V @
CC
ƪ
P TOT
ICCQ
+
ƪ
)V @f
CC
ICCQ
CLOCK
)V @f
ǒ
CC
@ N@C
TJ
fCLOCK,MAX
@ N@C )
Ǔƫ
+T )P @R
A
2
CC
PD
CL
M
+ C @ N1 @ V @
PD
TIMING SOLUTIONS
ȍ
)ȍ
) ȍƪ
CLOCK
PD
ǒ
If the calculated maximum frequency is below 250 MHz, it
becomes the upper clock speed limit for the given application
conditions. The following eight derating charts describe the
safe frequency operation range for the MPC9443. The charts
were calculated for a maximum tolerable die junction
temperature of 110°C (120°C), corresponding to an
estimated MTBF of 9.1 years (4 years), a supply voltage of
3.3V and series terminated transmission line or capacitive
loading. Depending on a given set of these operating
conditions and the available device convection a decision on
the maximum operating frequency can be made.
ƪ
TOT
Ǔƫ
CL
M
DC Q
P
@V
@ I @ ǒV * V Ǔ ) ǒ1 * DC Ǔ @ I @ V
OH
thja
* * ǒI @ V
T J,MAX T A
R thja
CCQ
Equation 1
CC
CC
CC
OH
ƫ
Ǔ
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Q
OL
ƫ
OL
Equation 2
Equation 3
Equation 4
MOTOROLA
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
MPC9443
Figure 6. Maximum MPC9443 frequency, VCC = 3.3V, MTBF
9.1 years, driving series terminated transmission lines
Figure 7. Maximum MPC9443 frequency, VCC = 3.3V,
MTBF 9.1 years, 4 pF load per line
Figure 8. Maximum MPC9443 frequency, VCC = 3.3V, MTBF
4 years, driving series terminated transmission lines
Figure 9. Maximum MPC9443 frequency, VCC = 3.3V,
MTBF 4 years, 4 pF load per line
MOTOROLA
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TIMING SOLUTIONS
Freescale Semiconductor, Inc.
MPC9443
DUT MPC9443
Pulse
Generator
Z = 50
ZO = 50Ω
ZO = 50Ω
W
RT = 50Ω
RT = 50Ω
VTT
VTT
Figure 10. CCLK MPC9443 AC test reference for Vcc = 3.3V and Vcc = 2.5V
DUT MPC9443
ZO = 50Ω
Differential
Pulse Generator
Z = 50
ZO = 50Ω
Freescale Semiconductor, Inc...
W
RT = 50Ω
RT = 50Ω
VTT
VTT
Figure 11. PCLK MPC9443 AC test reference
PCLK
VCC
VCC 2
B
CCLK
VCMR
VPP
PCLK
GND
VCC
VCC 2
B
QX
VCC
VCC 2
B
QX
GND
t(LH)
GND
t(HL)
t(HL)
t(LH)
Figure 12. Propagation delay (tPD) test reference
VCC
VCC 2
B
Figure 13. Propagation delay (tPD) test reference
VCC
VCC 2
B
CCLK
GND
GND
VOH
VCC 2
B
VCC
VCC 2
B
QX
GND
GND
tSK(LH)
tSK(HL)
The pin–to–pin skew is defined as the worst case difference
in propagation delay between any two similar delay paths
within a single device
Figure 14. Output–to–output Skew tSK(LH, HL)
TIMING SOLUTIONS
t(LH)
t(HL)
tSK(P) = | tPLH – tPHL |
Figure 15. Output Pulse Skew tSK(P) test reference
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MOTOROLA
Freescale Semiconductor, Inc.
MPC9443
VCC
VCC 2
B
GND
tP
T0
DC = tP /T0 x 100%
The time from the PLL controlled edge to the non controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage
Freescale Semiconductor, Inc...
Figure 16. Output Duty Cycle (DC)
tF
TN
TN+1
VCC=2.5V
1.8V
0.55
0.6V
tR
Figure 17. Output Transition Time test reference
VCC
VCC 2
B
CCLK
PCLK
TJIT(CC) = |TN –TN+1 |
VCC=3.3V
2.4
GND
VCC
VCC 2
B
CLK_STOP
GND
The variation in cycle time of a signal between adjacent cycles,
over a random sample of adjacent cycle pairs
Figure 18. Cycle–to–cycle Jitter
MOTOROLA
tS
tH
Figure 19. Setup and hold time (tS, tH) test reference
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TIMING SOLUTIONS
Freescale Semiconductor, Inc.
MPC9443
OUTLINE DIMENSIONS
FA SUFFIX
LQFP PACKAGE
CASE 932-03
ISSUE F
4X
0.200 AB T–U Z
DETAIL Y
A
P
A1
48
37
36
U
B
V
AE
B1
12
25
13
AE
V1
24
DIM
A
A1
B
B1
C
D
E
F
G
H
J
K
L
M
N
P
R
S
S1
V
V1
W
AA
Z
S1
T, U, Z
S
DETAIL Y
4X
0.200 AC T–U Z
0.080 AC
G
AB
AD
AC
ÎÎÎ
ÏÏÏ
ÎÎÎ
ÏÏÏ
ÎÎÎ
MILLIMETERS
MIN
MAX
7.000 BSC
3.500 BSC
7.000 BSC
3.500 BSC
1.400
1.600
0.170
0.270
1.350
1.450
0.170
0.230
0.500 BSC
0.050
0.150
0.090
0.200
0.500
0.700
0 _
7_
12 _REF
0.090
0.160
0.250 BSC
0.150
0.250
9.000 BSC
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
M_
BASE METAL
TOP & BOTTOM
N
R
J
0.250
Freescale Semiconductor, Inc...
1
T
C
E
GAUGE PLANE
9
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE AB IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS T, U, AND Z TO BE DETERMINED AT
DATUM PLANE AB.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE AC.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.250 PER SIDE. DIMENSIONS A AND B DO
INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE AB.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.350.
8. MINIMUM SOLDER PLATE THICKNESS SHALL BE
0.0076.
9. EXACT SHAPE OF EACH CORNER IS OPTIONAL.
F
D
0.080
M
AC T–U Z
SECTION AE–AE
W
H
L_
K
DETAIL AD
AA
TIMING SOLUTIONS
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MOTOROLA
Freescale Semiconductor, Inc.
MPC9443
Freescale Semiconductor, Inc...
NOTES
MOTOROLA
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TIMING SOLUTIONS
Freescale Semiconductor, Inc.
MPC9443
Freescale Semiconductor, Inc...
NOTES
TIMING SOLUTIONS
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MOTOROLA
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
MPC9443
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
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MOTOROLA and the
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E Motorola, Inc. 2002.
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MOTOROLA
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MPC9443/D
TIMING
SOLUTIONS