AKM AK8180D

AK8180D
2.5V, 3.3V LVCMOS 1:10
Clock Fanout Buffer
AK8180D
Features
Description
The AK8180D is a member of AKM’ｓ LVCMOS
clock fanout buffer family designed for telecom,
networking and computer applications, requiring a
range of clocks with high performance and low
skew. The AK8180D distributes 10 buffered
clocks configured by pin-setting per bank. The 10
outputs can drive 10 terminated 50  clock lines.
3 – 3 – 4 configurable 10 LVCMOS outputs
Translate LVPECL input to LVCMOS output
Single, dual and mixed voltage supply
available on 2.5V and 3.3V
Clock output frequency up to 250MHz
Output-to-output skew : 200ps max
High-impedance output control
Enable to drive up to 20 series terminated
clock lines
Operating Temperature Range: -40 to +85℃
Package: 32-pin LQFP (Pb free)
Pin compatible with MPC9456
AK8180D are derived from AKM’ｓ long-termexperienced clock device technology, and enable
clock output to perform low skew. The AK8180D
is available in a 7mm x 7mm 32-pin LQFP
package.
Block Diagram
MS1306-E-01
Oct-2011
-1-
AK8180D
GND
QB0
VDDB
QB1
GND
QB2
VDDB
VDDC
Pin Descriptions
24
23
22
21
20
19
18
17
VDDA
25
16
QC3
QA2
26
15
GND
GND
27
14
QC2
QA1
28
13
VDDC
VDDA
29
12
QC1
QA0
30
11
GND
GND
31
10
QC0
MR/OE
32
9
VDDC
4
5
6
PCLKn
DSELA
DSELB
7
8
GND
3
DSELC
2
PCLKp
NC
1
VDD
AK8180D
Package: 32-Pin LQFP(Top View)
Pin No.
Pin Name
Pin
Type
Pullup
/down
Description
1
NC
---
--
No internal connection
2
VDD
--
--
Power Supply
3
PCLKp
IN
PD
4
PCLKn
IN
PU/PD
5
DSELA
IN
PD
Divide Select Input for Output Bank A
6
DSELB
IN
PD
Divide Select Input for Output Bank B
7
DSELC
IN
PD
Divide Select Input for Output Bank C
8,
GND
--
--
Ground
LVPECL Differential Clock Inputs
9
VDDC
--
--
Power Supply for Output bank C
10
QC0
OUT
--
Clock output Bank C
11
GND
--
--
Ground
12
QC1
OUT
--
Clock output Bank C
(continued on next page)
Oct-2011
MS1306-E-01
-2-
AK8180D
Pin No.
Pin Name
Pin
Type
Pullup
/down
Description
13
VDDC
--
--
Power Supply for Output bank C
14
QC2
OUT
--
Clock output Bank C
15
GND
--
--
Ground
16
QC3
OUT
--
Clock output Bank C
17
VDDC
--
--
Power Supply for Output bank C
18
VDDB
--
--
Power Supply for Output bank B
19
QB2
OUT
--
Clock output Bank B
20
GND
--
--
Ground
21
QB1
OUT
--
Clock output Bank B
22
VDDB
--
--
Power Supply for Output bank B
23
QB0
OUT
--
Clock output Bank B
24
GND
--
--
Ground
25
VDDA
--
--
Power Supply for Output bank A
26
QA2
OUT
--
Clock output Bank A
27
GND
--
--
Ground
28
QA1
OUT
--
Clock output Bank A
29
VDDA
--
--
Power Supply for Output bank A
30
QA0
OUT
--
Clock output Bank A
31
GND
--
--
32
MR/ OE
IN
PD
Ground
Master Reset and Output Enable
(Output disable = High impedance)
PU: Pull up PD: Pull down
Ordering Information
Part Number
Marking
Shipping
Packaging
Package
Temperature
Range
AK8180D
AK8180D
Tape and Reel
32-pin LQFP
-40 to 85 ℃
MS1306-E-01
Oct-2011
-3-
AK8180D
Absolute Maximum Rating
Over operating free-air temperature range unless otherwise noted
Items
Supply voltage
Input voltage
Symbol
Ratings
Unit
VDD
-0.3 to 4.6
V
Vin
GND-0.3 to VDD+0.3
V
IIN
±10
mA
Tstg
-55 to 130
C
Input current (any pins except supplies)
Storage temperature
(1)
Note
(1) Stress beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
These are stress ratings only. Functional operation of the device at these or any other conditions beyond those
indicated under “Recommended Operating Conditions” is not implied. Exposure to absolute-maximum-rating
conditions for extended periods may affect device reliability. Electrical parameters are guaranteed only over the
recommended operating temperature range.
ESD Sensitive Device
This device is manufactured on a CMOS process, therefore, generically susceptible to
damage by excessive static voltage. Failure to observe proper handling and
installation procedures can cause damage. AKM recommends that this device is handled with
appropriate precautions.
Recommended Operation Conditions
Parameter
Operating temperature
Supply voltage (1)
Symbol
Conditions
Min
Ta
Typ
-40
VDD
VDD5%
(1) Power of 2.5V or 3.3V requires to be supplied from a single source.
should be located close to each VDD pin.
Max
Unit
85
C
2.375
2.5
2.625
3.135
3.3
3.465
V
A decoupling capacitor of 0.1F for power supply line
Supported VDD Supply Voltage Configurations
Supply Voltage
Configuration
VDD
VDDA
VDDB
VDDC
GND
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
0V
3.3 V and 2.5 V
3.3 V
3.3 V or 2.5 V
2.5 V
2.5 V
2.5 V
3.3 V or 2.5 V 3.3 V or 2.5 V
2.5 V
0V
2.5 V
0V
General Specification
Parameter
Symbol
Conditions
Min
Typ
Unit
Output Termination Voltage
VTT
ESD Protection 1
MM
Machine model
200
V
ESD Protection 2
HBM
Human Body Model
2000
V
200
mA
Latch-Up Immunity
Power Dissipation Capacitance
VDD/2
Max
LU
per output
Input Capacitance
Oct-2011
V
10
pF
4.0
pF
MS1306-E-01
-4-
AK8180D
Power Supply Current <3.3V>
Parameter
Full operation
Symbol
(1)
Quiescent state
VDD= 3.3V5%, Ta: -40 to +85℃
IDD1
(1)(2)
Conditions
Min
CCLK0=250MHz
CLK_SEL=L
IDD2
(1) The outputs have no loads.
Typ
Max
Unit
95
120
mA
1.6
2.6
mA
(2) All inputs are in default state by the internal pull up/down resisters.
DC Characteristics <3.3V>
All specifications at VDD=VDDA=VDDB=VDDC= 3.3V5%, Ta: -40 to +85℃, unless otherwise noted
Parameter
Symbol
Conditions
MIN
TYP
MAX
Unit
High Level Input Voltage
VIH
LVCMOS
2.0
VDD+0.3
V
Low Level Input Voltage
VIL
LVCMOS
-0.3
0.8
V
Vpp
LVPECL
250
Vcmr
LCPECL
1.1
Peak-to-Peak Input Voltage
Common Mode Range
Input Current
(1)
(2)
High Level Output Voltage
Low level Output Voltage
I L1
Vin=GND or VDD
VOH
IOH= -24mA
(3)
IOL= +24mA
IOL= +12mA
(3)
VOL
mV
VDD-0.6
V
200
μA
2.4
V
0.55
0.30
Output Impedance
V

14-17
(1)
Vcmr(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within t he
Vcmr range and the input swing lies within the Vpp(DC) specification.
(2)
Input pull-up / pull down resistors influence input current.
(3)
The AK8180D is capable of driving 50  transmission lines of the incident edge. Each output drives one 50  parallel
terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50  series
terminated transmission lines.
(4)
IDDQ is the DC current consumption of the device with all outputs open and the input in its default state or
open.
AC Characteristics <3.3V> (1)
All specifications at VDD=VDDA=VDDB=VDDC= 3.3V5%,
Parameter
Symbol
Ta: -40 to +85℃, unless otherwise noted
Conditions
MIN
TYP
MAX
Unit
250
MHz
Input Frequency
fIN
Pin: PCLKp/n
0
Input Pulse Width
tpwIN
Pin: PCLKp/n
1.4
ns
500
1000
mV
1.3
VDD-0.8
Peak-to-Peak Input Voltage Vpp
Common Mode Range
Input Rise/Fall time
(2)
(3)
Output Frequency
Pin: PCLKp/n
Vcmr
Pin: PCLKp/n
trIN,tfOUT
Pin: PCLKp/n
fOUT
Pin: Q0-11
0.8 to 2.0V
0
1.0
ns
250
MHz
3.55
ns
10
ns
10
ns
Output Disable Time
tPLH
tPHL
tPLZ,tPHZ
Output Enable Time
tPZL,tPZH
Output-to-Output Skew
tskPP
Device-to-Device Skew
tskD
150
200
350
2.25
tskO
200
Propagation Delay
Output Pulse Skew
(4)
PCLK to any Q
Within one bank
Any output, same output divider
Any output, Any output divider
1.3
2.2
ps
ns
ps
(continued on next page)
MS1306-E-01
Oct-2011
-5-
AK8180D
Parameter
Symbol
Output Duty Cycle
DCOUT
Output Rise/Fall Time
tr, tf
Conditions
DCREF= 50%
x1 output
DCREF= 25-75% x1/2 output
0.55 to 2.4V
MIN
TYP
MAX
45
47
0.1
50
50
55
53
1.0
Unit
%
ns
AC characteristics apply for parallel output termination of 50  to VTT.
The AK8180D is functional up to an input and output clock frequency of 350MHz and is characterized up to 250MHz.
Vcmr(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within
the Vcmr range and the input swing lies within the Vpp(AC) specification. Violation of Vcmr or Vpp impacts tPLH/PHL and tskD.
(4) Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, devi ce-to-device skew,
input pulse width, output duty cycle and maximum frequency specifications .
(5) Output pulse skew tskO is the absolute difference of the propagation delay times :| tPLH - tPHL |.
Output duty cycle is frequency dependent (= 0.5  tskO x fout). For example at fout = 125 MHz the output duty
cycle limit is 50%  2.5%.
(1)
(2)
(3)
Power Supply Current <2.5V>
Parameter
Full operation
Symbol
(1)
Quiescent state
VDD= 2.5V5%, Ta: -40 to +85℃
IDD1
(1)(2)
Conditions
Min
CCLK0=250MHz
CLK_SEL=L
IDD2
(1) The outputs have no loads.
Typ
Max
Unit
71
95
mA
1.6
2.5
mA
(2) All inputs are in default state by the internal pull up/down resisters.
DC Characteristics <2.5V>
All specifications at VDD=VDDA=VDDB=VDDC= 2.5V5%, Ta: -40 to +85℃, unless otherwise noted
Parameter
Symbol
Conditions
MIN
TYP
MAX
Unit
V
VIH
LVCMOS
1.7
VDD+0.3
Low Level Input Voltage
VIL
LVCMOS
-0.3
0.7
Peak-to-Peak Input Voltage
Vpp
LVPECL
250
Vcmr
LVPECL
1.1
High Level Input Voltage
Common Mode Range
Input Current
(1)
(２)
High Level Output Voltage
Low level Output Voltage
IL1
VOH
VOL
Vin=GND or VDD
IOH= -15mA
(３)
IOL= +15mA
(３)
Output Impedance
V
mV
VDD-0.7
V
200
μA
1.8
V
0.6
17-20
V

(1)
Vcmr(DC) is the crosspoint of the differential input signal. Functional operation is o btained when the crosspoint is within the
Vcmr range and the input swing lies within the Vpp(DC) specification.
(2)
Input pull-up / pull down resistors influence input current.
(3)
The AK8180D is capable of driving 50  transmission lines of the incident edge. Each output drives one 50  parallel
terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50  series
terminated transmission lines.
IDDQ is the DC current consumption of the device with all outputs open an d the input in its default state or open.
(4)
Oct-2011
MS1306-E-01
-6-
AK8180D
AC Characteristics <2.5V> (1)
All specifications at VDD=VDDA=VDDB=VDDC= 2.5V5%,
Parameter
Input Frequency
Symbol
(2)
Ta: -40 to +85℃, unless otherwise noted
Conditions
MIN
TYP
MAX
Unit
250
MHz
fIN
Pin: PCLKp/n
tpwIN
Pin: PCLKp/n
1.4
Peak-to-Peak Input Voltage Vpp
Pin: PCLKp/n
500
1000
Pin: PCLKp/n
1.1
VDD-0.7
Input Pulse Width
Common Mode Range
Input Rise/Fall time
Output Frequency
(2)
(3)
(2)
Vcmr
trIN,tfOUT Pin: PCLKp/n
fOUT
tPLH
Propagation Delay
tPHL
ns
0.8 to 2.0V
1.0
DSELx = 0
x1 output
250
DSELx = 1
x1/2 output
125
PCLKp/n to any Q
1.4
2.4
mV
ns
MHz
4.4
ns
Output Disable Time
tPLZ,tPHZ
10
ns
Output Enable Time
tPZL,tPZH
10
ns
Output-to-Output Skew
tskPP
Device-to-Device Skew
tskD
3.0
ns
tskO
200
ps
Output Pulse Skew
(4)
Within one bank
150
Any output, same output divider
200
Any output, Any output divider
350
Output Duty Cycle
DCOUT
DCREF= 50%
Output Rise/Fall Time
tr, tf
0.6 to 1.8V
x1 or 1/2 output
45
50
0.1
ps
55
%
1.0
ns
(1)
AC characteristics apply for parallel output termination of 50  to VTT.
(2)
The AK8180D is functional up to an input and output clock frequency of 350MHz and is characterized up to 250MHz.
(3)
Violation of the 1.0 ns maximum input rise and fall tim e limit will affect the device propagation delay, device-to-device skew,
input pulse width, output duty cycle and maximum frequency specifications.
(4)
Output pulse skew tskO is the absolute difference of the propagation delay times:| tPLH - tPHL |.
Output duty cycle is frequency dependent (= 0.5  tskO x fout). For example at fout = 125 MHz the output duty
cycle limit is 50%  2.5%.
AC Characteristics <mixed with 3.3V and 2.5V> (1)(2)
All specifications at VDD, VDDB= 3.3V5%, VDDA, VDDC=2.5V5%, Ta: -40 to +85℃, unless otherwise noted
Parameter
Symbol
Propagation Delay
tPLH、tPHL
Output-to-Output Skew
Device-to-Device Skew
Output Pulse Skew
(3)
Output Duty Cycle
tskPP
Conditions
MIN
PCLK to any Q
TYP
See 3.3V table
150
Any output, same output divider
250
Any output, Any output divider
350
tskO
DCREF= 50%
x1 or 1/2 output
45
50
ps
2.5
ns
250
ps
55
%
(1)
AC characteristics apply for parallel output termination of 50  to VTT.
(2)
For all other AC specifications, refer to 2.5V and 3.3V tables according to the supply voltage of the output bank .
(3)
Unit
ns
Within one bank
tskD
DCOUT
MAX
Output pulse skew tskO is the absolute difference of the propagation delay times:| tPLH - tPHL |.
Output duty cycle is frequency dependent (= 0.5  tskO x fout). For example at fout = 125 MHz the output duty
cycle limit is 50%  2.5%.
MS1306-E-01
Oct-2011
-7-
AK8180D
Figure 1
PCLK/PCLKn AC Test Reference
Figure 2 Output Translation Time Test Reference
Figure 4 Output-to-Output Skew
Figure 3
Propagation Delay Test Reference
Figure 5
Oct-2011
Output Duty Cycle (DC)
MS1306-E-01
-8-
AK8180D
Function Table
The following table shows the inputs/outputs clock state configured through the control pins.
Table 1: Control-Pin-Setting Function Table
Control Pin
Default
0
1
DSELA
0
QA0-2 = REFCLK x 1
QA0-2 = REFCLK x 1/2
DSELB
0
QB0-2 = REFCLK x 1
QB0-2 = REFCLK x 1/2
DSELC
0
QC0-3 = REFCLK x 1
QC0-3 = REFCLK x 1/2
MR/ OE
0
Output enabled
MS1306-E-01
Internal reset. Outputs disabled.
(High impedance)
Oct-2011
-9-
AK8180D
Package Information
 Mechanical data :
32-lead LQFP
9.00±0.20
7.00
17
25
16
32
9
7.00
0.80
8
0.30～0.45
0.10
M
1゜～5゜
1.60MAX
1
1.35～1.45
9.00±0.20
24
0.40～0.80
0.10
Oct-2011
S
0.05～0.15
0.09～0.20
S
MS1306-E-01
- 10 -
AK8180D
 Marking
a:
b:
c:
#1 Pin Index
Part number
Date code (7 digits)
b
c
a
AKM and the logo -
- are the brand of AKM’ｓ IC’s and identify that AKM
continues to offer the best choice for high performance mixed-signal solution under
this brand.
 RoHS Compliance
All integrated circuits form Asahi Kasei Microdevices Corporation (AKM)
assembled in “lead-free” packages* are fully compliant with RoHS.
(*) RoHS compliant products from AKM are identified with “Pb free” letter indication on
product label posted on the anti-shield bag and boxes.
MS1306-E-01
Oct-2011
- 11 -
AK8180D
IMPORTANT NOTICE
 These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
 Descriptions of external circuits, application circuits, software and other related information contained in this
document are provided only to illustrate the operation and application examples of the semiconductor products. You
are fully responsible for the incorporation of these external circuits, application circuits, software and other related
information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third
parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent,
intellectual property, or other rights in the application or use of such information contained herein.
 Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
 AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it,
and which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety
or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or
perform may reasonably be expected to result in loss of life or in significant injury or damage to person or
property.
 It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places
the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer
or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all
claims arising from the use of said product in the absence of such notification.
Oct-2011
MS1306-E-01
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