[AK7756] AK7756 DSP with Mono CODEC + Mic/Lineout Amp GENERAL DESCRIPTION The AK7756 is a highly integrated digital signal processor, including a mono voice audio codec, a MIC pre-amplifier and digital audio I/F. The audio DSP has 9216step at fs = 8kHz parallel processing power. As the AK7756 is a RAM based DSP, it is programmable for user requirements such as hands free and acoustic effect. The AK7756EN is available in a space saving small 28pin QFN package and the AK7756VF is available in a 30pin VSOP package. FEATURES DSP - Word length: 24bit (Data RAM 24bit floating point) - Instruction cycle: 13.6 ns (9216 steps at fs=8 kHz) - Multiplier 20 x 20 → 36bit (double precision available) - Divider 20 / 20 → 20bit - ALU: 36bit arithmetic operation (with overflow margin 4bit) 24bit floating point arithmetic and logic operation - Program RAM: 3072 x 36bit - Coefficient RAM: 2048 x 20bit - Data RAM: 1024 x 24-bit (24bit floating point) - Delay RAM: 3072 x 20bit, 3072 x 20bit - Master Clock: 4.6MHz ~ 73.7MHz - JX pins (Interrupt) Audio Serial I/F - Master / Slave operation - Right / Left justified and I2S - PCM (Short / Long Frame) - 16bit linear, 8bit A-law, 8bit µ-law Mono CODEC - Sampling Rate 8KHz, 16KHz - DAC S/N: 91dB, S/(N+D): 83dB (fs:16kHz) - ADC S/N: 86dB, S/(N+D): 77dB (fs:16kHz) Microphone interface - Differential or single-ended input - Programmable Gain (+33dB ~ +15dB and 0dB, 3dB step) - Low Noise Microphone Bias Automatic Power Down (CODEC, DSP) μP I/F : SPI, I2C-slave I2C bootloader Power supply Analog (AVDD) : 3.0V ~ 3.6V (typ.3.3V) Digital1 (DVDD) : 3.0V ~ 3.6V (typ.3.3V) Digital2 (DVDD18) : 1.7V ~ 1.9V (typ.1.8V) Operating temperature range: -20°C ~ 85°C (AK7756EN), -40°C ~ 85°C (AK7756VF) Package: 28pin QFN (AK7756EN) 30pin VSOP (AK7756VF) MS1218-E-00-PB 2010/08 1 [AK7756] ■ Block Diagram MPRF AVDD VSS2 DVDD VCOM DVDD18 VSS1 PMMB MICBIAS Mic AIN/INP AKM DSP Core MIC Power Supply XTO PLL LFLT PMADC I2S or PCM Interface SELDI2 A/D DIN2 INN SELDO2 JX1 DOUT2 PMDAC SDOUT2/RDY EXTEEP/RQN μP (I2C,SPI)/ EEPROM (I2C) Interface AOUT D/A SDIN1 STO/RDY/SDOUT1 RDY Line Out LRCK SDOUT1 WDT/ CRC JX1E JX1 BICK SELDO1 JX0 JX0/SDIN2 DIN1 DOUT1 JX0E XTI DOUT3 SCL/SCLK SDA/SO I2CSEL pin SI I2CSEL EEST/SDOUT3/SI EEST SELDO3 PMOSC OSC Memory IRSTN Figure 1. Block Diagram MS1218-E-00-PB 2010/08 2 [AK7756] ■ ■ Ordering Guide AK7756EN AK7756VF -20 ∼ +85°C -40 ∼ +85°C AKD7756HFS Evaluation Board for AK7756 28pin QFN 30pin VSOP Pin Layout SDOUT2/RDY LRCK BICK SDIN1 IRSTN JX1 AOUT AK7756EN 21 20 19 18 17 16 15 MPRF 22 14 STO/RDY/SDOUT1 VCOM 23 13 SDA/SO VSS2 24 12 SCL/SCLK AVDD 25 11 EEST/SDOUT3/ SI MICBIAS 26 10 EXTEEP/RQN INP/AIN 27 9 JX0/SDIN2 INN 28 8 SDOUT1 MS1218-E-00-PB 5 6 7 VSS1 DVDD 4 DVDD18 3 XTI I2CSEL LFLT 1 2 XTO Top View 2010/08 3 [AK7756] AK7756VF DVDD18 1 30 XTI VSS1 2 29 XTO DVDD 3 28 I2CSEL SDOUT1 4 27 LFLT JX0/SDIN2 5 26 INN EXTEEP/RQN 6 25 INP/AIN EEST/SDOUT3/SI 7 24 MICBIAS SCL/SCLK 8 23 AVDD SDA/SO 9 22 AVDD STO/RDY/SDOUT1 10 21 VSS2 SDOUT2/RDY 11 20 VCOM NC 12 19 MPRF LRCK 13 18 AOUT BICK 14 17 JX1 SDIN1 15 16 IRSTN AK7756VF Top View MS1218-E-00-PB 2010/08 4 [AK7756] ■ DSP Block Diagram CP0, CP1 DLP0, DLP1 DP0, DP1 DLRAM DRAM 512w × 24-Bit 512w × 24-Bit CRAM 2048w x 20-Bit DLRAM Address Pointer OFREG 32w x 13-Bit 3072w x 20-Bit 3072w x 20-Bit CBUS(20-Bit) DBUS(24-Bit) MPX20 µP I/F MPX20 X Control PRAM DEC Y Serial I/F 3072w x 36-Bit Multiply 20 x 20 → 36-Bit PC Stack: 5 level(max) TMP 12 x 24-Bit 24-Bit 36-Bit PTMP(LIFO) 6 x 24-Bit MUL DBUS SHIFT 40-Bit 40-Bit A B ALU 40-Bit Overflow Margin: 4-Bit 1 x 24-Bit DIN2 (ADC or SDIN2 pin) 2 x 24-Bit DIN1 40-Bit DR0 ∼ 3 40-Bit Over Flow Data Generator Division 20÷20→20 1 x 24-Bit 2 x 24-Bit DOUT3 (DAC or SDOUT3pin) DOUT2 2 x 24-Bit DOUT1 Peak Detector MS1218-E-00-PB 2010/08 5 [AK7756] PIN/FUNCTION (AK7756EN) No. Pin Name 1 LFLT O 2 3 4 5 6 7 8 I2CSEL XTO XTI DVDD18 VSS1 DVDD SDOUT1 JX0 SDIN2 I O I O I I EXTEEP I RQN I EEST O SDOUT3 O SI I SCL I SCLK I SDA I/O 9 I/O 10 11 12 13 SO O STO RDY SDOUT1 O O O 15 SDOUT2 RDY O O 16 17 18 LRCK BICK SDIN1 I/O I/O I 19 IRSTN I 20 21 JX1 AOUT I O 22 MPRF O 14 Function Output Pin for Loop Filter of PLL Circuit This pin must be connected to VSS2 with 8.2KΩ and 33nF in series. Outputs “L” during initial reset. μP Control Mode Select Pin “H”: I2C, “L”: SPI Master Clock Output Pin. Outputs Hi-Z during initial reset. External Master Clock Input Pin Digital Power Supply 2 Pin. 1.7 ∼ 1.9V Ground Pin Digital Power Supply 1 Pin. 3.0 ∼ 3.6V Audio Serial Data Output1 Pin. Outputs “L” during initial reset. Conditional Jump Pin0 (JXOE bit = “1”) Audio Serial Data Input 2 Pin (JXOE bit = “0”) Start to Download from external EEPROM (I2CSEL pin = “H” : I2C Bus Mode) “H”: start download (download from external memory) “L”: normal operation μP I/F Write Request Pin (I2CSEL pin = “L” : SPI Mode) When initial reset and μP I/F are not in use, leave the RQN pin High level. EEPROM download busy output (I2CSEL pin = “H” and SELDO3 bit = “0”) H: Download is busy. L: download is complete. Outputs “L” during initial reset. Audio Serial Data Output Pin3 (I2CSEL pin = “H” and SELDO3 bit = “1”) Outputs “L” during initial reset. Control Data Input Pin (I2CSEL pin = “L”: SPI Mode) Control Data Clock Pin (I2CSEL pin = “H”: I2C Bus Mode) Outputs Hi-Z during initial reset. Control Data Clock Pin (I2CSEL pin = “L”: SPI Mode) Set this pin to “H” when there are no clock inputs. Control Data Input /Output Pin (I2CSEL pin = “H”: I2C Bus Mode) Outputs Hi-Z during initial reset. Control Data output Pin (I2CSEL pin = “L”: SPI Mode) Outputs “L” during initial reset. Status Output Pin Data Write Ready Output Pin for μP Interface Audio Serial Data Output Pin1 Outputs “H” during initial reset. Audio Serial Data Output2 Pin Data Write Ready Output Pin for μP Interface Outputs “L” during initial reset. Audio channel select Pin Audio Serial Data Clock Pin Audio Serial Data Input 1 Pin Reset Pin (active low) The AK7756 must be reset once upon power-up. “H”: Power-up, “L”: Initialize the control register. Conditional Jump Pin1 Analog Output Outputs. Outputs VSS2 during initial reset. Output Pin for Ripple Filter of MICBIAS Circuit Connect 1.0μF capacitor to VSS2. Outputs AVDD during initial reset. MS1218-E-00-PB 2010/08 6 [AK7756] Analog Common Voltage Output Pin Connect 0.1μF and 2.2μF capacitor to VSS2. Outputs VSS2 during initial reset. 24 VSS2 Ground Pin 25 AVDD Analog Power Supply Pin 3.0 ∼ 3.6V 26 MICBIAS O Microphone bias. Outputs Hi-Z during initial reset. AIN I Single-ended Analog Input pin (MDIF bit = “0”) 27 INP I Positive Microphone input pin (MDIF bit = “1”) 28 INN I Negative Microphone input pin (MDIF bit = “1”) Note 1. All digital input pins must not be left floating. Note 2. DVDD or VSS1 voltage must be input to the I2CSEL pin. Note 3. All analog input pins (INP/AIN, INN pins) must be supplied signal via AC-coupling capacitor. Note 4. Analog output pins (AOUT pin) must deliver signal via AC-coupling capacitor 23 VCOM O PIN/FUNCTION (AK7756VF) No. 1 2 3 Pin Name DVDD18 VSS1 DVDD I/O - 4 SDOUT1 O 5 JX0 SDIN2 I I EXTEEP I RQN I EEST O SDOUT3 O SI I SCL I SCLK I SDA I/O 6 7 8 9 SO O STO RDY SDOUT1 O O O 11 SDOUT2 RDY O O 12 NC - 10 Function Digital Power Supply 2 Pin. 1.7 ∼ 1.9V Ground Pin Digital Power Supply 1 Pin. 3.0 ∼ 3.6V Audio Serial Data Output1 Pin. Outputs “L” during initial reset. Conditional Jump Pin0 (JXOE bit = “1”) Audio Serial Data Input 2 Pin (JXOE bit = “0”) Start to Download from external EEPROM (I2CSEL pin = “H” : I2C Bus Mode) “H”: start download (download from external memory) “L”: normal operation μP I/F Write Request Pin (I2CSEL pin = “L” : SPI Mode) When initial reset and μP I/F are not in use, leave the RQN pin High level. EEPROM download busy output (I2CSEL pin = “H” and SELDO3 bit = “0”) H: Download is busy. L: download is complete. Outputs “L” during initial reset. Audio Serial Data Output Pin3 (I2CSEL pin = “H” and SELDO3 bit = “1”) Outputs “L” during initial reset. Control Data Input Pin (I2CSEL pin = “L”: SPI Mode) Control Data Clock Pin (I2CSEL pin = “H”: I2C Bus Mode) Outputs Hi-Z during initial reset. Control Data Clock Pin (I2CSEL pin = “L”: SPI Mode) Set this pin to “H” when there are no clock inputs. Control Data Input /Output Pin (I2CSEL pin = “H”: I2C Bus Mode) Outputs Hi-Z during initial reset. Control Data output Pin (I2CSEL pin = “L”: SPI Mode) Outputs “L” during initial reset. Status Output Pin Data Write Ready Output Pin for μP Interface Audio Serial Data Output Pin1 Outputs “H” during initial reset. Audio Serial Data Output2 Pin Data Write Ready Output Pin for μP Interface. Outputs “L” during initial reset. No Connect Pin. This pin must be connected to VSS1. MS1218-E-00-PB 2010/08 7 [AK7756] 13 14 15 Audio channel select Pin Audio Serial Data Clock Pin Audio Serial Data Input 1 Pin Reset Pin (active low) The AK7756VF must be reset once upon power-up. 16 IRSTN I “H”: Power-up, “L”: Initialize the control register. 17 JX1 I Conditional Jump Pin1 18 AOUT O Analog Output Outputs. Outputs VSS2 during initial reset. Output Pin for Ripple Filter of MICBIAS Circuit 19 MPRF O Connect 1.0μF capacitor to VSS2. Outputs AVDD during initial reset. Analog Common Voltage Output Pin 20 VCOM O Connect 0.1μF and 2.2μF capacitor to VSS2. Outputs VSS2 during initial reset. 21 VSS2 Ground Pin 22 AVDD Analog Power Supply Pin 3.0 ∼ 3.6V 23 AVDD Analog Power Supply Pin 3.0 ∼ 3.6V 24 MICBIAS O Microphone bias. Outputs Hi-Z during initial reset. AIN I Single-ended Analog Input pin (MDIF bit = “0”) 25 INP I Positive Microphone input pin (MDIF bit = “1”) 26 INN I Negative Microphone input pin (MDIF bit = “1”) Output Pin for Loop Filter of PLL Circuit 27 LFLT O This pin must be connected to VSS2 with 8.2KΩ and 33nF in series. Outputs “L” during initial reset. 28 I2CSEL I μP Control Mode Select Pin “H”: I2C, “L”: SPI 29 XTO O Master Clock Output Pin. Outputs Hi-Z during initial reset. 30 XTI I External Master Clock Input Pin Note 1. All digital input pins must not be left floating. Note 2. DVDD or VSS1 voltage must be input to the I2CSEL pin. Note 3. All analog input pins (INP/AIN, INN pins) must be supplied signal via AC-coupling capacitor. Note 4. Analog output pins (AOUT pin) must deliver signal via AC-coupling capacitor ■ LRCK BICK SDIN1 I/O I/O I Handling of Unused Pin The unused I/O pins must be processed appropriately as below. Classification Analog Digital Pin Name MICBIAS, INP/AIN, INN, AOUT, MPRF SDOUT1, STO/RDY/SDOUT1, SDOUT2/RDY, SDOUT3/EEST/ SI, XTO EXTEEP/RQN, SDIN1, XTI, JX0/SDIN2, JX1 MS1218-E-00-PB Setting These pins must be open. These pins must be open. These pins must be connected to VSS1. 2010/08 8 [AK7756] ABSOLUTE MAXIMUM RATINGS (VSS1=VSS2=0V; Note 5) Parameter Symbol min max Units Power Supplies: Analog AVDD 4.3 V −0.3 Digital 1 DVDD 4.3 V −0.3 Digital 2 DVDD18 2.5 V −0.3 Difference(VSS1~VSS2) ΔGND -0.3 0.3 V Input Current, Any Pin Except Supplies IIN mA ±10 Analog Input Voltage (Note 6) VINA (AVDD+0.3) or 4.3 V −0.3 Digital Input Voltage (Note 7) VIND1 (DVDD+0.3) or 4.3 V −0.3 AK7756EN Ta 85 −20 °C Ambient Temperature (powered applied) AK7756VF Ta 85 −40 °C Storage Temperature Tstg 150 −65 °C Note 5. All voltages with respect to ground. VSS1 and VSS2 must be the same voltage. Note 6. INP/AIN, INN pins Note 7. IRSTN, I2CSEL, EXTEEP, SI/EEST, SDA/SO, SCL/SCLK, JX1, JX0, SDIN1, LRCK, and BICK pins Note 8.Pull-up resistors at SDA and SCL pins must be connected to the DVDD voltage or less. Do not turn off the power supplies when the SDA and SCL pins are pulled-up to DVDD. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (VSS1=VSS2=0V; Note 5) Parameter Symbol min typ max Units Power Supplies Analog AVDD 3.0 3.3 3.6 V (Note 9) Digital DVDD 3.0 3.3 3.6 V Digital DVDD18 1.7 1.8 1.9 V Difference1 AVDD – DVDD -0.3 0 +0.3 V Note 5. All voltages with respect to ground. VSS1 and VSS2 must be the same voltage. Note 9. The power-up sequence between AVDD, DVDD and DVDD18 is not critical. But all power supplies must be ON before starting operation of the AK7756. * AKM assumes no responsibility for the usage beyond the conditions in this datasheet. MS1218-E-00-PB 2010/08 9 [AK7756] ANALOG CHARACTERISTICS (CODEC) ■ ADC Characteristics (Ta=25ºC; AVDD=DVDD=3.3V, DVDD18=1.8V; VSS1=VSS2=0V; BICK=64fs; Signal Frequency 1kHz; Measurement frequency =20Hz~8 kHz, fs=16 kHz, CKM mode 6, unless otherwise specified.) Parameter min typ max MIC Input Programmable Gain Amplifier Input Resistance (INP, INN pins) (MGAIN = 0dB) 22.5 30 37.5 Gain Min (MGAIN2-0 bit = “0H”) 0 Max (MGAIN2-0 bit = “7H”) +33 Step size (MGAIN2-0bit = “1H” ~ “7H”) 3 Microphone Bias Supply: MICBIAS pin Bias Output Voltage (Note 10) 2.32 Load Resistance 2.0 Load Capacitance 30 Resolution 24 Mono ADC Dynamic Characteristics AIN pin→ Mono ADC→ SDOUT1 MGAIN=21dB 72 S/(N+D) (-1dBFS) MGAIN= 0dB 69 77 MGAIN=21dB 77 Dynamic Range MGAIN= 0dB 78 86 MGAIN=21dB 77 S/N MGAIN= 0dB 78 86 Microphone Analog Inputs INP,INN (Note 11) Full-scale Input Voltage Units kΩ dB dB dB V kΩ pF Bits dB dB dB Differential MGAIN= 0dB ±2.0 ±2.2 ±2.4 Vpp Single-ended MGAIN= 0dB 2.0 2.2 2.4 VPP Note 10. The output voltage is proportional to AVDD. Vmic bias=0.70 * AVDD, Iout=1mA Note 11. The input voltage is proportional to AVDD. Vin=0.67 x AVDD (typ.) @MGAIN = 0dB MS1218-E-00-PB 2010/08 10 [AK7756] ■ DAC Characteristics (Ta=25ºC; AVDD=DVDD=3.3V, DVDD18=1.8V; VSS1=VSS2=0V; BICK=64fs; Signal frequency 1 kHz; Measurement frequency=20Hz~8 kHz, fs=16 kHz, CKM mode 6, unless otherwise specified.) Parameter min typ max Resolution 24 Mono DAC Dynamic Characteristics; Mono DAC→AOUT pin S/(N+D) (0dBFS) 75 83 S/N 83 91 Analog Output Full-scale Output Voltage (Note 12) 2.09 2.2 2.31 Load Resistance 10 Load Capacitance 30 Note 12. Full scale output voltage. The output voltage is proportional to AVDD. Vout=0.67 x AVDD (typ.) MS1218-E-00-PB Unit Bits dB dB Vpp kΩ pF 2010/08 11 [AK7756] DC CHARACTERISTICS (Ta=Tmin~Tmax; AVDD=DVDD=3.0~3.6V; DVDD18=1.7~1.9V; VSS1=VSS2=0V) Parameter Symbol min typ High level input voltage (Note 13) VIH 80%DVDD Low level input voltage (Note 13) VIL SCL, SDA High level input voltage VIH 70%DVDD SCL, SDA Low level input voltage VIL VOH DVDD-0.4 High level output voltage: Iout=-100μA (Note 14) VOL Low level output voltage: Iout=100μA (Note 14) SDA Low level output voltage Iout=3mA VOL Input leak current (Note 15) Iin Input leak current XTI pin Iix 26 Note 13. Except for the SCL/SCLK, SDA/SO pins. Note 14. Except for the SDA/SO pin. Note 15. Except for the XTI pin. max 20%DVDD 30%DVDD 0.4 0.4 ±10 Unit V V V V V V V μA μA POWER CONSUMPTION (Ta=25ºC; AVDD=DVDD=3.3V; DVDD18=1.8V; VSS1=VSS2=0V, fin=1 KHz, 24 bit, fs=8 KHz (CKM mode = 0), DSPS=BITFS=PMOSC bits= “0” PMMB bit=“1”, DSP running with programmed connecting DIN2 with DOUT1 and DIN1 with DOUT3.) Parameter min typ max Units Power Supplies: (Note 16) Power-Up (IRSTN pin = “H”) CODEC+DSP All Circuit Power-up AVDD+DVDD AVDD=DVDD=3.3V 11.0 mA DVDD18=1.8V DVDD18 6 mA Power Consumption 47 mW AVDD+DVDD AVDD=DVDD=3.6V 15 mA DVDD18=1.9V DVDD18 60 mA Reset (IRSTN pin = “L”), Power-down condition (Note 17, Note 18) AVDD+DVDD 1 10 μA DVDD18 3 200 μA Note 16. The Consumption of DVDD18 depends on the master clock frequency and the step size of the DSP program. (BITFS bit = “2h” and DSPS bit = “0”) Note 17. All digital input pins are fixed to each supply pin (DVDD or VSS1). Note 18. The condition of maximum values specifies Ta=Tmin~Tmax, AVDD=DVDD=3.0~3.6V and DVDD18=1.7~1.9V. MS1218-E-00-PB 2010/08 12 [AK7756] DIGITAL FILTER CHARACTERISTICS ■ ADC Block 1. fs=8kHz (Ta= Tmin~Tmax, AVDD= DVDD=3.0~3.6V, DVDD18=1.7~1.9V, VSS1=VSS2=0V; fs=8 kHz) Parameter Symbol min typ max Passband (±0.1dB) (Note 19, Note 20) PB 0 3.15 (-0.02dB) 3.63 (-3.0dB) 3.83 Stopband SB 4.66 Passband Ripple (Note 20) PR ±0.1 Stopband Attenuation (Note 21, Note 22) SA 68 Group Delay Distortion ΔGD 0 Group Deley (Ts=1/fs) GD 16 Note 19. The characteristic of the high pass filter is not included. Note 20. The passband is from DC to 3.15kHz Note 21. The stopband is 4.66kHz to 507.34kHz. Note 22. The analog modulator samples the input signal at 512kHz. 2. fs=16kHz (Ta= Tmin~Tmax, AVDD= DVDD=3.0~3.6V, DVDD18=1.7~1.9V, VSS1=VSS2=0V; fs=16 kHz) Parameter Symbol min typ max Passband (±0.1dB) (Note 23, Note 24) PB 0 6.3 (-0.02dB) 7.26 (-3.0dB) 7.66 Stopband SB 9.32 Passband Ripple (Note 24) PR ±0.1 Stopband Attenuation (Note 25,Note 26) SA 68 Group Delay Distortion ΔGD 0 Group Deley (Ts=1/fs) GD 16 Note 23. The characteristic of the high pass filter is not included. Note 24. The passband is from DC to 6.3kHz Note 25. The stopband is 9.32kHz to 1014.68kHz. Note 26. The analog modulator samples the input signal at 1024kHz. MS1218-E-00-PB Unit kHz kHz kHz kHz dB dB μs Ts Unit kHz kHz kHz kHz dB dB μs Ts 2010/08 13 [AK7756] ■ DAC Block 1. fs=8kHz (Ta= Tmin~Tmax, AVDD=DVDD= 3.0V ~ 3.6V, DVDD18= 1.7V ~ 1.9V; VSS1=VSS2=0V; fs=8 kHz) Parameter Symbol min typ max Unit Passband (±0.05dB) (Note 27) PB 0 3.62 kHz (-6.0dB) 4 kHz Stopband (Note 27) SB 4.37 kHz Passband Ripple PR ±0.01 dB Stopband Attenuation SA 64 dB Group Delay (Ts=1/fs) (Note 28) GD 24 Ts Digital Filter + Analog Filter Amplitude characteristic 20Hz~3.5kHz ±0.5 dB Note 27. Pass band and stop band parameters are related to sampling frequency (fs). PB=0.4535fs (at-0.05dB), SB=0.5465fs. Note 28. The digital filter’s delay is calculated as the time from setting 16-bit data into the input register until an analog signal is output. 2. fs=16kHz (Ta= Tmin~Tmax, AVDD=DVDD= 3.0V ~ 3.6V, DVDD18= 1.7V ~ 1.9V; VSS1=VSS2=0V; fs=16kHz) Parameter Symbol min typ max Passband (±0.05dB) (Note 27) PB 0 7.24 (-6.0dB) 8 Stopband (Note 27) SB 8.74 Passband Ripple PR ±0.01 Stopband Attenuation SA 64 Group Delay (Ts=1/fs) (Note 28) GD 24 Digital Filter + Analog Filter Amplitude characteristic 20Hz~7.0kHz ±0.5 MS1218-E-00-PB Unit kHz kHz kHz dB dB Ts dB 2010/08 14 [AK7756] SWITCHING CHARACTERISTICS ■ System Clock (Ta= Tmin~Tmax, AVDD=DVDD= 3.0V ~ 3.6V, DVDD18= 1.7V ~ 1.9V, VSS1=VSS2=0V, CL=20pF) Parameter Symbol min typ max Master operation a) XTI/XTO with a X’tal, External Clock input CKM[2:0]bits=6h(768x16KHz) fXTI 11.0 12.288 12.4 Duty Cycle 40 50 60 Slave mode operation LRCK Frequency fs 8 BICK Frequency fBICK Duty 0.1 40 ■ 32fs/48fs/64fs Unit MHz % 16 kHz 1.1 60 MHz % Reset (Ta= Tmin~Tmax, AVDD=DVDD=3.0~3.6V; DVDD18=1.7~1.9V; VSS1=VSS2=0V) Parameter Symbol min typ tRST 600 Reset pulse width (Note 29) Note 29. The IRSTN pin must be put to “H” after all power supplies are powered up. MS1218-E-00-PB max Unit ns 2010/08 15 [AK7756] ■ Digital Audio Interface (SDIN1, SDOUT1, 2) 1) SDIN1/2, SDOUT1/2/3 (Ta= Tmin~Tmax, AVDD=DVDD= 3.0V ~ 3.6V, DVDD18= 1.7V ~ 1.9V, VSS1=VSS2=0V, CL=20pF) Parameter Symbol min typ I2S and PCM Interface Input Timing Delay Time from BICK “↑” to LRCK (Note 30) tBLRD 20 Delay Time from LRCK to BICK “↑” (Note 30) tLRBD 20 Serial Data Input Latch Setup Time tBSIDS 80 Serial Data Input Latch Hold Time tBSIDH 80 Delay Time from LRCK to Serial Data Output (Note 31) tLRD Delay Time from BICK “↓” or “↑”to LRCK Output tBSOD 2 I S and PCM Interface Output Timing SDOUT1/2 BICK Frequency fBICK 64 BICK Duty cycle 50 Delay Time from BITCLK “↓” to LRCK Output tMBL -20 Serial Data Input Latch Setup Time tBSIDS 80 Serial Data Input Latch Hold Time tBSIDH 80 Delay Time from LRCK to Serial Data Output (Note 31) tLRD Delay Time from BICK “↓” or “↑”to LRCK Output tBSOD Note 30. BICK edge must not occur at the same time as LRCK edge. Note 31. Except I2S. MS1218-E-00-PB max Unit 80 80 ns ns ns ns ns ns 40 80 80 2010/08 16 fs % ns ns ns ns ns [AK7756] ■ μP Interface (SPI mode) (Ta= Tmin~Tmax; AVDD=DVDD=3.0~3.6V; DVDD18=1.7~1.9V, VSS1=VSS2=0V; CL=20pF) Parameter Symbol min typ max μP Interface Timing (SPI mode) RQN Fall Time tWRF 30 RQN Rise Time tWRR 30 SCLK Fall Time tSF 30 SCLK Rise Time tSR 30 SCLK Frequency fSCLK 2.1 SCLK Low Level Width tSCLKL 200 SCLK High Level Width tSCLKH 200 RQN High Level Width tWRQH 500 From RQN “↑” to IRSTN “↑” tRST1 600 From IRSTN “↑” to RQN “↓” tIRRQ 100 From RQN “↓” to SCLK “↓” tWSC 500 From SCLK “↑” to RQN “↑” tSCW 800 SI Latch Setup Time tSIS 200 SI Latch Hold Time tSIH 200 AK7756 → μP Delay Time from SCLK “↓”to SO Output tSOS 200 Hold Time from SCLK “↑” to SO Output (Note 32) tSOH 200 Note 32. Except when writing to the 8th bit of command code. ■ Unit ns ns ns ns MHz ns ns ns ns μs ns ns ns ns ns ns μP/EEPROM Interface (I2C BUS mode) (Ta= Tmin~Tmax; AVDD=DVDD=3.0~3.6V, DVDD18=1.7~1.9V, VSS1=VSS2=0V; CL=20pF) Parameter Symbol min typ max I2C Timing SCL clock frequency fSCL 400 Bus Free Time Between Transmissions tBUF 1.3 Start Condition Hold Time tHD:STA 0.6 (prior to first Clock pulse) Clock Low Time 1.3 tLOW Clock High Time 0.6 tHIGH Setup Time for Repeated Start Condition 0.6 tSU:STA SDA Hold Time from SCL Falling 0 0.9 tHD:DAT SDA Setup Time from SCL Rising 0.1 tSU:DAT Rise Time of Both SDA and SCL Lines 0.3 tR Fall Time of Both SDA and SCL Lines 0.3 tF Setup Time for Stop Condition 0.6 tSU:STO Pulse Width of Spike Noise Suppressed tSP 0 50 by Input Filter Capacitive load on bus Cb 400 2 Note 33. I C-bus is a trademark of NXP B.V. MS1218-E-00-PB Unit kHz μs μs μs μs μs μs μs μs μs μs ns pF 2010/08 17 [AK7756] ■ Timing Diagram 1/fXTI 1/fXTI tXTI=1/fXTI XTI VIH VIL 1/fs ts=1/fs 1/fs LRCK VIH VIL 1/fBICK 1/fBICK tBICK=1/fBICK VIH BICK VIL tBICKH tBICKL Figure 2. System Clock IRSTN tRST VIL Figure 3. Reset Timing Note 34. Set the IRSTN pin = “L” when power up and down the AK7756. MS1218-E-00-PB 2010/08 18 [AK7756] VIH VIL LRCK tBLRD tLRBD VIH VIL BICK tBSIDS tBSIDH VIH VIL SDIN1/2 Figure 4. Audio Interface (Slave Mode Input) VIH VIL LRCK tLRD VIH VIL BICK tLRD tBSOD SDOUT1/2/3 tBSOD 50%VDD Figure 5. Audio Interface (Slave Mode Output) MS1218-E-00-PB 2010/08 19 [AK7756] 50%DVDD LRCK tMBL tMBL BICK 50%DVDD tBSIDS tBSIDH VIH VIL SDIN1/2 Figure 6. Audio Interface (Master Mode Input) LRCK 50%DVDD tLRD BICK 50%DVDD tLRD tBSOD tBSOD SDOUT1/2/3 50%DVDD Figure 7. Audio Interface (Master Mode Output) MS1218-E-00-PB 2010/08 20 [AK7756] VIH RQN VIL tWRF tWRR tSF tSR VIH SCLK VIL tSCLKL tSCLKH 1/fSCLK 1/fSCLK VIH IRSTN VIL VIH RQN VIL tRST1 tIRRQ Figure 8. μP Interface 1 (SPI ) VIH RQN tWRQH VIL VIH SI VIL tSIS tSIH VIH SCLK VIL tWSC tSCW tWSC tSCW Figure 9. μP Interface 2 (SPI) MS1218-E-00-PB 2010/08 21 [AK7756] VIH SCLK VIL VIH SO VIL tSOH tSOS Figure 10. μP Interface 3 (SPI) VIH SDA VIL tBUF tLOW tR tHIGH tF tSP VIH SCL VIL tHD:STA Stop tHD:DAT tSU:DAT Start tSU:STA tSU:STO Start Stop Figure 11. μP Interface (I2C Bus) MS1218-E-00-PB 2010/08 22 [AK7756] PACKAGE (AK7756EN) 28Pin QFN (Unit: mm) 3.10 5.0±0.07 14 21 15 22 8 0.55±0.07 2.50 3.10 5.0±0.07 A 1 28 7 B 0.05 M 2.50 SAB C0.30 0.23±0.05 0.00~0.05 0.70 0.75MAX 0.05 S 0.5 0.05MAX [Detail A] A 0.12~0.18 S 0.18~0.28 Note: The exposed pad on the bottom surface of the package must be open or connected to the ground. ■ Package & Lead frame material Package molding compound: Epoxy Lead frame material: Cu Lead frame surface treatment: Solder (Pb free) plate MS1218-E-00-PB 2010/08 23 [AK7756] PACKAGE (AK7756VF) 0.45±0.20 -0.05 0.17 +0.06 30Pin VSOP (Unit: mm) 9.70±0.10 16 1 15 5.60±0.10 7.60±0.20 30 0.12 0.65 0°~8˚ M 0.30 0.24±0.06 ■ 10.00MAX 1.20±0.10 +0.10 -0.05 0.08 S 0.10 1.50MAX S Package & Lead frame material Package molding compound: Epoxy Lead frame material: Cu Lead frame surface treatment: Solder (Pb free) plate MS1218-E-00-PB 2010/08 24 [AK7756] MARKING (AK7756EN) 7756 XXXX 1 XXXX : Date code identifier (4 digits) MARKING (AK7756VF) AKM AK7756VF XXXBYYYYC 1) AKM Logo 2) Marketing Code: AK7756VF 3) Pin #1 identification 4) Date Code: XXXBYYYYC XXXB: Lot number (X: Digit number, B: Alpha character) YYYYC: Assembly date (Y: Digit number, C: Alpha character) MS1218-E-00-PB 2010/08 25 [AK7756] REVISION HISTORY Date (YY/MM/DD) 10/08/18 Revision 00 Reason First Edition Page Contents IMPORTANT NOTICE z These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei Microdevices Corporation (AKM) or authorized distributors as to current status of the products. z Descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application examples of the semiconductor products. You are fully responsible for the incorporation of these external circuits, application circuits, software and other related information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. z Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKM. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS1218-E-00-PB 2010/08 26 [AK7756] Thank you for your access to AKM products information. More detail product information is available, please contact our sales office or authorized distributors. MS1218-E-00-PB 2010/08 27